KR20000020316A - Method of manufacturing perpendicular fine pattern by using tri-layer resist of semiconductor device - Google Patents
Method of manufacturing perpendicular fine pattern by using tri-layer resist of semiconductor device Download PDFInfo
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- KR20000020316A KR20000020316A KR1019980038876A KR19980038876A KR20000020316A KR 20000020316 A KR20000020316 A KR 20000020316A KR 1019980038876 A KR1019980038876 A KR 1019980038876A KR 19980038876 A KR19980038876 A KR 19980038876A KR 20000020316 A KR20000020316 A KR 20000020316A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 12
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 5
- 239000011737 fluorine Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 25
- 239000010410 layer Substances 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 239000007789 gas Substances 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 description 5
- 229920000642 polymer Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 230000000171 quenching effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- General Chemical & Material Sciences (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 삼중 구조의 감광막(Tri-layer resist)을 이용한 미세 패턴 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a fine pattern using a tri-layer resist.
일반적으로, 반도체 소자의 집적도가 증가함에 따라 포토 공정시 패턴의 기하학적 형태에 의한 노칭(notching), 밀도 차이에 의한 근사효과(proximity effect), 타포러지(topology)에 기인한 촛점심도 차이에 의해 발생하는 넥킹(necking) 및 브리지(bridge) 문제점을 방지하고자 TLR공정의 필요성이 대두되어 왔다.In general, as the degree of integration of a semiconductor device increases, it is caused by notching due to the geometrical shape of the pattern during the photolithography process, approximation effect due to density difference, and depth of focus due to topology. The need for a TLR process has emerged to prevent necking and bridge problems.
도 1은 종래의 질화막 베리어 SAC(Self-Aligned Contact) 관련 폴리실리콘 게이트 형성을 위한 TLR공정시 나타난 경사 프로파일을 나타낸 도면으로, 도면에서 도면부호 1은 불순물 주입된 폴리실리콘 게이트, 2는 텅스텐 실리사이드막, 3은 하드 마스크 산화막(hard mask oxide)으로 사용되는 중온 산화막(MTO:middle thermal oxide)을 각각 나타내고 있다.1 is a view showing the inclination profile of the conventional nitride film barrier SAC (Self-Aligned Contact) related polysilicon gate formation, in which reference numeral 1 is an impurity-injected polysilicon gate, 2 is a tungsten silicide layer 3 denotes a middle thermal oxide (MTO) used as a hard mask oxide.
도면에 도시된 바와 같이, 종래의 폴리실리콘 게이트 형성 방법은 후속공정에서 증착되는 콘택 전도층과 하드 마스크 산화막 하부의 텅스텐 실리사이드(2)와의 단락을 방지하기 위한 질화막 베리어 SAC 공정의 마진확보를 위해 중온 산화막(3)의 측면(4)을 경사지게 형성하고 있다.As shown in the figure, the conventional polysilicon gate forming method is a medium temperature to secure the margin of the nitride barrier SAC process to prevent a short circuit between the contact conductive layer deposited in the subsequent process and the tungsten silicide (2) under the hard mask oxide film The side surface 4 of the oxide film 3 is formed to be inclined.
그러나, 상기 종래의 폴리실리콘 게이트 형성 방법은, 후속 단계에서 질화막 베리어 SAC 공정마진을 확보하기 위하여는 하드 마스크 산화막의 두께가 높아져야하고, 이에 따라 TLR 공정시 MTO막에 발생한 기울기는 하부 층과의 단락을 유발하여 소자의 신뢰성을 저하시키는 문제점이 따랐다.However, in the conventional polysilicon gate forming method, the thickness of the hard mask oxide layer must be increased in order to secure the nitride barrier SAC process margin in a subsequent step, so that the slope of the MTO film during the TLR process is short-circuited with the underlying layer. The problem of deteriorating the reliability of the device was caused.
상기 문제점을 해결하기 위하여 안출된 본 발명은 하부층과의 단락을 방지하여 반도체 소자의 신뢰도를 향상시킬 수 있는 삼층구조의 감광막을 이용한 수직한 미세 패턴 제조 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a vertical fine pattern manufacturing method using a three-layer photosensitive film that can improve the reliability of the semiconductor device by preventing a short circuit with the lower layer.
또한, 본 발명은 TLR구조의 감광막 패턴형성에 있어서 수직한 프로파일의 패턴을 형성하여 반도체 소자의 신뢰성을 향상시킬 수 있는 삼층구조의 감광막을 이용한 수직한 미세 패턴 제조 방법을 제공하는데 그 목적이 있다.In addition, an object of the present invention is to provide a vertical fine pattern manufacturing method using a three-layer photosensitive film that can improve the reliability of the semiconductor device by forming a pattern of the vertical profile in forming a photosensitive film pattern of the TLR structure.
도 1은 종래의 질화막 베리어 SAC 관련 폴리실리콘 게이트 형성을 위한 TLR공정시 나타난 경사 프로파일을 나타낸 도면,1 is a view showing a tilt profile shown in the TLR process for forming a conventional silicon film barrier SAC-related polysilicon gate,
도 2a 내지 도 2e는 본 발명에 따른 폴리실콘 게이트 형성을 위한 MTO막 패턴 제조 공정도,2a to 2e is an MTO film pattern manufacturing process for forming a polysilicon gate according to the present invention,
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11: 폴리실리콘막 12: 텅스텐 실리사이드11: polysilicon film 12: tungsten silicide
13: MTO막 14: 하층 레지스트13: MTO film 14: lower layer resist
15: 저온 산화막15: low temperature oxide film
본 발명은 반도체 소자의 폴리실리콘 게이트 관련 TLR공정으로 식각시 발생되는 하드마스크(MTO)의 경사를 O2가스 증가 및 RF전원 증가에 의한 Ar 스퍼터링을 이용하여 수직한 프로파일을 형성하는 공정으로 O2증가에 의한 폴리머 제거로 경사를 최소화시키며, RF전원 증가로 Ar 스퍼터링 양을 증가시켜 패턴 가장자리에서 튀어나오는 Ar이 측면식각을 실시함으로써 MTO의 경사를 억제한다.The present invention is a process for forming a vertical profile of the hard mask (MTO) generated during the etching of the polysilicon gate-related TLR process of the semiconductor device by using the Ar sputtering by O 2 gas increase and RF power increase O 2 The removal of the polymer by the increase minimizes the inclination. The increase of the RF power increases the amount of Ar sputtering, and the Ar protruding from the pattern edge suppresses the inclination of the MTO.
따라서, 본 발명은, 전도층을 형성하는 단계; 상기 전도층 상에 MTO막을 형성하는 단계; 상기 MTO막 상에 산화막을 포함하는 TLR막을 형성하는 단계; 및 상기 TLR막 하층 레지스트 패턴을 식각마스크로 사용하여 Ar, O2및 불소계열 플라즈마 가스로 상기 MTO막 패턴을 형성하되 O2가스 증가 및 RF전원 증가를 통해 상기 Ar을 스퍼터링되도록 하여 상기 MTO막의 측면을 식각하는 단계를 포함한다.Thus, the present invention comprises the steps of forming a conductive layer; Forming an MTO film on the conductive layer; Forming a TLR film including an oxide film on the MTO film; And forming the MTO film pattern using Ar, O 2, and fluorine-based plasma gas using the TLR film lower resist pattern as an etch mask, but allowing the Ar to be sputtered by increasing O 2 gas and increasing RF power. Etching a.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
먼저, 도 2a에 도시된 바와 같이, 본 발명에 따른 폴리실리콘 게이트 형성을 위한 TLR공정은 불순물이 주입된 폴리실리콘막(11), 텅스텐 실리사이드막(12)이 차례로 형성한다. 그리고, 1500∼2000Å의 MTO막(13)을 상기 텅스텐 실리사이드막(12) 상에 형성한 후, TLR공정을 수행하기 위하여 상기 MTO막(13) 상에 1.0∼1.2μm의 하층 감광막(I-line)(14), 1000∼1200Å의 저온 산화막(15) 및 0.4∼0.6μm의 DUV(deep UV) 감광막(16)을 차례로 형성하는데, 후속 공정에서 진행되는 전도층의 콘택물질과 게이트 전극의 전기적 접촉을 방지하기 위하여 MTO막(13)의 두께를 두껍게 한다. 한편, 도 3은 본 발명에서 사용되는 상기 MTO막의 큐닝후 구조도를 보여주고 있다.First, as shown in FIG. 2A, in the TLR process for forming a polysilicon gate according to the present invention, a polysilicon film 11 into which impurities are injected and a tungsten silicide film 12 are sequentially formed. Then, after forming an MTO film 13 of 1500 to 2000 microns on the tungsten silicide film 12, a lower photoresist film (I-line) of 1.0 to 1.2 μm on the MTO film 13 to perform the TLR process. (14), a low temperature oxide film 15 of 1000 to 1200 Å, and a deep UV (DUV) photosensitive film 16 of 0.4 to 0.6 µm are sequentially formed. In order to prevent the thickness of the MTO film 13 is thickened. On the other hand, Figure 3 shows a structural diagram after the quenching of the MTO film used in the present invention.
이어서, 도 2b에 도시된 바와 같이, DUV감광막(16) 패턴을 형성한후 Ar/CHF3/O2가스를 가지는 식각가스를 이용하여 저온 산화막(Interlayer PE oxide)(15) 패턴을 형성한다. 이 저온 산화막(15)의 식각은 압력, RF 전원 500W이상, 자장 50Gauss 이상, Ar은 100-150sccm정도, CHF3은 50∼70sccm정도, O2는 20∼40sccm정도에서 공정이 진행된다.Subsequently, as shown in FIG. 2B, after forming the DUV photosensitive film 16 pattern, an interlayer PE oxide 15 pattern is formed using an etching gas having an Ar / CHF 3 / O 2 gas. The etching of the low temperature oxide film 15 is performed at a pressure, an RF power of 500 W or more, a magnetic field of 50 Gauss or more, an Ar of about 100-150 sccm, a CHF 3 of about 50 to 70 sccm, and an O 2 of about 20 to 40 sccm.
그리고, 도 2c에 도시된 바와 같이, 저온 산화막(15) 패턴을 식각 마스크로하여 하층 감광막(14) 패턴을 형성하는데, RF전원 500W이하, 자장 50Gauss 이하, Ar은 20∼40sccm정도, O2는 20∼40sccm정도에서 수행된다.As shown in FIG. 2C, the lower photosensitive layer 14 pattern is formed using the low temperature oxide layer 15 pattern as an etch mask. An RF power source is 500W or less, a magnetic field of 50 Gauss or less, Ar is about 20 to 40 sccm, and O2 is about 20 It is performed at about -40 sccm.
계속하여, 도 2d에 도시된 바와 같이, 하층 감광막(14) 패턴을 식각 마스크로하여 MTO막(13)의 패턴을 형성한다. Ar/CHF3/O2함유 가스 플라즈마로를 이용하여 MERIE(Magnetically Enhanced Reactive Ion Etcher)에서 MTO막(13)의 식각을 수행한다. 이때, O2증가에 의한 폴리머 제거로 경사를 최소화 시키며, RF전원 증가로 Ar 스퍼터링 양을 증가시켜 하층 감광막(1) 패턴의 가장자리에서 튀어나온 Ar이 측면식각을 실시함으로써 경사진 폴리머를 제거한다. 물론, 캐리어 가스로 사용되는 Ar은 기타 다른 중성 가스로, CHF3는 C4F8, CF4, SF6와 같은 기타 다른 불소계열 가스로 대체될 수 있을 것이다. 또한, MTO막(13)의 식각은 RF 전원 500W이상, 자장 50Gauss이상, Ar은 100∼150sccm정도, CHF3는 50∼70sccm정도, O2는 5∼10sccm정도에서 수행된다.Subsequently, as shown in FIG. 2D, the pattern of the MTO film 13 is formed using the lower photosensitive film 14 pattern as an etching mask. The MTO film 13 is etched in a MERIE (Magnetically Enhanced Reactive Ion Etcher) using an Ar / CHF 3 / O 2 -containing gas plasma furnace. At this time, the inclination is minimized by the removal of the polymer due to the increase of O 2 , and the amount of Ar sputtering is increased by the increase of the RF power, and the Ar protruding from the edge of the lower photosensitive layer 1 pattern is etched to remove the inclined polymer. Of course, Ar used as a carrier gas may be replaced with other neutral gas, and CHF 3 may be replaced with other fluorine-based gas such as C 4 F 8 , CF 4 , SF 6 . In addition, the etching of the MTO film 13 is performed at an RF power supply of 500 W or more, a magnetic field of 50 Gauss or more, Ar at about 100 to 150 sccm, CHF 3 at about 50 to 70 sccm, and O 2 at about 5 to 10 sccm.
끝으로, 상기 공정을 완료하게 되면, 도 2e에 도시된 바와 같은 수직한 MTO막(13) 패턴이 형성되어 이후의 공정에서 발생될 수 있는 전도층 간의 단락을 방지 할 수 있다.Finally, when the process is completed, a vertical MTO film 13 pattern as shown in FIG. 2E is formed to prevent a short circuit between conductive layers that may occur in a later process.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아니다. 또한, 본 발명의 기술분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다. 즉, MOS구조의 스페이서 제조시 사용되는 질화막의 스트레스 억제 방법 또는 반도체 제조 공정중 질화막을 사용하는 모든 공정 단계에 확대 적용 가능한 것으로써, 버퍼 산화막 증착의 단일 공정만 추가하여 현재 제조되고 있는 모든 집적 소자에 적용할 수 있다. 예를 들어 상기 MTO막은 반도체 소자의 층간 절연막으로 사용되어 양호한 패턴을 형성할 수 도 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above-described preferred embodiment, the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention. That is, it is widely applicable to the stress suppression method of the nitride film used in the manufacture of the spacer of the MOS structure or to all the process steps using the nitride film during the semiconductor manufacturing process, and all integrated devices currently manufactured by adding a single process of buffer oxide film deposition. Applicable to For example, the MTO film may be used as an interlayer insulating film of a semiconductor device to form a good pattern.
상기와 같이 이루어지는 본 발명은 본 발명을 사용하면 하드 마스크의 경사로 인한 후속 공정(nitride barrier SAC)시 발생되는 단락을 방지할 수 있어 소자의 신뢰성을 향상시키고, 소자의 수율을 증대시키는 효과가 있다. .The present invention made as described above can prevent the short circuit occurring during the subsequent process (nitride barrier SAC) due to the inclination of the hard mask has the effect of improving the reliability of the device, increase the yield of the device. .
Claims (7)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980038876A KR20000020316A (en) | 1998-09-19 | 1998-09-19 | Method of manufacturing perpendicular fine pattern by using tri-layer resist of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980038876A KR20000020316A (en) | 1998-09-19 | 1998-09-19 | Method of manufacturing perpendicular fine pattern by using tri-layer resist of semiconductor device |
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