KR20000019905A - Method for forming multi-layered line of semiconductor device - Google Patents
Method for forming multi-layered line of semiconductor device Download PDFInfo
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- KR20000019905A KR20000019905A KR1019980038251A KR19980038251A KR20000019905A KR 20000019905 A KR20000019905 A KR 20000019905A KR 1019980038251 A KR1019980038251 A KR 1019980038251A KR 19980038251 A KR19980038251 A KR 19980038251A KR 20000019905 A KR20000019905 A KR 20000019905A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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Abstract
Description
본 발명은 반도체 소자를 제조하는 공정에 있어서, 특히, 패턴 밀도가 높은곳에서의 금속 배선, 컨택홀(contact hole), 비아홀(via hole)등을 형성하는 다층 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layered wiring forming method for forming metal wirings, contact holes, via holes, and the like, particularly in places of high pattern density.
일반적으로, 반도체 소자의 고밀도화, 미세화, 및 배선 구조의 다층화에 따라 단차가 증가하게 되고, 사진 공정과 금속 배선 공정에 많은 문제를 유발하게 되었다. 예를들어 소정의 금속 패턴은 Al, Cu, W와 같은 금속을 증착한후, RIE(Reactive Ion Etch) 공정을 통해 패턴을 형성하고, 층간 절연막으로 산화막을 금속 배선 사이에 증착하는 공정을 통해 형성되는데, 상술한 공정에서는 금속의 오버-에칭(over etching)이 필요하고, 표면단차가 발생하며, 금속 배선 사이의 작은 공간을 산화막으로 채우기 어렵다. 또한 층간 산화막을 증착하는 동안 열응력이 발생하여 배선 신뢰도를 저하시킨다.In general, the step height is increased due to the high density of semiconductor elements, the miniaturization, and the multilayered wiring structure, which causes many problems in the photolithography process and the metal wiring process. For example, a predetermined metal pattern is formed by depositing metals such as Al, Cu, and W, forming a pattern through a reactive ion etching (RIE) process, and depositing an oxide film between metal wires using an interlayer insulating film. In the above-described process, overetching of the metal is required, a surface step occurs, and it is difficult to fill a small space between the metal wirings with an oxide film. In addition, thermal stress is generated during deposition of the interlayer oxide film, thereby lowering wiring reliability.
이를 극복하기 위해 현재 많은 반도체 소자 생산 업체에서는 다층 배선 형성시, 다마신(Damascene) 공정을 사용하고 있다. 도 1 에는 다마신 공정에 의한 다층 배선 형성 공정이 도시된다.To overcome this, many semiconductor device manufacturers are using the damascene process in forming multilayer wiring. 1 shows a multilayer wiring formation process by a damascene process.
도 1을 참조하면, 트랜지스터 소자, 또는 금속 배선막과 같은 집적회로가 형성된 반도체 기판(11) 상에 절연막(12)을 형성한후, 소정의 에치 과정을 통해 절연막에 배선을 매립할 소정의 패턴을 형성한다. 이후, 티타늄/질화 티타늄(Ti/TiN)(13)을 증착하고, 금속막(14)을 증착하는데(도 1a 참조), 여기에서 금속막(14)은 금속 배선용, 비아 홀용, 또는 컨택홀용으로 사용하기 위한 것으로, 주로 알루미늄(Al), 구리(Cu), 텅스턴(W)등이 이용된다.Referring to FIG. 1, after the insulating film 12 is formed on a semiconductor substrate 11 on which a transistor element or an integrated circuit such as a metal wiring film is formed, a predetermined pattern for embedding wiring in the insulating film through a predetermined etch process To form. Thereafter, a titanium / titanium nitride (Ti / TiN) 13 is deposited and a metal film 14 is deposited (see FIG. 1A), where the metal film 14 is used for metal wiring, via holes, or contact holes. In order to use, mainly aluminum (Al), copper (Cu), tungsten (W), etc. are used.
CMP(Chemical Mechanical Polishing) 공정을 통해, 금속 배선 패턴만을 남긴채, 절연막(12) 위쪽에 있는 금속막(14)을 제거한다. 절연막(12) 위쪽의 잔류 금속막, 즉, 티타늄/질화 티타늄층(13) 및 금속막(14)을 완전히 제거하기 위해서는 절연막(12)이 노출된 후에도 얼마간 연마를 계속하는 오버 폴리싱(over polishing)이 필요하다.Through the chemical mechanical polishing (CMP) process, the metal film 14 over the insulating film 12 is removed while leaving only the metal wiring pattern. In order to completely remove the remaining metal film on the insulating film 12, that is, the titanium / titanium nitride layer 13 and the metal film 14, over polishing is continued for some time after the insulating film 12 is exposed. This is necessary.
그런데, 금속막 CMP를 수행하기 위한 연마액은 그 특성상 금속막(14)은 잘 연마하지만 절연막(12)은 잘연마하지 못한다. 따라서, 오버 폴리싱을 하게되면, 도 1b에 도시된 바와 같이, 금속 배선의 패턴 밀도가 높은곳에서는, 절연막의 표면적에 비해 금속이 차지하는 표면적율이 상대적으로 높기 때문에 연마속도가 빠르고(도 1b의 우측), 절연막의 표면적에 비해 금속이 차지하는 표면적율이 상대적으로 낮은 도 1b의 좌측은 연마 속도가 느리다. 그 결과로, 금속 배선의 패턴 밀도가 높은곳에서 매몰 현상이 발생하게 되고, 이는 반도체 소자의 평탄도 및 균일도의 저하를 초래하며, 금속 배선 패턴 밀도에 따른 금속 배선의 두께가 달라져서 금속 배선의 신뢰도를 저하시키는 요인으로 작용하였다.By the way, in the polishing liquid for performing the metal film CMP, the metal film 14 is polished well, but the insulating film 12 is not polished well. Therefore, when overpolishing, as shown in FIG. 1B, where the pattern density of the metal wiring is high, the polishing rate is fast because the surface area ratio of the metal is relatively high compared to the surface area of the insulating film (right side of FIG. 1B). ), The left side of FIG. 1B having a relatively low surface area ratio of metal compared to the surface area of the insulating film has a low polishing rate. As a result, the buried phenomenon occurs in the place where the pattern density of the metal wiring is high, which causes the flatness and uniformity of the semiconductor element to decrease, and the thickness of the metal wiring varies according to the metal wiring pattern density, so that the reliability of the metal wiring is changed. It acted as a factor to lower the.
따라서, 최근에 개발된 방법(February 13-14, 1997 CMP-MIC Conference 1997 ISMIC200P/97/0415 참조)으로는 두단계의 연마를 통해 매몰 현상을 방지하고 있다. 우선, 금속 연마용 연마액, 예를들어 Al2O3을 주성분으로 한 연마액을 이용하여 시드(seed)층으로 사용되는 티타늄층(13)까지 연마한다. 이후 오버 폴리싱을 할 때에는 절연막 연마용 연마액, 예를들어 SiO2을 주성분으로 한 연마액을 이용하여 연마함으로서, 매몰 현상을 방지하고 있다. 그러나, 이러한 공정은 매몰 현상을 줄일수는 있지만 상술한 바와 같이, 두 번의 공정을 거쳐야하기 때문에 공정 복잡성이 증가하고, 공정 마진(margin)이 줄어드는 또다른 문제점을 가지고 있으며, 더불어 생산성이 떨어지고, 공정 비용 상승을 유발한다.Therefore, the recently developed method (see Febuary 13-14, 1997 CMP-MIC Conference 1997 ISMIC200P / 97/0415) prevents the buried phenomenon through two-step polishing. First, polishing is performed to a titanium layer 13 used as a seed layer using a polishing liquid mainly composed of metal polishing, for example, Al 2 O 3 . Subsequently, when overpolishing, polishing is performed using a polishing liquid for insulating film polishing, for example, a polishing liquid containing SiO 2 as a main component, thereby preventing the burial phenomenon. However, this process can reduce the investment phenomenon, but as described above, it has to go through two processes, which increases the complexity of the process, has another problem of decreasing the process margin, and also decreases the productivity. It causes an increase in costs.
따라서, 본 발명은 상술한 종래 기술의 문제점을 해결하기 위한 것으로, 단순한 공정을 통하여 오버 폴리싱으로 인한 매몰 현상을 방지할수 있는 다층 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a multi-layered wiring which can prevent the buried phenomenon due to over polishing through a simple process.
상기 목적을 달성하기 위한 본 발명은, 다층 배선 구조의 반도체 소자를 형성하는 다층 배선 형성 방법에 있어서: 집적회로가 형성된 반도체 기판상에 서로 다른 식각 선택비를 갖는 제 1 절연막 및 제 2 절연막을 순차적으로 적층하는 제 1 단계; 상기 제 2 절연막 및 제 1 절연막의 일부를 순차적으로 패터닝하여 금속 배선을 매립할 소정 영역에 패턴을 형성하는 제 2 단계; 상기 패턴을 형성한후 전면에 금속을 적층하는 제 3 단계; 상기 금속의 일부 및 제 2 절연막을 제거하여, 상기 제 1 절연막에 의해 전기적으로 서로 격리된 다수개의 금속층을 형성하는 제 4 단계; 상기 다수개의 금속층 각각에 일대일 대응되게 전기적으로 접속되는 다수개의 상부 전극을 형성하는 제 5 단계를 포함하여 이루어짐을 특징으로 한다.SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method for forming a multilayer wiring structure for forming a semiconductor device having a multilayer wiring structure: sequentially forming a first insulating film and a second insulating film having different etching selectivity on a semiconductor substrate on which an integrated circuit is formed. First step of laminating with; A second step of sequentially patterning a portion of the second insulating film and the first insulating film to form a pattern in a predetermined region to fill the metal wiring; A third step of laminating a metal on the front surface after forming the pattern; Removing a portion of the metal and the second insulating film to form a plurality of metal layers electrically isolated from each other by the first insulating film; And a fifth step of forming a plurality of upper electrodes electrically connected to each of the plurality of metal layers in a one-to-one correspondence.
도 1은 종래 기술의 다층 배선 형성 방법을 나타낸 공정 순서도,1 is a process flowchart showing a method for forming a multilayer wiring of the prior art;
도 2는 본 발명의 바람직한 실시예에 따른 다층 배선 형성 방법을 나타낸 공정 순서도.2 is a process flowchart showing a method for forming a multilayer wiring according to a preferred embodiment of the present invention.
＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
110 : 반도체 기판 120: 제 1 절연막110 semiconductor substrate 120 first insulating film
130 : 제 2 절연막 140 : 장벽 금속막130: second insulating film 140: barrier metal film
150 : 금속막150: metal film
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대하여 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 2 에는 본 발명의 실시예에 따른 다층 배선 형성 방법을 나타낸 공정 순서도가 도시된다.2 is a process flowchart showing a method for forming a multilayer wiring according to an embodiment of the present invention.
도 2를 참조하면, 트랜지스터 소자, 또는 금속 배선막과 같은 집적회로가 형성된 반도체 기판(110)상에 제 1 절연막(120)을 증착한다. 이때, 제 1 절연막(120)으로는 금속막 CMP공정시 폴리싱(polishing)이 되지 않는 것을 특징으로 하는 플라즈마 CVD 절연막등을 이용한다. 이후, 본 발명의 가장 특징점이라 할수 있는 제 1 절연막(120)위에 제 2 절연막(130)을 얇게, 바람직하기로는 200Å 내지 2000Å 두께로 증착한다(도 2a 참조). 여기에서, 제 2 절연막(130)은 금속막 CMP공정시 폴리싱이 잘되는 물질, 예를들어, BPSG, PSG,BSG, SiO2, SOG(Spin On Glass)류의 물질로 형성함이 바람직하다(도 2a).Referring to FIG. 2, a first insulating layer 120 is deposited on a semiconductor substrate 110 on which a transistor element or an integrated circuit such as a metal wiring layer is formed. In this case, the first insulating film 120 is a plasma CVD insulating film or the like, which is not polished during the metal film CMP process. Thereafter, the second insulating film 130 is thinly deposited on the first insulating film 120, which is the most characteristic point of the present invention, and is preferably 200 Å to 2000 Å thick (see FIG. 2A). Here, the second insulating film 130 is preferably formed of a material that is well polished in the metal film CMP process, for example, BPSG, PSG, BSG, SiO 2 , or SOG (Spin On Glass) materials (FIG. 2a).
소정의 에치 공정을 통해 금속 배선 패턴을 형성한후, 장벽 금속막(140)과 금속막(150)을 순차적으로 적층하는데(도 2b 참조), 장벽 금속막(140)은 티타늄/질화 티타늄(Ti/TiN)이나, WN으로 형성한다. 또한 금속막(150)은 금속 배선용, 비아 홀용, 또는 컨택홀용으로 사용하기 위한 것으로, 식각 선택비가 제 1 절연막(120)보다 높고, 제 2 절연막(130)과 같거나 낮은 물질, 예를들어 알루미늄(Al), 구리(Cu), 텅스턴(W) 등으로 형성함이 바람직하다. 즉, 제 1 절연막(120)은 금속막(150)보다 식각 선택비가 낮은 물질로 구성하고, 제 2 절연막(130)은 식각 선택비가 금속막(150)과 같거나 낮은 물질로 구성한다.After the metal wiring pattern is formed through a predetermined etch process, the barrier metal film 140 and the metal film 150 are sequentially stacked (see FIG. 2B). The barrier metal film 140 is formed of titanium / titanium nitride (Ti). / TiN) or WN. In addition, the metal layer 150 is used for metal wiring, via hole, or contact hole, and has an etching selectivity higher than or equal to that of the first insulating layer 120 and lower than or equal to the second insulating layer 130, for example, aluminum. It is preferable to form with (Al), copper (Cu), tungsten (W), etc. That is, the first insulating layer 120 is made of a material having a lower etching selectivity than the metal film 150, and the second insulating layer 130 is made of a material having an etching selectivity lower than or equal to the metal film 150.
CMP(Chemical Mechanical Polishing) 공정을 통해, 상측의 금속막(150), 장벽 금속막(140), 제 2 절연막(130)을 순차적으로 제거한후, 제 1 절연막(120)이 표면에 드러나게 되면 연마를 즉시 멈춘다(도 2c 참조). 여기에서, 제 1 절연막(120)이 표면에 드러나는지를 확인하기 위해서 EPD(End Point Detection) 시스템을 적용함이 바람직하며, EPD시스템으로는 광학 EPD, 모터 전류 EPD시스템을 적용한다.Through the chemical mechanical polishing (CMP) process, the upper metal film 150, the barrier metal film 140, and the second insulating film 130 are sequentially removed, and then polishing is performed when the first insulating film 120 is exposed to the surface. Stop immediately (see FIG. 2C). Here, it is preferable to apply an end point detection (EPD) system to check whether the first insulating film 120 is exposed on the surface, and an optical EPD and a motor current EPD system are applied as the EPD system.
따라서, 금속막CMP공정에 있어서, 제2절연막(130)으로 사용된 물질이 제1절연막(120)보다 연마가 빠르게 진행되는 반면, 제1절연막(120)의 연마는 비교적 느리게 진행되어, 제1절연막(120)에 대한 오버 폴리싱을 방지하게 된다. 또한 제2절연막(130)으로 사용된 물질이 제1절연막(120)의 물질 특성과는 다른 물질일 경우, 제2절연막(120)에 비해 제2절연막(130)에 높은 식각 선택비, 예를들어 5:1의 식각 선택비를 갖는 연마액을 이용하여 CMP 공정을 수행함으로서, 제1절연막(120)에 대한 오버 폴리싱을 방지하게 된다.Therefore, in the metal film CMP process, the material used as the second insulating film 130 is polished faster than the first insulating film 120, while the polishing of the first insulating film 120 is relatively slow, and thus the first It is possible to prevent overpolishing of the insulating film 120. In addition, when the material used as the second insulating layer 130 is a different material from that of the first insulating layer 120, the etching selectivity higher than that of the second insulating layer 120 may be higher than that of the second insulating layer 120. For example, by performing a CMP process using a polishing liquid having an etching selectivity of 5: 1, overpolishing of the first insulating layer 120 is prevented.
즉, 상부의 금속막(150)과 장벽 금속막(140)이 연마되고 나면, 제2절연막(130)이 드러나는데, 이때, 제2절연막(130)이 금속막(150) 및 제1절연막(120)보다 훨씬 연마가 잘되므로, 금속 배선의 패턴 밀도가 낮은곳에서의 제2절연막(130)이 금속 배선의 패턴 밀도가 높은곳에서의 제2절연막(130)보다 빠르게 연마된다 할지라도, 금속 배선 패턴 밀도가 높은곳에 위치한 금속막(150) 및 제1절연막(120)이 금속 배선의 패턴 밀도가 낮은곳에서의 제2절연막(130)보다 훨씬 느리게 연마되므로, 오버 폴리싱을 방지할수 있는 것이다.That is, after the upper metal film 150 and the barrier metal film 140 are polished, the second insulating film 130 is exposed. In this case, the second insulating film 130 is formed of the metal film 150 and the first insulating film ( Since the polishing is much better than that of 120, even if the second insulating film 130 where the pattern density of the metal wiring is low is polished faster than the second insulating film 130 where the pattern density of the metal wiring is high, Since the metal film 150 and the first insulating film 120 positioned at the high wiring pattern density are polished much slower than the second insulating film 130 at the low pattern density of the metal wiring, overpolishing can be prevented.
또한, 제1절연막(120)의 표면이 드러나지 않고, 제2절연막(130)의 잔류물이 남은 상태에서 연마를 중단할지라도, 소자간 단락을 유발하지 않게된다.In addition, even if the surface of the first insulating film 120 is not exposed and the polishing is stopped while the residue of the second insulating film 130 remains, the short circuit between the devices is not caused.
이와 같이하여 제1절연막(120)에 의해 전기적으로 서로 격리된 다수개의 금속층이 형성되면, 각 금속층에 전기적으로 접속되는 다수개의 상부 전극을 일대일 대응되게 형성하여 다층 배선 구조의 반도체 소자를 제조한다.When a plurality of metal layers electrically isolated from each other by the first insulating layer 120 are formed in this way, a plurality of upper electrodes electrically connected to the respective metal layers are formed in one-to-one correspondence to manufacture a semiconductor device having a multi-layered wiring structure.
이와 같이, 본원 발명은 층간 절연막과 티타늄/질화 티타늄막 사이에, 층간 절연막보다 연마비가 높은 절연층을 형성하여 CMP를 수행함으로서, 티타늄/질화 티타늄막은 완전히 제거되는 반면, 오버 폴리싱을 하지 않아도 되기 때문에 매몰 현상을 방지할수 있게 된다.As described above, according to the present invention, since the CMP is performed between the interlayer insulating film and the titanium / titanium nitride film by forming an insulating layer having a higher polishing ratio than the interlayer insulating film, the titanium / titanium nitride film is completely removed but does not require overpolishing. It is possible to prevent the investment phenomenon.
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