TW529091B - A slot via filled dual damascene structure without middle stop layer and method for making the same - Google Patents

Abstract

An interconnect structure and method of forming the same in which a diffusion barrier/etch stop layer (22) is deposited over a conductive layer (20). An organic low k dielectric material (24) is deposited over the diffusion barrier/etch stop layer (22) to form a first dielectric layer (24). The first dielectric layer (24) is etched to form a slot via (50) in the first dielectric layer (24). An inorganic low k dielectric material (30) is deposited within the slot via (50) and over the first dielectric layer (24) to form a second dielectric layer (30) over the slot via (50) and the first dielectric layer (24). The re-filled via (50) is simultaneously etched with the second dielectric layer (30) in which a trench (38) is formed. The trench (38) extends in a direction that is normal to the length of the slot via (50). The entire width of the trench (38) is directly over the via (36). The re-opened via and the trench (38) are filled with a conductive material (40). In other embodiment, the first dielectric layer 24 comprises an inorganic low k dielectric layer and the second dielectric layer 30 comprises an organic low k dielectric layer.

Description

529091 V. Description of the invention (1) [Technical Field] The present invention is especially in the connection area. [Background] The continuous increase in super efficiency and we find that this provides low-resistance through-hole contacts in time, especially the traditional Into a semiconductor pattern. The formation of such conductive patterns is usually achieved by using (ie, upper plugs to establish electrical contacts with half.) Semiconductor crystals that are scaled down to approximately the same size are usually in layers, and then related to the metal wiring layer when manufacturing semiconductor devices. Zhixingguan uses a through-hole filling two-channel metal damascene technology to form a metal damascene structure in gold. In addition to the demand for large integrated circuits, the type of capacitance must be increased-RC: The trench has the above-mentioned conditions. The substrate and the complex circuit, which include the conductors on the conductive substrate on which the vias are filled to fill the vias and the lower layer), form a layer of semiconductor-based micrometers in the trenches. A conventional lithography semiconductor is used to obtain wiring patterns that are difficult to meet due to the wiring technology requirements. The size of the wiring pattern is small. It often includes several circuits that are formed in sequence to form a integrated circuit. The conductive pattern 'and the active area (such as conductive lines, and the way the material extends, so it is common to include five layers. Conductive pattern guidance and engraving techniques There is a corresponding change in the associated high density. This is sufficient because it is necessary to fill the source isotopes of the electrical complexes doped with large aspect ratios, especially at submicrons, or A single junction dielectric is connected to the conductive pattern formed by the contact / drain conductive layer due to the multilayer crystal chip layer and the polar circuit device metal of the different holes of the electric wire. Formed in the dielectric layer

92022.ptd Page 7 529091 V. Description of the invention (2) Open the hole, and then fill the opening with a conductive material such as tungsten (W) to form a conductive plug that fills the through hole. Chemical mechanical grinding

(Chemical Mechanical Polishing; CMP for short) technology to remove excess conductive material on the surface of the dielectric layer. One such method is called damascene, and damascene technology basically involves the following steps: forming an opening in the dielectric layer; and filling the opening with metal. The dual metal damascene technique involves the following steps: forming an opening including a lower-level contact area or a via portion, and the low-level contact area is connected to an upper trench portion, and then filled with a conductive material that is usually metal The opening is used to form a conductive plug and a conductive line in electrical contact with the conductive plug at the same time.

High-performance microprocessor applications require semiconductor circuits to be fast. The control speed of the semiconductor circuit changes inversely with the resistance and capacitance values of the wiring pattern. As the integrated circuit becomes more complicated and the microstructure size and interval become smaller, the speed of the integrated circuit becomes less dependent on the transistor itself 'and more dependent on the wiring pattern. Miniaturization requires long connections with small contacts and small cross sections. Therefore, the wiring pattern limits the speed of the integrated circuit. If the connection node is routed for a relatively long distance (for example, a distance of several hundred micrometers or more in the sub-micron technology), then the connection capacitance value limits the load of the circuit node capacitance value, and because the circuit is limited speed. When the sub-micron design rule (for example, a design rule of about 0.1 micron or less) is used to increase the element density and reduce the size of the microstructure, the quality failure rate of the integrated circuit is delayed by 4 1 Significantly limits the output rate and significantly increases ^ ^

92022.ptd Page 8 529091 V. Description of the invention Cost. Prior line. The selected material is more than tungsten, and the wiring is formed below the simultaneous deposition of the system to cover the hole and the trench. The etch stop dielectric layer is a layer such as a through pattern etched in the middle. Then, the microstructure is hardly masked, and the through-hole stratification of two dielectrics with the same etchant is performed. The aluminum alloy is used to attract attention to the gas characteristics. It is usually in the sedimentation product, and the bottom hole and the first interstitial structure are etched in the second, second, and etched dielectrics in a fine manner. The dielectric layer is reduced. The metal deposition masks such as the number of engraved wires connected to the medium-sized ultra-large integrated circuits are now connected to gold. These aluminum circuits in aluminum metal have a lower resistivity and are used as conductive plugs and When the conductive metal is inlaid, the wiring is connected to the previous shape. A conductive material is deposited to make a hole (such as through the bottom of the conductive connection layer. Then the copper and copper before the first (3), a relatively good electricity is an automatic convolution of a conductive conductive layer) in. After the layer sinks the barrier layer holes, etc., it can be on the layer and the. The system that continues to form within the agent of the first stratum is used to replace. The copper ratio makes the copper genus. The formation of an electrical barrier and a layer covered with an electrical element dielectric material will be used as the etch resist layer on the resist layer. In this way, a second double-lane with a protective barrier layer is manufactured to protect the dielectric material layer from the through-hole material. Then the etch produced a hard etch on the barrier layer, which was conductive with the first step. Using the dielectric layer pattern #, the first electrical etch is the second electrical capping layer. Ditches and other dielectric layers. Then the grooves in the layer are etched to the dielectric layer, and the barrier layer dielectric is etched through the desired same with a non-conductive material and a dielectric channel, and

92022.ptd Page 9 529091 V. Description of the invention (4) _ In the earlier deposition step, η + material. (If copper is used: deposit a barrier layer of conductive material in the through hole and the trench to prevent 1 :: as a conductive material, and m will first sink the tomb steel in the wiring layer in a traditional manner.) The The conductive material can be connected to the lightning conductor below: the conductive material in has electrical contact. V-Electricity will be a low-k dielectric. The efficiency of the work has been studied by more and more people now. Reducing the metal wire used to replace the higher-k dielectric material will reduce the Rra of the wafer. When the overall k value of the dielectric layer is used, such as benzocyclobutene (f), the efficiency of the wafer is improved. (HSQ), silicon oxyfluoride ^) 'hydrogen silseQUio × Xane Traditionally, k: low-k materials are often more difficult to handle than the pattern of layers such as oxides. For example, a k-value dielectric material is being produced. / Photoresistive material technology is easy to damage the inorganic low, it may be damaged in: organic = photoresistive layer used to form trenches. This is based on the traditional formula; the fine junctions formed in the low-k dielectric layer, H m ^ in a two-lane metal damascene configuration, special care must be taken: change :: because 1 will be involved in lower through holes The inorganic material in the layer has two through-hole layers; when the photoresist of the through-hole is formed, the first time is lost and the material is removed. Another area of improvement that compromises the same non-defective layer embedding configuration in the via layer is the use of an intermediate etch stop layer between the lower dielectric layer and the second layer. After etching the underlayer, such as a via, it remains When the intermediate etch field is provided with the intermediate etch barrier layer, the connection area will usually be increased.

Page 529, page 529091 5. The overall k value of the description of the invention (5) < generates double gold, for example, when a pattern is required to generate a step line layer, some extra steps may be shown in double gold. The related field is shown in the top view. Align the trench (and conductive material filling (62). Figure 15 (6 8) of the mass layer (64) does not align the part of the trench pattern of the second electrical upper layer. This is in addition to an intermediate etch barrier. The number of process steps that must be used for a damascene structure will be increased. The intermediate etch barrier layer deposition step and the intermediate etch barrier layer. As is common in the existing manufacturing technology, there are multiple repeats in different connection layers. These additional steps. This increases the manufacturing cost and reduces the output rate. It is a possibility that the trench and via connection structure is not aligned when the mosaic technology forms the connection structure. As shown in Figure 15 The via hole (70) formed in the lower dielectric layer has no subsequent conductive line (60). Therefore, only a part of the through-hole (70) is used to form the medium trench of the conductive plug structure. The dielectric layer is advanced because the filling should be performed. In this case, the conductive material is narrower than expected. The resistance value of (6 2) is due to the current need for a two-layer metal damascene with a quality layer without seriously damaging the side-to-side etching stop pattern. The etching should be performed in (66). The through-holes are not time-consuming, and the shape will not cause RC to provide through-holes that can be formed in the connection structure on the first layer (65 simultaneous trenches, so the guidance formed in the trenches is desirable). The method and risk of increasing the value of the via layer is shown in Fig. 1). The anisotropy of the medium shape and the via hole only open the positive plug of the channel (in the case of adding 0, the configuration is used, while reducing the pattern of the first dielectric. During the etching process, it will be based on the bottom of the target through-hole. After 6 2), a lower k-value dielectric will be added than the original conductive plug.

Η

92022.ptd Page 11 529091 V. Description of the Invention (6) Dielectric layer and dielectric. There is also a need to provide a full width through hole. [Disclosure of the present invention] The implementation method of the present invention satisfies the above step: the first dielectric material is deposited on the conductive layer. The material is an organic dielectric, and the first dielectric layer is interposed between the medium layers in the trench. The example of the through hole provides the requirement that the conductive plug mentioned directly below the conductive line formed by the intermediate etching barrier layer has a complete target width, and is filled in the dielectric layer and refilled. In the entire example of the filled structure extending along the first extension, the dielectric material along the second second groove is electrically narrowed to the body width, and the first material is the first dielectric groove to energize the dielectric. Via, dielectric layer structure. The second aspect is to diffuse these and other barrier layers in a dielectric to form the first dielectric material. The first formation trench is etched to deposit organic electricity on the trench extending layer, and the first dielectric layer ensures that the conductive hole formed and the first layer are inorganic and the second layer is etched vertically along the trench. The width of the trench via material is a dielectric material. The hole is engraved with a wide plug in the layer. Slot length second dielectric medium dielectric on the through hole above the electromechanical groove. The dielectric layer is the first material layer in the material layer. The method includes the diffusion wall layer. The dielectric layer vias are then formed on the material. At the same time, Yu Zhiguo, the direction of at least part of the trench. In the length of the dielectric, the material of the present invention's structure includes the following steps of sinking the first dielectric so as to pass through the first electrical trench so as to re-engage in the two dielectrics and thus form two directions. The micro-fine junction is another implementation of the second through-trench through-hole with the width of the upper conductive line.

92022.ptd Page 12 529091 V. Description of the invention (7) In addition, because the second dielectric material is deposited in the via hole 'after the first formation of the via hole', the second etching of the via hole passes through Newly deposited electrical and qualitative materials. The advantage of this method is that the photoresist removal process loss and the amount of organic dielectric material in the first dielectric layer are reduced. The method of the present invention can use a low-k organic dielectric material in the first dielectric layer, and can use a low-k inorganic dielectric material in the second dielectric layer. In the photoresist removal process, the low-k value organic dielectric material is lower than the low-k value of two = electricity; 贝 shell is less vulnerable to damage. Therefore, because of the value of the inorganic dielectric material in the upper dielectric layer, in the two-way method of forming a connection, only a low-k value inorganic dielectric material is subjected to a photoresist that may cause damage. System, integrity and through-holes in the first dielectric layer "); add two electric = layer one value of Λ electromechanical dielectric material and the * electromechanical dielectric material is refilled with 'electricity: ^ :: 甬 with low k value It is advantageous to have through-holes in the two-layer metal inserts forming the connection. The photoresist, which is damaging during the low-gap method at the through hole, is removed during the removal process. This method has the effect of reducing the damage of the Hi dielectric inorganic material #, forming through holes and conductive plugs. ° Where the integrity and when the first dielectric layer is shaped, such as organic and inorganic materials, two different types of low-k materials such as dielectric layers and Z materials can be etched. Intermediate etching is not needed = another dielectric will be etched Floor. This layer is under the lower dielectric layer to resist 2 layers. In some embodiments, the diffusion barrier is formed by a covering material 92022.ptd Page 13 529091 Five 'invention description layer, so the pattern is better when the barrier layer is in accordance with the present method, and the conductive layer is The dielectric material has a long-etched conductive dielectric medium that extends the second dielectric groove and the energized dielectric medium. The dielectric material has two holes extending in the width of the front medium. (8) can be more in this way, can be found in. The next step is to form a layer. The in the 苐, and the length. Dielectric material. In order to substantially etch the plane formed in the medium, the via hole is filled with the electricity in the electric medium, and another precise method is required to generate a photoresist on the lower dielectric layer under the lower dielectric type. The layered dielectric layer does not use a patterned etched layer formed in the dielectric layer of the bulk-barrier layer dielectric layer described in the example which can be formed by other methods than the formed dielectric layer. The material of the series of large through-hole dielectric materials that are perpendicular to each other provides a shape requirement; and the first dielectric in the texture layer, the second moment, the two electricity, the second straight through-hole shaping, and the material. The material is exemplified by the direction of the second dielectric layer trench of the connected dielectric dielectric. The width of the trench is in the trench. It is inorganic organic electricity that provides a line structure. This method forms a channel with a width extending channel on the layer of the expanded dielectric dielectric layer and the dielectric layer in the layer is approximately the same as that of the line in other dielectric dielectric materials. Containing: The wiring junction includes the following bulkhead barrier layer material is a through hole, the dielectric material in the trench and the re-ditch in the plane, and along the length. The degree is smaller than that of the material in the embodiment directly below the line, and the line structure forms an organic trench on the step of conducting the first layer: the inorganic via material is filled in the direction of the first dielectric via. The full trench is located at the width of the first trench, and the first, second, and through holes, and then the first and second electrical channels also satisfy the upper diffusion.

92022.ptd Page 14 529091 V. Description of the invention (9) A barrier layer; and a first dielectric layer containing an organic dielectric material on the diffusion barrier layer. The patterned trenches extend along a first direction in the first dielectric layer. The second dielectric layer on the first dielectric layer contains an inorganic dielectric material, and some of the inorganic dielectric material is in the first dielectric layer in the patterned groove. A conductive plug is provided in a through hole formed in the patterned groove of the first dielectric layer. A conductive line is formed in the second dielectric layer, and the conductive line extends along a second direction perpendicular to the first direction. The conductive lines and the conductive plugs have approximately the same width. Almost the entire width of the conductive plug is directly below the conductive line. In other embodiments, the first dielectric layer includes an inorganic dielectric material, and the second dielectric layer includes an organic dielectric material. If you refer to the following detailed description of the present invention and the accompanying drawings, it will be easier to understand the features, aspects, and advantages of the present invention and other features described above. [Mode for Carrying Out the Invention] The present invention solves a problem associated with a dielectric layer of an auto-aligned two-lane metal damascene configuration using a low-k dielectric material for a metal wiring region of a semiconductor wafer. More specifically, the present invention reduces the overall dielectric constant value of the thin film and prevents extensive damage to the lower dielectric layer of the dual-channel metal damascene configuration, and at the same time ensures that the conductive plugs in the dual-channel metal damascene configuration are below the conductive lines The full width formed. This is achieved in part by providing a low-k organic dielectric layer as the bottom dielectric layer in a dual metal damascene configuration. Forming a trench via in the first dielectric layer

92022.ptd Page 15 529091 V. Description of the Invention (ίο) and the trench via extends vertically to the trench to be formed in the second dielectric layer. The length of the trench via is shorter than the width of the trench. After the trench via is formed and the photoresist layer used to generate the trench via is removed, the trench via is refilled with the inorganic dielectric material used to form the second dielectric layer. When the second dielectric layer is etched to form a circuit or other fine structure in the second dielectric layer, the filled trench via is etched again to reopen the via immediately below the trench. The trench via thus guarantees that the via formed at the end has a full width directly below the trench. In addition, after the trench through-holes are refilled, a photoresist removal removal process is not performed on the inorganic dielectric material. Since two kinds of low-k dielectric materials with different sensitivities are used in the lower W dielectric layer and the upper dielectric layer, there is no need to provide an etching stop layer between the dielectric layers. This method reduces the overall k value of the connection structure, reduces the process steps, and reduces the manufacturing cost. In other embodiments, the first dielectric layer is a low-k inorganic dielectric layer, and the second dielectric layer is a low-k organic dielectric layer. FIG. 1 shows a cross-sectional view of a metal wiring portion of a wafer processed in accordance with an embodiment of the present invention in one stage of a process. At this stage, a conductive layer (20) has been formed, and the conductive layer (20) may be formed such as a metal or other conductive material. In a particularly preferred embodiment, the conductive metal is copper or a steel alloy, because the copper described above is superior to other metals. Such as sinking on top of the conductive layer (20) to form a first etch stop layer (2 2). In some embodiments, Sun α Regal a * ^ ^ ^ a Q / τ is made of sulfide silicon to form the first etch blocking layer (22). Other materials such as silicon oxynitride or silicon nitride can also be used

529091 5. The invention description (η) is used in the first remaining barrier layer (22). The main purpose of the first etched and barrier layer is to protect the upper dielectric layer during etching (20). The first etch stop layer (22) is also used as a diffusion barrier layer. Another purpose of the first remaining resist layer (22) is to be used as an Anti-ReHective Coating (Arc) for improving the formation of through holes in the first dielectric layer. Silicon carbide, which is an example of the material of the etch resist layer, has excellent ARC characteristics, and thus Tian is particularly suitable for the first etch barrier layer (2 2). As shown in Figure 2, a first dielectric layer (24) is then formed on the first etch stop layer (2 2). In the first embodiment of the present invention, the material forming the first dielectric layer (24) is an organic dielectric material. In a particularly preferred embodiment, the organic dielectric material is a low-k organic dielectric material. Available from many different materials including SILK, phentermine, Nautilus (all made by Dow), polyfluorotetraethylene glycol (made by DuPont), FLARE (made by Allied Chemical), etc. The low-k organic dielectric material is selected. For example, it is assumed that the first dielectric layer (2 4) is formed to a thickness between about 1,000 angstroms and about 8,000 angstroms. Fig. 3 is a cross-sectional view of a metal connecting portion shown in Fig. 2 after a photoresist layer (28) is disposed on the first dielectric layer (24) and a pattern is generated on the photoresist layer (28). The pattern created in the photoresist layer (28) defines a fine structure such as a trench via, and the trench via is finally etched to the first dielectric layer (24). When the diffusion barrier layer contains ARC used to form the first etch barrier layer (22), the photoresist layer (28) is improved.

92022.ptd Page 17 529091 V. Description of the invention (12) Resolution of fine structure. Unlike conventional vias, the length of the trench vias of the present invention is greater than the width of the trenches to be formed in the second dielectric layer. To ensure that the trench will extend through the entire width of the trench, the length of the trench via in some embodiments of the present invention is equal to the width of the trench plus twice the misalignment tolerance. For example, if the misalignment tolerance is 8 nm, a perfectly aligned trench via will extend 8 nm at each end of the trench, but the other end of the trench via will coincide with the other end of the trench . This ensures that the vias formed will extend to the full width of the trench. As shown in FIG. 13, the trench through hole will be perpendicular to the trench to be formed. Because each trench via may extend the maximum tolerance on one end of the trench, the trench lines should be isolated with more than twice the maximum tolerance to allow the two largest misaligned vias connected to adjacent lines. The holes do not touch each other. FIG. 4 is a cross-sectional view of the portion shown in FIG. 3 after the first dielectric layer (2 4) is etched to form a trench via (50) according to an embodiment of the present invention. The etchant should be selective so that the material on the first dielectric layer (2 4) is etched away, but the etching is blocked by the first etch blocking layer (22). The etchant chemical used to etch the organic dielectric material in the first dielectric layer (24) may be, for example, nitrogen / hydrogen, or oxygen / nitrogen / argon. After the via holes shown in FIG. 3 are etched, at least some of the photoresist layer (28) shown in FIG. 4 remain on the first dielectric layer (2 4). However, in some embodiments of the present invention, the through-hole and the photoresist layer (2 8) are etched simultaneously. Therefore, when the through-hole is etched, all the photoresist layer (28) is removed. In these embodiments, the first

Η

92022.ptd Page 18 529091 V. Description of the invention (13) The structure shown in Figure 4 and the next structure after Figure 3 is the structure shown in Figure 5. Fig. 5 is a cross-sectional view of the portion shown in Fig. 4 after the photoresist layer (28) is removed and a second dielectric layer (30) is formed on the first dielectric layer (24). The dielectric material in the second dielectric layer (30) also fills the trench vias (50) previously opened in the first dielectric layer (24) as shown in FIG. Therefore, the following effect is achieved: the previously opened trench via (50) may be damaged due to the removal of the photoresist layer (28), but the trench via is now refilled with a non-destructive dielectric material (50). The photoresist removal process performed in Figure 5 may damage the upper surface of the first dielectric layer (24), but the low-k organic dielectric material is less sensitive to the process than the low-k inorganic dielectric material. In some embodiments of the present invention, a cap layer is formed on the first dielectric layer (24) before the pattern of the vias is created and the vias are etched, so that such damage can be largely avoided. Exemplary materials include silicon oxide or silicon nitride, but other materials may be used. The cover layer can be left in place, or the cover layer can be removed. These drawings do not show the formation and removal of the cap layer. In these embodiments, the second dielectric layer (30) is formed once the cap layer is removed. In the first embodiment of the present invention, the dielectric material in the second dielectric layer (30) and the first dielectric layer The dielectric materials in the trench vias (50) now refilled in (24) are all inorganic dielectric materials. In some preferred embodiments of the invention, the inorganic dielectric material is a low-k dielectric material. An example of a non-electromechanical dielectric material is silicon dioxide

92022.ptd Page 19 529091 V. Description of the invention (14), etc. Low-k inorganic silsesquioxane (MSQ), hydrosilsesquioxane (HSQ), and fluorinated dagger f 埝 OS silicate (FTEOS). The use of low-k dielectric Hexahedron in the upper trench layer: In improving the working speed of the circuit, the line-to-line voltage 优点 = advantage is even more critical than the drop in capacitance in the via layer. In order to provide an inorganic material in the lower dielectric layer, and when another dielectric drawer = medium to a machine material, it can make the dielectric f layers have a good, = provided when the etching method described below When refilling the via: J optional. Selective y is used to precisely etch the refilled vias because the first dielectric material is etched and not etched until Monday. It will only etch. The dielectric material fills the through hole with the same material as that used for the upper second dielectric layer. When we understand that the use of phase materials in the refilled vias in the second dielectric layer (30) :; the newly filled dielectric layer (24) can ensure the use of a single-㈣ 剂 来 # 刻Ditch = quality material groove through hole (50). Update-filled In some embodiments, a planarization process is not required. In the embodiment, the second dielectric layer (/, 3 = planarization only is performed by a CMP process, for example. In any embodiment, a hard mask is deposited on the second layer (30) as shown in FIG. 6). Layer (32). The hard masking layer (32) may include an oxide such as silicon or nitride, and is used to selectively protect the second dielectric layer (30) during the i-etching step. Wait for money j = shown in Figure 7, and then deposit a photoresist layer on the hard masking layer (32) and create a pattern on the photoresist layer (34). Photoresist layer (34

529091 5. The pattern in the description of the invention (15)) contains a fine structure to be etched into the second dielectric layer (30). The hard masking layer (32) and the second dielectric layer (30) are etched to produce a desired fine structure such as a trench opening (see FIG. 8). The etching continues through the portion of the refilled trench via (50) directly below the trench formed in the second dielectric layer (30). The etch is blocked by the first etch stop layer (22). As shown more clearly in FIG. 8, only a part of the trench via (50) is etched in this step, and the rest of the trench via (50) is not directly under the trench. Part) still contains the second dielectric material. Because the material surrounding the refilled via is an organic dielectric material and the ¥ via is refilled with an inorganic dielectric material, in the selective etching process, in addition to reopening the via, and This first dielectric layer is not etched. In the preferred embodiment of the present invention, multiple etching steps are used to produce the structure shown in FIG. These steps include: etching the hard masking layer (32), and then simultaneously etching the second dielectric layer (30) and the trench vias (50) refilled in the first dielectric layer (24). A suitable etchant chemical for etching the nitride hard masking layer (3 2) is CHF3 / N2. The etchant chemical used to etch the second dielectric layer (30) and the inorganic dielectric material in the refilled vias may be CHF3 / 02 / Ar, C4F8, CF4, or C2F6. These etchants are only examples, and this is because an appropriate etchant may be used depending on the specific inorganic dielectric material including the second dielectric layer (30). As mentioned earlier, when using two different types of dielectric materials with different etch sensitivity, the vias can be accurately formed from the refilled vias.

92022.ptd Page 21 529091 V. Description of the invention (16) Hole. During the etching of the second dielectric layer and the refilled vias, only the second dielectric material of the first dielectric layer in the refilled vias will be etched. During the reopening of the via, the first dielectric material that was previously filled but now surrounds the refilled via in the first dielectric layer will not be etched. As shown in FIG. 9, the photoresist layer (3 4) can be removed by an etching or oxygen ashing process. Although in the first embodiment, an inorganic dielectric material is used to form the second dielectric layer (30) and the reopened vias (36), the material will only accept a single light that may damage the formed trenches or vias. Resistance removal process. For the structure with vias (36) and trenches, the above process is superior to the inorganic dielectric material in the via layer and / or trench layer. It must accept multiple process steps that may damage the via and accept A single photoresist removal process step that damages the trench. As shown in Figure 10, the first etch stop layer (2 2) is now etched in the re-opened vias (3 6) that currently exist in the first dielectric layer (24). Thus, the etch-blocking material of the conductive material covering the conductive layer (20) is removed. A suitable etchant that removes the remaining impact materials such as broken fossils but does not adversely affect conductive materials such as copper is CHF3 / N2. The etchant chemical prevents the oxidation of copper, removes the sidewall polymer with nitrogen, and etches the dielectric material in the second dielectric layer (30) or the dielectric material in the first dielectric layer (24) without damaging the dielectric material. Silicon carbide. The etching of the first etch stop layer (2 2) leaves a first opening (3 6) such as a through hole, and a second opening (3 8) such as a trench.

92022.ptd Page M 529091 V. Description of the invention (π) Now in the simultaneous deposition step, the through hole (3 6) and the trench are filled with a conductive material (preferably copper in some embodiments of the invention). (3 8). The deposition of a barrier layer commonly used to avoid copper diffusion is not shown in the figure so as not to obscure the present invention, but the barrier layer may be provided. In addition, in some embodiments of the invention, it is not necessary that the barrier layer of some low-k dielectric materials form a spontaneous barrier that resists copper diffusion. After performing chemical mechanical planarization (CMP), a two-channel metal damascene structure as shown in FIG. 11 is formed, in which a via (or bolt) (40) electrically connects a lower conductive layer (20) to a trench ( 38). In a second embodiment of the present invention, the first dielectric layer includes an inorganic dielectric jp dielectric material, and the second dielectric layer includes an organic dielectric material. Specific etchants suitable for these materials have been described previously. As for the removal of the photoresist layer (3 4) (FIG. 9), please note that, in this second embodiment, an organic dielectric material is used to form the second dielectric layer (30) and the reopened via ( 3 6), so the trenches and vias (3 6) formed in the organic dielectric material are more resistant to the photoresist removal process than those formed with the inorganic dielectric material, and therefore are less likely to be damaged in the photoresist removal process. Since the previously formed trench vias are filled during the deposition of the second dielectric layer, vias that are less likely to be damaged by processes such as photoresist removal can be formed. This method enhances the integrity of the microstructure formed in the lower dielectric layer, such as a via layer, and enables the use of low-k inorganic dielectric materials in one of the two-layer metal damascene configurations. Due to the use of trench vias, it is ensured that the resulting vias will extend completely below the trench. While the invention has been shown and described in detail, it will be apparent that

92022.ptd Page 23 529091

92022.ptd Page 24 529091 Brief description of the drawings [Simplified description of the drawings] FIG. 1 is a metal connection of a semiconductor wafer after a first etch stop layer is deposited on a lower conductive connection layer according to an embodiment of the present invention Sectional cross section. Fig. 2 is a cross-sectional view of a metal wiring portion shown in Fig. 1 after a first dielectric layer is formed on a first etch stop layer according to an embodiment of the present invention. FIG. 3 is a cross-section of the portion shown in FIG. 2 after the photoresist layer on the first dielectric layer is deposited and patterned to define a microstructure to be etched into the first dielectric layer according to an embodiment of the present invention. Sectional view. FIG. 4 is a cross-sectional view of the portion shown in FIG. 3 after the first dielectric layer is etched to form a trench via according to an embodiment of the present invention. FIG. 5 is the part shown in FIG. 4 after the photoresist layer on the first dielectric layer is removed, a second dielectric layer is formed on the first dielectric layer, and the through hole in the first dielectric layer is filled. Cross-section view. FIG. 6 is a cross-sectional view of the portion shown in FIG. 5 after a hard masking layer is deposited on the second dielectric layer according to an embodiment of the present invention. FIG. 7 is a portion shown in FIG. 6 after the photoresist layer on the second dielectric layer is deposited and patterned to define a first fine structure to be etched into the second dielectric layer according to an embodiment of the present invention. Cross-section view. FIG. 8 is a pattern in a photoresist layer according to an embodiment of the present invention.

92022.ptd Page 25 529091 The diagram is simply illustrated and etched through the hard mask layer and the second dielectric layer to create a first microstructure in the second dielectric layer and etched through the refilled trench via to A cross-sectional view of the portion shown in FIG. 7 after the vias are defined in the first dielectric layer. FIG. 9 is a cross-sectional view of the portion shown in FIG. 8 after the photoresist layer is removed according to an embodiment of the present invention. FIG. 10 is a cross-sectional view of the portion shown in FIG. 9 after the first etch stop layer is etched according to an embodiment of the present invention. FIG. 11 is a cross-sectional view taken along line I-I shown in FIG. 13 after the first and second microstructures are filled with a conductive material according to an embodiment of the present invention. Sectional view. Fig. 12 shows the part shown in Fig. 10 after the first and second microstructures are filled with a conductive material according to the embodiment of the present invention. The part is taken along line 1-II shown in Fig. 13 Cross-section view. Fig. 13 is a plan view of a part of a wiring arrangement having a trench via according to an embodiment of the present invention. Figure 14 is a cross-sectional view of a connection structure formed according to the prior art. Fig. 15 is a plan view showing the connection structure shown in Fig. 14 according to the prior art. ⑯ [Explanation of component symbols] 20 Conductive layer 22 Barrier / etch stop layer 24 Organic dielectric material (dielectric layer) 2 8, 3 4 Photoresistive layer

92022.ptd Page 26 529091

92022.ptd Page 27

Claims (1)

529091 VI. Scope of patent application 1. A method for forming a connection structure, comprising the following steps: depositing a diffusion barrier layer (2 2) on a conductive layer (2 0); and diffusing the barrier layer (2 2) A first dielectric material (24) is deposited thereon to form a first dielectric layer (24), the first dielectric material (24) is a low-k organic dielectric material (24); the first dielectric layer (24) In order to form a trench via (50) in the first dielectric layer, the trench via (50) extends a trench length in the first direction in the first dielectric layer (24); A second dielectric material (30) is deposited in the trench via (50) and on the first dielectric layer (24) so as to be on the trench via (0) and the first dielectric layer (24). Forming a second dielectric layer (30), the second dielectric material (30) being an inorganic dielectric material (30); and simultaneously etching the trench via (50) and the second dielectric layer (30), thereby forming A microstructure (36, 38) extending in the second dielectric layer (30) along a second direction perpendicular to the first direction And at least a part of the trench via (50) is etched, the width of the microstructure (36, 38) along the second direction is smaller than the length of the trench, and the microstructure (36, 38) The overall width is above the trench via (50). I 2. The method according to item 1 of the scope of patent application, wherein the low-k organic dielectric material is selected from at least one of SILK, benzocyclobutene, Nautilus, FLARE, and Teflon ( twenty four) 92022.ptd Page 28 529091 6. Scope of patent application 3. For the method of item 2 of the patent scope, which is from silicon dioxide, methane silsesquioxane (MS Q), hydrogen silsesquioxane (HSQ) ), And at least one material selected from the group consisting of fluorinated tetraethyl orthosilicate (FTEOS), the inorganic dielectric material (30). 4. The method according to item 3 of the patent application scope, further comprising the following steps: simultaneously depositing a conductive material (40) in the trench via (50) and the microstructure (36, 38). 5. The method according to item 4 of the patent application, wherein the conductive material (40) is copper. 6. A method for forming a connection structure, comprising the following steps: f depositing a diffusion barrier layer (22) on the conductive layer (20); depositing a first dielectric material (2 2) on the diffusion barrier layer (2 2) 24), so as to form a first dielectric layer (24), the first dielectric material (24) is an inorganic dielectric material (24); etching the first dielectric layer (24) so that the first dielectric layer (2 4) A trench via (50) is formed in the trench, and the trench via (50) extends the length of the trench along the first direction within the first dielectric layer (24); in the trench via (50) And depositing a second dielectric material (30) on the first dielectric layer (24), so as to form a second dielectric layer (30) on the trench via (50) and the first dielectric layer (24), The second dielectric material (30) is an organic dielectric material (30); and the trench via (50) and the second dielectric layer are etched simultaneously ( 92022.ptd page 29 529091 VI. Patent application scope 3 0), thus forming a microstructure (36, 38) extending in the second dielectric layer (30) along a second direction perpendicular to the first direction ), And at least a part of the trench via (50) is etched, the width of the microstructure (36, 38) along the second direction is smaller than the length of the trench, and the microstructure (36, 3) 8) The overall width is above the trench via (50). 7. The method according to item 6 of the patent application, wherein the low-k organic dielectric material (30 is selected from at least one of SILK, benzocyclobutene, FLARE, Teflon, and Nautilus) ) ° 8. The method according to item 7 in the scope of patent application, which consists of silicon dioxide, methanesilsesquioxane (MS Q), argon silsesquioxane (HSQ), and tetraethyl orthofluoride. The inorganic dielectric material (24) is selected from at least one material of the acid salt (FTEOS). 9. The method according to item 8 of the patent application, further comprising the following steps: depositing a conductive material (40) in the trench via (50) and the microstructure (36, 38) simultaneously. 10. The method according to item 9 of the scope of patent application, wherein the conductive material (40) is copper. 92022.ptd Page 30