KR20000018996A - Multi-interconnection structure with improved charge of contact via and fabricating method of the same - Google Patents
Multi-interconnection structure with improved charge of contact via and fabricating method of the same Download PDFInfo
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- KR20000018996A KR20000018996A KR1019980036880A KR19980036880A KR20000018996A KR 20000018996 A KR20000018996 A KR 20000018996A KR 1019980036880 A KR1019980036880 A KR 1019980036880A KR 19980036880 A KR19980036880 A KR 19980036880A KR 20000018996 A KR20000018996 A KR 20000018996A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
Description
본 발명은 반도체 집적 회로 공정의 다층 배선 구조 및 그 형성 기술에 관한 것으로, 특히 콘택 비아 내부에 보이드(void)가 없이 평탄화된 메탈 배선 구조 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a multilayer interconnection structure of a semiconductor integrated circuit process and a forming technology thereof, and more particularly, to a planarized metal interconnection structure having no voids inside a contact via and a method of manufacturing the same.
반도체 집적 회로 공정에 있어서, 금속 인터커넥션 층(metal interconnection layer)의 형성 공정은 반도체 기판 위에 형성된 능동 소자 및 수동 소자의 동작을 위하여 매우 중요한 공정 단계이다. 제1도에 도시한대로 금속 인터커넥트 라인은 반도체 기판 상에 형성된 하부의 도전층(conductive layer) 또는 활성 영역에 전기적 접속을 위하여, 층간 절연막에 콘택 비아(contact via)를 형성함으로써 전기적 접속을 완성하게 된다.In semiconductor integrated circuit processes, the process of forming metal interconnection layers is a very important process step for the operation of active and passive devices formed on semiconductor substrates. As shown in FIG. 1, the metal interconnect lines complete electrical connection by forming contact vias in the interlayer insulating film for electrical connection to an underlying conductive layer or active region formed on the semiconductor substrate. .
따라서, 반도체 기판 상에 형성된 소자들이 올바로 동작하기 위해서는 콘택 비아를 도전성 물질로 충분히 충전 매립함으로써 고신뢰성의 인터커넥트 층을 형성할 수 있어야 한다.Thus, in order for devices formed on a semiconductor substrate to function properly, it is necessary to fill the contact vias sufficiently with a conductive material to form a highly reliable interconnect layer.
이와 같은 반도체 집적 회로의 인터커넥트 층을 형성하기 위하여, 반도체 제조 업계에서는 물성적 및 전기적 우수성 때문에 알루미늄(aluminum)을 사용하고 있다. 그러나, 알루미늄은 스퍼터링 공정으로 증착하여 콘택 비아를 매립하려고 하면, 입구부에 증착되는 알루미늄의 그림자 마스크 효과(shadow mask effect)로 콘택 비아를 충분히 충전 매립시키지 못하고 콘택 비아 내부에 보이드(void)를 형성 할 수 있다.In order to form such interconnect layers in semiconductor integrated circuits, aluminum is used in the semiconductor manufacturing industry because of physical and electrical superiority. However, when aluminum is deposited by a sputtering process to fill the contact via, the shadow mask effect of aluminum deposited at the inlet does not sufficiently fill the contact via and forms a void inside the contact via. can do.
그런데, 이러한 문제점은 반도체 기판 상에 형성되는 소자의 최소 선폭 길이(minimum feature size)가 축소하게 됨에 따라 더욱 심각하게 나타나게 된다. 즉, 고집적도의 반도체 공정에서는 콘택 비아의 수평 길이가 수직 깊이에 비하여 상대적으로 작아서, 상기 콘택 비아에 보이드를 형성시키지 않고 알루미늄을 충전 매립시키는 것이 더욱 용이하지 않게 된다.However, this problem becomes more serious as the minimum feature size of the device formed on the semiconductor substrate is reduced. In other words, in a high-density semiconductor process, the horizontal length of the contact via is relatively small compared to the vertical depth, so that it is not easy to fill and fill the aluminum without forming voids in the contact via.
반도체 제조 업계에서는 전술한 콘택 비아의 수평 길이와 수직 깊이의 비를 면비(aspect ratio)라 부르고 있으며, 면비가 큰 콘택 비아에 대하여 양호한 스텝 커버리지(step coverage)를 갖고 전기적 접속 특성이 양호한 인터커넥션 층을 형성하기 위한 기술 개발을 수행하고 있다.In the semiconductor manufacturing industry, the ratio of the horizontal length and the vertical depth of the contact vias described above is called an aspect ratio, and an interconnect layer having good step coverage and good electrical connection properties for a large contact ratio via The development of technology to form a.
콘택 비아를 충전 매립하는 알루미늄 평탄화 공정의 한 예로서, 에이치 오노(H. Ohno) 등은 물리적 증착 방식(physical vapor deposition)으로 알루미늄을 고온 증착한 후, 이어서 고온 처리를 수행하는 알루미늄의 표면 확산(surface diffusion) 원리를 이용한 콘택 비아 충전 기술을 1990년도 VMIC 학회 논문집 제76쪽 내지 제82쪽에서 개시하고 있으며, 알루미늄 증착 온도로서 500∼550℃를 권고하고 있다.As an example of an aluminum planarization process that fills contact vias, H. Ohno et al. Have deposited a high temperature of aluminum by physical vapor deposition, followed by a surface diffusion of aluminum that is subjected to a high temperature treatment. Contact via filling technique using the surface diffusion) principle is disclosed in pages 76 to 82 of the 1990 VMIC Society, and 500 to 550 ° C is recommended as the aluminum deposition temperature.
이러한 알루미늄의 고온 증착 공정 기술은, 고온에서의 알루미늄이 가지는 표면 확산 원리를 이용하여 콘택 비아 내에 증착된 알루미늄의 표면 장력(surface tension)을 최소화하도록 알루미늄이 이동(migration)하게 함으로써 콘택 비아를 충분히 충전(fill)하게 된다. 그러나, 이와 같은 표면 확산을 이용한 알루미늄 평탄화(aluminium planarization) 공정도 콘택 비아의 수평 길이가 좁아지고, 면비가 증가할수록 알루미늄이 플로우(flow)하는 동안 비아의 입구가 막히는 경우가 빈번히 발생하여, 비아 내에 보이드를 형성하면서 충전되지 못하는 문제를 여전히 지니고 있다.This high temperature deposition process of aluminum utilizes the surface diffusion principle of aluminum at high temperatures to sufficiently fill the contact vias by allowing the aluminum to migrate to minimize the surface tension of the aluminum deposited in the contact vias. will fill. However, such an aluminum planarization process using surface diffusion narrows the horizontal length of the contact via, and as the aspect ratio increases, the inlet of the via frequently becomes clogged while aluminum flows. It still has the problem of not charging while forming voids.
따라서, 본 발명의 목적은 반도체 집적 회로의 콘택 비아 성립 공정에 있어서, 콘택 비아 내에 도전 물질의 충전 매립이 용이하게 하기 위한 다층 배선 구조 및 그 제조 방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a multi-layered wiring structure and a method of manufacturing the same for facilitating the filling of conductive material in contact vias in a contact via formation process of a semiconductor integrated circuit.
제1도는 종래 기술에 따른 다층 구조를 나타낸 단면도.1 is a cross-sectional view showing a multilayer structure according to the prior art.
제2도는 본 발명에 따른 다층 배선 구조를 나타낸 단면도.2 is a cross-sectional view showing a multilayer wiring structure according to the present invention.
제3a도 및 3b도는 본 발명의 제1 실시예에 따른 제1 금속층 패턴 프로파일을 나타낸 단면도.3A and 3B are cross-sectional views showing a first metal layer pattern profile according to a first embodiment of the present invention.
제4도는 본 발명의 제2 실시예에 따른 제1 금속층 패턴 프로파일을 나타낸 단면도.4 is a cross-sectional view showing a first metal layer pattern profile according to a second embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
10, 20 : 반도체 기판 상의 구조물10, 20: structure on a semiconductor substrate
14, 24 : 제1 금속층14, 24: first metal layer
16, 26 : 콘택 비아16, 26: Contact Vias
12, 22 : 층간 절연막12, 22: interlayer insulation film
21 : 고밀도 플라즈마 증착 방식의 층간 절연막21: interlayer insulating film of high density plasma deposition
27 : 실리콘 옥시 나이트라이드막(SiON)27 silicon oxynitride film (SiON)
상기 목적을 달성하기 위하여 본 발명은 양측 상단 어깨 부위가 중앙에서 주변 방향으로 경사진 형태를 갖는 반도체 기판 상에 형성된 제1 금속층과; 상기 제1 금속층 상부에 형성된 콘택 비아와; 상기 제1 금속층 및 상기 콘택 비아의 주위에 형성된 층간 절연막과; 상기 콘택 비아에 충전 매립된 제2 금속층으로 구성됨을 특징으로 하는 반도체 집적 회로의 다층 배선 구조 장치를 제공한다.In order to achieve the above object, the present invention includes a first metal layer formed on a semiconductor substrate having a shape in which both upper shoulder portions are inclined from the center to the peripheral direction; A contact via formed on the first metal layer; An interlayer insulating film formed around the first metal layer and the contact via; Provided is a multi-layered wiring structure device of a semiconductor integrated circuit, characterized in that it is composed of a second metal layer filled in the contact via.
이하, 본 발명에 따른 반도체 집적 회로의 다층 배선 구조 장치 및 그 제조 방법의 양호한 실시예를 첨부 도면을 참조하여 상세히 설명한다.DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a multilayer wiring structure device of a semiconductor integrated circuit and a method of manufacturing the same according to the present invention will now be described in detail with reference to the accompanying drawings.
제2도는 본 발명에 따른 반도체 집적 회로의 다층 배선 장치를 나타낸 도면이다. 제2도를 참조하면, 반도체 기판 상에 형성된 구조물(20) 상부에 제1 금속층(24)이 형성되어 있으며, 특히 상기 제1 금속층은 양측 상단 어깨 부위(25)가 중앙에서 주변 방향으로 경사진 형태를 갖고 있다.2 is a diagram showing a multilayer wiring apparatus of a semiconductor integrated circuit according to the present invention. Referring to FIG. 2, the first metal layer 24 is formed on the structure 20 formed on the semiconductor substrate. In particular, the first metal layer has both upper shoulder portions 25 inclined from the center to the peripheral direction. It has a form.
그리고, 상기 제1 금속층(24) 상부에는 층간 절연막(22)을 사이에 두고 층간 전기 접속을 위한 콘택 비아(26)가 형성되어 있으며, 상기 콘택 비아(26)는 제2 금속층(28)으로 충전 매립된다.In addition, a contact via 26 for interlayer electrical connection is formed on the first metal layer 24 with the interlayer insulating layer 22 therebetween, and the contact via 26 is filled with the second metal layer 28. Landfill
제3a도는 본 발명의 제1 실시예에 따른 반도체 집적 회로의 다층 배선 장치를 제조하는 방법을 나타낸 도면이다. 제3도를 참조하면, 반도체 기판 상의 구조물(20) 상부에 제1 금속층(24)을 증착하고, 소정의 금속 패턴에 따라 상기 제1 금속층(24)을 건식 식각하게 된다. 이때에, 상기 제1 금속층(24)을 약간 과도 식각(over etch)함으로써 제3도의 점선 원(25)으로 나타낸 바와 같이 제1 금속층(24)의 양측 상단 어깨 부위가 중앙에서 주변 방향으로 경사지도록 형성할 수 있으며, 본 발명에 따른 바람직한 실시예로서, 상기 제1 금속층(24)의 어깨 경사각은 30 ∼60。로 할 수 있다.3A is a diagram showing a method of manufacturing a multilayer wiring apparatus of a semiconductor integrated circuit according to the first embodiment of the present invention. Referring to FIG. 3, the first metal layer 24 is deposited on the structure 20 on the semiconductor substrate, and the first metal layer 24 is dry-etched according to a predetermined metal pattern. At this time, by slightly overetching the first metal layer 24, the upper shoulder portions on both sides of the first metal layer 24 are inclined from the center to the peripheral direction, as indicated by the dotted circle 25 in FIG. 3. can be formed and, in a preferred embodiment according to the present invention, the shoulder angle of inclination of the first metal layer 24 may be a 30-60.
이어서 3b도를 참조하면, 건식 식각된 제1 금속층(24)과 반도체 기판 상에 노출된 구조물 상부에 층간 절연막(22)을 전면 도포한다. 본 발명에 따른 바람직한 실시예로서, 상기 층간 절연막(22)을 플라즈마 인핸스트 화학 기상 증착(plasma enhanced chemical vapor deposition; PECVD) 방식으로 형성할 수 있다.Subsequently, referring to FIG. 3B, the interlayer insulating layer 22 is entirely coated on the dry-etched first metal layer 24 and the structure exposed on the semiconductor substrate. According to a preferred embodiment of the present invention, the interlayer insulating film 22 may be formed by plasma enhanced chemical vapor deposition (PECVD).
반도체 기판 상의 구조물 상부에 형성된 층간 절연막(22)에 대하여 콘택 비아(26)를 형성하고, 제2 금속층(28)을 충전 매립한다. 이어서, 상기 제2 금속층(28)을 위한 패턴 형성 단계를 거쳐서 상기 패턴에 따라 제2 금속층을 식각한다.A contact via 26 is formed on the interlayer insulating layer 22 formed on the structure on the semiconductor substrate, and the second metal layer 28 is filled in the filling. Subsequently, the second metal layer is etched according to the pattern through a pattern forming step for the second metal layer 28.
제4도는 본 발명의 제2 실시예에 따른 반도체 집적 회로의 다층 배선 장치를 제조하는 방법을 나타낸 도면이다. 제4도를 참조하면, 본 발명의 제1 실시예에 따른 반도체 기판 상의 구조물(20) 상부에 제1 금속층(24)을 증착하는 단계에 부가하여 상기 제1 금속층(24) 상부에 식각 속도가 상대적으로 빠른 박막(27)을 증착하고, 상기 제1 금속층(24)과 상기 박막층(27)의 상부에 제1 금속 마스크 패턴을 형성한다. 본 발명에 따른 바람직한 실시예로서, 상기 제1 금속층 상부에 형성된 박막(27)은 실리콘 옥시 나이트라이드(SiON)를 200∼600Å 정도로 형성할 수 있다.4 is a view showing a method of manufacturing a multilayer wiring apparatus of a semiconductor integrated circuit according to a second embodiment of the present invention. Referring to FIG. 4, in addition to depositing the first metal layer 24 on the structure 20 on the semiconductor substrate according to the first embodiment of the present invention, an etching rate is formed on the first metal layer 24. A relatively fast thin film 27 is deposited, and a first metal mask pattern is formed on the first metal layer 24 and the thin film layer 27. According to a preferred embodiment of the present invention, the thin film 27 formed on the first metal layer may form silicon oxynitride (SiON) in the range of about 200 to about 600 kPa.
이어서, 상기 실리콘 옥시 나이트라이드 박막층(27)과 상기 제1 금속층(24)을 패턴에 따라 건식 식각을 수행한다. 이때에, 상기 실리콘 옥시 나이트라이드 박막층(27)의 건식 식각 속도가 상기 제1 금속층(24)의 식각 속도보다 상대적으로 빠르기 때문에, 식각 공정후의 단면 프로파일은 제4도에 나타낸 바와 같이 제1 금속층(24)의 양측 어깨 상단 부위 상부에 형성된 실리콘 옥시 나이트라이드 박막(27)이 식각되어 제1 금속층(24)을 노출시키고, 상기 제1 금속층(24)의 양측 상단 어깨 부위가 중앙에서 주변 방향으로 경사진 형태를 갖게 된다. 그리고, 콘택 비아 및 제2 금속층 형성 공정은 제1 실시예의 제3b도에 따른 공정과 동일하게 진행된다.Subsequently, dry etching of the silicon oxynitride thin film layer 27 and the first metal layer 24 is performed according to a pattern. At this time, since the dry etching rate of the silicon oxynitride thin film layer 27 is relatively faster than the etching rate of the first metal layer 24, the cross-sectional profile after the etching process is shown in FIG. The silicon oxynitride thin film 27 formed on both upper shoulder upper portions of 24 is etched to expose the first metal layer 24, and the upper shoulder portions on both sides of the first metal layer 24 are tilted from the center to the peripheral direction. It will take the form of a picture. The contact via and the second metal layer forming process are performed in the same manner as the process according to FIG. 3b of the first embodiment.
이상과 같이 본 발명에 따른 반도체 집적 회로의 다층 배선 장치 및 그 제조 방법은 제1 금속층의 상부 어깨 부위를 중앙에서 주변 방향으로 경사지게 함으로써, 후속 알루미늄 평탄화 공정 진행중 표면 확산(surface diffusion)이 일어나는 동안 비아 홀 안으로의 알루미늄의 이동(migration)뿐만 아니라 비아 입구 주변에 형성된 골을 향하여 동시에 이동(migration)하게 하도록 한다.As described above, the multilayer wiring apparatus of the semiconductor integrated circuit and the manufacturing method thereof according to the present invention incline the upper shoulder portion of the first metal layer from the center to the circumferential direction so that the via during the surface diffusion during the subsequent aluminum planarization process occurs. In addition to the migration of aluminum into the hole, it simultaneously migrates towards the valleys formed around the via inlet.
그 결과, 알루미늄 평탄화 공정 진행중 비아의 입구가 막히게 되는 것을 저지할 수 있고, 콘택 비아 내에 보이드 형성을 방지하고 비아 크기와 면비에 따른 충전 매립 능력의 향상을 기대할 수 있다.As a result, it is possible to prevent the inlet of the via from being blocked during the aluminum planarization process, to prevent void formation in the contact via, and to improve the filling filling ability according to the via size and aspect ratio.
Claims (7)
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