KR20000009129A - High screen quality format transferring device and a method thereof - Google Patents

Abstract

PURPOSE: A high screen quality format transferring device is provided to achieve high screen quality display by using control clock having low frequency. CONSTITUTION: The device comprises a clock occurring part(12); an analog/digital transistor(2) which digitalizes the analog screen signal corresponding to the clock timing; an input data control measurement; an input data controlling part(8) which manages the digital image signal as right/left data; a screen quality transferring measurement (4) which transfers the digital image signal into the image signal to have a certain brightness; an output data controlling measurement (10) which manages the right/left data into a single screen data; and a data transmitting part(6) which transmits the image signal to the display device. The data transmitting part(6) uses the low frequency clock in order to display high screen quality.

Description

Apparatus of Format Conversion for High-Resolution and Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-sync digital display device, and more particularly, to a high resolution format conversion device and a method configured to implement a high resolution display using a control clock having a low frequency.

In recent years, with the development of high-performance personal computers (hereinafter, referred to as "PCs") and digital display devices, display devices are becoming larger and higher in resolution. In particular, display devices used for CAD (Computer Aided Design) require ultra-high resolution, and even high-end display devices such as workstations require ultra-high resolution, so UXGA (Ultra-XGA; 1600) is required. There is a demand for a display device having a resolution of 占 1200) or more. In response to these demands, research and development on display devices having a resolution of UXGA or higher is being continued. However, in the display device having the resolution of UXGA, the signal processing frequency is high only by the process of phase division, and thus the implementation thereof is difficult. For example, when a 200 MHz video signal is processed within the H frequency of the horizontal synchronization signal H, sampling of an A / D converter (hereinafter referred to as "A / D converter") ( Sampling period can be lowered by phase division, but the video signal (i.e. red (hereinafter referred to as "R"), green (hereinafter referred to as "G"), blue (hereinafter referred to as "B") ) Must be processed at 200 MHz. However, current technology for processing video signals is difficult to implement a system having a clock of 130MHz or more. In addition, as the processing speed of the image signal increases, the effects of EMI (Electro Magnetic Interference) and noise (Nise) is increased, which has a bad effect on the system has been derived.

Accordingly, an object of the present invention is to provide a high resolution format converting apparatus and a method configured to implement a high resolution display using a control clock having a low frequency.

1 is a block diagram illustrating the basic concept of a high resolution format conversion apparatus according to the present invention;

FIG. 2 is a waveform diagram illustrating waveforms of a horizontal synchronous signal for displaying an entire image in FIG. 1. FIG.

3 is a block diagram schematically showing the configuration of FIG.

4 is a waveform diagram illustrating a clock signal waveform of FIG. 3.

FIG. 5 is a block diagram showing the configuration of FIG. 3 in detail. FIG.

FIG. 6 is a diagram for explaining a data processing form according to a horizontal synchronization signal; FIG.

FIG. 7 is a diagram for explaining a control form in the input data controller of FIG. 5; FIG.

FIG. 8 is a diagram for explaining a control form in the output data processor of FIG. 5; FIG.

<Description of Symbols for Main Parts of Drawings>

2: analog / digital converter 4: resolution converter

6: data transmission unit 8: input data control unit

10: output data controller 12: clock generator

In order to achieve the above object, a high resolution format conversion apparatus according to the present invention includes a clock generator for generating a clock having four phases, and an analog / digital converter for digitizing an analog video signal in response to clock timing having four phases. Input data control means for processing a digital video signal into left and right half data of two phases, resolution converting means for converting left and right half data of two phases into a video signal having a specific resolution, and a left and right half of two phases; Output data control means for processing data into two-phase single-screen data.

In addition, the high resolution format conversion method according to the present invention comprises the steps of dividing the phase of the input video signal into a plurality of steps, the step of screen-dividing the phase-divided video signal into two-phase left and right data, and the screen divided video signal Converting a video signal having a specific resolution, and performing parallel processing of left and right half data of two phases having a specific resolution into single-phase data of two phases.

Other objects and features of the present invention other than the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Referring to Figures 1 to 8 will be described a preferred embodiment of the present invention.

1, a block diagram illustrating a basic concept of a high resolution format conversion apparatus according to the present invention is shown. The high resolution format converter includes an A / D converter 2 for converting an analog video signal having an arbitrary resolution into a digital video signal, a resolution converter 4 for converting a digital video signal into a video signal having a specific resolution; And a data transmitter 6 for transmitting the processed video signal to a display device (not shown). The analog R (or G, B) signal having an arbitrary resolution is digitized by the A / D converter 2, and the digital R (or G, B) signal is converted by the resolution converter 4 to the desired resolution in the display device. The video signal having a is converted. The video signal having the specific resolution is transmitted to the data transmission section 6 by dividing two-phase data (that is, Odd Data and Even Data) into left and right data. The data transmitter 6 processes two-phase data (that is, odd data and even data) as full image data and transmits the data to the display apparatus. Referring to FIG. 2, the entire image data is expanded and processed for the same horizontal synchronization signal based on the horizontal synchronization signal. 2 (a) shows a horizontal synchronization signal of the entire image, and the horizontal synchronization signal of the entire image is shown in FIG. 2 (c) and the horizontal synchronization signal of the left half screen image shown in FIG. It is divided into horizontal synchronization signals of the right half screen image shown and processed in parallel at the same time.

Referring to FIG. 3, a high resolution format converter according to the present invention includes a clock generator 12 for generating a clock having four phases, and an A / D converter 2 for digitizing an analog video signal having an arbitrary resolution. And an input data controller 8 for processing the digital video signal into four-phase left and right half data, a resolution converter 4 for converting the digital video signal into a video signal having a specific resolution, and two-left left and right And an output data control unit 10 for processing the sub data into single-phase data of two phases, and a data transmission unit 6 for transmitting the processed video signal to the display device. 4, the change in the clock frequency in the high resolution format conversion apparatus according to the present invention will be described. When processing a video signal having a pixel clock (e.g., a MHz) that is an original video frequency band, the A / D converter 2 is configured to provide a first clock (e.g., 1/4 of a pixel clock) for sampling the video signal. That is, a / 4 ㎒) is used to digitize the input signal. At this time, the digital video signal has a frequency of a / 4 MHz. The input data control unit 8 includes a second clock (for example, a / 4 MHz) for recording the image information into the input memory, and a third clock (for example, a / for reading the image information of the input memory). 8 MHz) and the fourth clock (eg, a / 4 MHz) for processing the four-phase left and right half data into two-phase left and right half data, and the digital image signal is divided into two phases. The data is processed. The resolution converter 4 converts a digital video signal having an arbitrary resolution into left half data and right half data having a specific resolution by using a fifth clock (for example, a / 4 MHz). At this time, the image frequency (eg, ca MHz) of the left and right half data converted by the resolution converter 4 varies depending on the format. The output data control unit 10 includes a sixth clock (for example, ca MHz) for recording left and right half data into an output memory, and a seventh clock (for example, 2ca for reading image information of the output memory). (MHz) to process the left and right half data of two phases into single-phase data of two phases. The data transmitter 6 transmits the single screen data to the display apparatus using the eighth clock (eg, 2ca MHz). In this case, waveforms of the first to eighth clocks are illustrated in FIG. 4.

5, the operation of the high resolution format conversion apparatus of the present invention will be described. The clock generator 12 generates clocks having four phases corresponding to the first clock (ie, CLKA, CLKB, CLKC, and CLKD). The A / D converter 2 comprises first to fourth A / D converters 2a to 2d for dividing the input analog video signals R, G, and B into four phases and digitizing them. At this time, the pixel data form of the video signal actually input is shown in FIG. The CLKA, CLKB, CLKC, and CLKD clocks are supplied to the first to fourth A / D converters 2a to 2d, respectively, to generate digital image signals a, b, c, and d having different phases. . The input data control section 8 comprises first to eighth input memories 8a to 8h for dividing and processing the digital video signals a, b, c and d into two-phase left and right half data. The digital image signals a, b, c, and d are divided into four phases of data and input to the first to eighth input memories 8a to 8h based on the horizontal synchronization signal. The data control mode in the input memory control unit 8 will be described with reference to FIG. Lxx means left half pixel data, and Rxx means right half pixel data. For example, L23 means the third pixel of the second H line in the left half. The pixel data of the left half four phases (e.g., L11, L12, L13, L14) and the right half four phases (e.g., R11, R12, R13, R14) are shown in FIG. The left and right half data of the four phases is input to the left half data (i, j) of the two phases according to the timing of the fourth clock of FIG. 4 in response to the timing. The right half data (k, l) of two phases is output. At this time, the data writing / reading timings in the first to eighth input memories 8a to 8h are staggered with respect to the H line. That is, if the recording time point is the first H line, reading is done at the second H line. Accordingly, the left half data LO and LE and the right half data RO and RE output from the first to eighth input memories 8a to 8h are output to the resolution converter 4. The resolution output section 4 converts the left and right half data (LO, LE, RO, RE) of two phases input at an arbitrary resolution into left and right half data having a specific resolution, respectively. It consists of converters 4a and 4b. At this time, the CLKA and CLKC clocks are supplied to the first to second resolution converters 4a and 4b so that the left and right half data of the two phases are left half data CLO and CLE and right half data CRO having a specific resolution. , CRE). In addition, the shape of the pixel data processed by the first resolution converter 4a is illustrated in FIG. 6B, and the shape of the pixel data processed by the second resolution converter 4b is illustrated in FIG. 6C. ) Is shown. The output data control unit 10 includes first to fourth output memories 10a to 10d to process two-phase left / right data (CLO, CLE, CRO, CRE) having a specific resolution into two-phase single screen data. It consists of. The two-phase left and right half data CLO, CLE, CRO, and CRE are input by dividing two-phase left half data and two-phase right half data into the first to fourth output memories 10a to 10d. The data control form in the output memory controller 10 will be described with reference to FIG. 8. (A) and (b) of FIG. 8 denote left-half data CLO and CLE of two phases output from the resolution converting unit. FIG. it means. The pixel data of the left half two-phase (eg, CL11, CL12) and the right half two-phase (eg, CR11, CR12) is the first to fourth output memories 10a corresponding to the sixth clock timing of FIG. 4. To 10d), and the left and right half data of the two phases are output as single phase data (e, f) of two phases in accordance with the timing of the seventh clock of FIG. In addition, the data write / read timings in the first to fourth output memories 10a to 10d are staggered with respect to the H line. That is, if the recording time point is the first H line, reading is done at the second H line. Accordingly, the two-phase single screen data OD and ED output from the first to fourth output memories 10a to 10d are output to the data transfer unit 6. In this case, the single screen pixel data type is illustrated in FIG. The data transmitter 6 transmits the single screen data OD and ED to the display apparatus in response to the eighth clock timing of FIG. 4. As a result, the apparatus and method for converting a high resolution format according to the present invention divides a video signal having an arbitrary resolution into phases with a low frequency clock, and divides single-screen data into left and right half data. By processing the left and right half data in parallel, a video signal having a desired resolution is processed. As a result, a high resolution video signal is processed at a low clock to reduce EMI and reduce noise. In addition, the use of a lower clock enables ASIC (Application-Specfic IC).

As described above, the apparatus and method for converting a high resolution format according to the present invention divides a video signal having an arbitrary resolution into a phase with a low frequency clock and divides single screen data into left and right half data. By processing and processing the left and right data in parallel, there is an advantage that can process a high resolution video signal with a clock of a low frequency.

In addition, the high resolution format conversion apparatus and method according to the present invention reduces EMI and noise, and also has an advantage of enabling ASIC (Application-Specfic IC) because it uses a low clock.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A clock generator for generating a clock having four phases, An analog / digital converter for digitizing an analog video signal corresponding to the clock timing having the four phases; Input data control means for processing the digital video signal into two-phase left and right half data; Resolution converting means for converting the left and right half data of the two phases into a video signal having a specific resolution; And output data control means for processing the left and right half data of the two phases into single-phase data of two phases. The method of claim 1, And a data transmission unit for transmitting the single screen data to a display device. The method of claim 1, And a clock having four phases divides a phase of an image signal input to the analog-digital converter into a plurality of phases. The method of claim 1, And dividing the digital video signal into two phases of left and right data by the input data control unit. The method of claim 1, And the left and right half data of the two phases are processed in parallel by the left and right half data of a single screen by the output data control unit. Dividing a phase of an input video signal into a plurality; Splitting the phase-divided video signal into two-phase left and right half data; Converting the screen divided video signal into a video signal having a specific resolution; And parallel-processing two-phase left and right half data having the specific resolution into two-phase single-screen data. The method of claim 6, And the input video signal is divided by a clock having a plurality of phases. The method of claim 6, And the phase-divided video signal is screen-divided into two-phase left and right half data by a horizontal synchronous signal having the same frequency. The method of claim 6, And the left and right half data of the two phases are processed in parallel into left and right half data of a single screen by a horizontal synchronization signal having the same frequency.