JPH02191076A - Picture memory interleave input / output circuit - Google Patents

Abstract

PURPOSE:To make a transfer clock speed higher than a memory read cycle by forming a picture memory with plural blocks, sending the outputs of a parallel / serial and serial / parallel conversion circuits to a computing element and the picture memory, and executing the generation control of read and write signals and a switch signal by a control circuit. CONSTITUTION:A picture memory 5 is composed of plural memory blocks 6 and 7 and the data of a parallel / serial conversion circuit 9 and a serial / parallel conversion circuit 10 are respectively made into output data 27 to the computing element and outputs to picture memory data buses 25 and 26. In a read / write control circuit 4, a read signal 22 and a write signal 23 of the memory 5 and a read / write switch signal 24 are generated. Thus, the transfer clock speed can be made higher than the memory read cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device applied to a vehicle number recognition device of a road toll machine.

[Conventional technology]

In image processing devices that require high-speed vehicle number recognition, etc., a pipeline calculation type image processing device is used within the membrane.

FIG. 3 shows an example of a pipeline calculation type image processing device.

The data input by the camera 12 is transferred to the A/D converter 1
3, it is converted into a digital signal and written into the image memory 5.

The image data written in the image memory 5 is sequentially read out according to instructions from the computer 14, subjected to image processing by the arithmetic unit 15, and then written to the image memory 5 again.

The processed image is converted into an analog video signal by a D/A converter 16 and displayed on a monitor television 17.

FIG. 5 shows an example of an image memory input/output circuit of a pipeline operation type image processing apparatus according to the prior art, and FIG. 6 shows a timing chart of the image memory input/output circuit of FIG. 5.

In FIG. 5, a read address generation circuit 1 generates a read address RA of output data to an arithmetic unit.

RAl, RA2, . . . are generated in synchronization with the clock 18.

The write address generation circuit 2 generates write addresses WA, WA1 . . . WA1 . wA2... is generated in synchronization with the clock 18.

The read/write control circuit 4 receives an image memory read signal 22, a write signal 23, and a read/write switching signal 2.
Generates 4. The read/write switching signal 24 becomes HI in the first half of one clock cycle and LO in the second half, and the image memory 5 performs a write operation in the first half of one clock cycle and a read operation in the second half.

The address selector 3 has a read/write switching signal 24.
When the switch signal is LO, the read address 19 is output to the image memory address bus 21, and when the switching signal is HI, the write address 20 is output to the image memory address bus 21.

The data switching circuit 8 receives a read/write switching signal 24
When is LO, read data RDo, RD, RD2-, etc. on the image memory data bus 29 are output to the data output flip-flop 11.

When the switching signal is HI, input data WDo, WD, WD2, . . . from the arithmetic unit 15 are output to the image memory data bus.

The data output flip-flop 11 synchronizes the data RDo, RD1°RD2, . . . sent from the image memory with the clock 18, and outputs the data to the arithmetic unit.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, only one pixel worth of data is handled in one read and write operation, so two operations, read and write to the image memory, must be performed during one transfer cycle. It won't happen.

Therefore, the transfer lock speed cannot be increased beyond the memory read/write cycle time.

Furthermore, as the number of inputs and outputs to the arithmetic unit increases, the processing speed becomes slower. For example, when outputting two systems of data to a computing unit and receiving two systems of data from the computing unit, two memory read operations and two memory write operations are required during one transfer cycle. .

The present invention aims to provide a device that solves these problems.

[Means to solve the problem]

The image memory interleave input/output circuit according to the present invention includes a read address generation circuit 1 and a write address generation circuit 2.
In an image memory input/output circuit comprising an address selector 3, a read/write control circuit 4, an image memory 5, and a data switching device 8, a parallel/serial conversion circuit 9 and a serial/parallel conversion circuit 10 are provided, and the image memory 5 consists of a plurality of memory blocks, the parallel/serial conversion circuit 9 converts image data input from the plurality of memory blocks into serial data and outputs it to the arithmetic unit, and the serial/parallel conversion circuit 10 converts image data input from the arithmetic unit to serial data. The read/write control circuit 4 generates a read signal, a write signal, and a read/write switching signal for the image memory 5, and converts the image data into parallel data and outputs it to the image memory 5.

[Effect]

The image memory is composed of a plurality of memory blocks, and a plurality of neighboring pixel data are stored in separate memory blocks.

Data is read from multiple memory blocks simultaneously, the read data is converted into serial data by a parallel/serial conversion circuit, and then transferred to the arithmetic unit in order.

The data transferred from the arithmetic unit is converted into parallel data by a serial/parallel converter circuit for multiple pixels, and is written into multiple memory blocks at the same time.

By dividing the image memory into a plurality of blocks and reading and writing a plurality of image data at the same time, the image data transfer lock cycle is increased beyond the memory read/write cycle.

〔Example〕

Examples of the present invention are shown in FIGS. 1 to 4.

FIG. 1 shows an embodiment of an image memory input/output circuit for pipeline operation type image processing according to the present invention, and FIG.
A timing chart of the image memory input/output circuit is shown.

In FIG. 1, the read address generation circuit 1 uses a read address RAo of output data to the arithmetic unit.

RA 112... is generated once every two clocks.

The write address generation circuit 2 generates write addresses WAo, WA, of input data from the arithmetic unit.

WA2... is generated once every two clocks.

The read/write control circuit 4 generates a read signal 22, a write signal 23, and a read/write switching signal 24 for the image memory 5. The read/write switching signal 24 is
This is a repeating signal that is LO during one clock cycle and HI during the next clock cycle.

In address selector 3, read/write switching signal 24
When the switch signal 24 is LO, the read address 19 is output to the image memory address bus 21, and when the switching signal 24 is Hl, the write address 20 is output to the image memory address bus 21.

The image memory 5 consists of two blocks, a block 6 and a block 7, and the block 6 connects the image memory bus 25 to
Block 7 has an image memory data bus 26. Block 6 handles even-numbered transfer data RDo, RD2-... and WDo, WD2-.... Block 7 is odd-numbered transfer data RD1. RD3... and WDl, WD
3... The data switching circuit 8 handles the read/write switching signal 2.
4 is LO, read data RDo, RD21RD4, . . . on the image memory data bus 25 and read data RD, RD3, . RD5
... is output to the parallel/serial conversion circuit 9. Further, when the read/write switching signal 24 is HI, data WD1. W.D.
3°WD,...and WDl, WD3. WD5... is output to the image memory data bus 2526.

The parallel/serial conversion circuit 9 converts a set of data (RD o +RD, ), (R
D2. RD3), (RD4°RD5), etc. are converted into serial data and sequentially output to the arithmetic unit.

The serial/parallel conversion circuit 10 receives serial data WDo, WD, sent from the arithmetic unit.

WD2-... are put together two by two (WDo, WD1
).

(WD2.WD3), (WD4.WD5)... Output to image memory data bus 25.26.

In the circuit of the present invention, when image data is transferred from the image memory to the arithmetic unit and from the arithmetic unit to the image memory, as shown in FIG. will be held.

Utilizing this feature, the image memory is configured with multiple memory blocks, multiple image data adjacent to each other are stored in separate memory blocks, and increment processing is performed to read and write multiple data to the image memory at the same time. By this,
Raise the image data transfer lock cycle above the memory read/write cycle.

〔Effect of the invention〕

Since the present invention is configured as described above, it produces the effects described below.

(1) By reading/writing a plurality of pixel data at the same time, it is possible to increase the image data transfer port/tuck cycle beyond the memory read cycle.

(2) Even if the number of inputs and outputs to the arithmetic unit increases, it is possible to avoid dropping the transfer lock by increasing the number of blocks in the image memory.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the circuit of the present invention, Fig. 2 is a diagram showing a timing chart of the embodiment of the circuit of the present invention, Fig. 3 is a configuration diagram of a pipeline arithmetic processing device, and Fig. 4 is an image memory An explanatory diagram of data scanning, FIG. 5 is a diagram showing a conventional circuit, and FIG. 6 is a diagram showing a timing chart of the conventional circuit. DESCRIPTION OF SYMBOLS 1... Read address generation circuit, 2... Write address generation circuit, 3... Address selector, 4... Read/write control circuit, 5... Image memory, 8... Pig switching circuit, 9...Parallel/serial conversion circuit,
10... Serial/parallel conversion circuit.

Claims (1)

[Claims] A read address generation circuit (1), a write address generation circuit (2), an address selector (3), a read/write control device (4), an image memory (5), and a data switching device (
8), the image memory input/output circuit includes a parallel/serial conversion circuit (9) and a serial/parallel conversion circuit (10), the image memory (5) is composed of a plurality of memory blocks, The conversion circuit (9) converts image data input from multiple memory blocks into serial data and outputs it to the arithmetic unit.
The serial/parallel conversion circuit (10) converts image data input from the arithmetic unit into parallel data and outputs it to the image memory (5).
) is an image memory interleave input/output circuit characterized in that it generates a read signal, a write signal, and a read/write switching signal for the image memory (5).