JPS61136169A - High-speed arithmetic unit - Google Patents

Abstract

PURPOSE:To attain a satisfactory high-speed arithmetic speed and also to reduce the circuit scale by performing an intra-array operation with two actions and furthermore securing the common use of an arithmetic part between the 1st and 2nd operations. CONSTITUTION:The external signals are written to a coefficient register 13 via a selector 11 and a line buffer 12. The data on N lines of the buffer 12 are stored all at once to a shift register 15 at every lines. If the 1st action clock is applied under such conditions, the odd column data of 1, 3, 7... at the M column side of the register 15 are given to a product sum part 17 together with the odd column data at the M column side of the register 13 selected by a coefficient selector part 16. These data are calculated by the part 17 and stored temporarily to a storage register 18. Then the 2nd action clock is applied. Thus the even column data of 2, 4, 6... at the M column side of the register 15 are shifted once to the odd column data and then delivered. Then this even column data is applied to the part 17 together with the even column data at the M column side of the register 13 selected by the selector 16 and delivered after an operation and an addition carried out at an addition part 19.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a high-speed arithmetic device used in image processing and the like.

[Technical background of the invention and its drawbacks]

2. Description of the Related Art Conventionally, a high-speed arithmetic device that performs sum-of-products operations within an M x N array at high speed has been used to process image outputs from TV cameras and the like that have been subjected to NΦ transformation.

Conventionally, as shown in FIG. 3, this type of high-speed arithmetic device combines M x N array data and the data of coefficient register 1, which has the same size as this array and each has an operation coefficient, into M x N array data. There is a system in which a multiplier circuit group 2 performs multiplication and N-1 adder circuit groups 3 perform addition to perform a product-sum operation.

This device can perform operations within the array in one operation clock, so high-speed operation can be expected.
On the other hand, since M x N multiplier circuits and N-1 adder circuits are used, the circuit scale becomes extremely large and the cost becomes high.

Therefore, there is a method for greatly reducing the circuit scale, which performs calculations in multiple stages, but this method has a significantly slow calculation speed and cannot be used as a high-speed calculation circuit.

[Purpose of the invention]

The present invention has been made to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a high-speed arithmetic device that can obtain sufficiently high arithmetic speed, reduce the circuit scale, and be inexpensive.

[Summary of the invention]

A high-speed arithmetic device according to the present invention stores data in a readable/writeable line buffer having N lines to which an external signal is applied in a shift register having an M×N storage section for each line, and stores M column data in this shift register. The odd-numbered columns and the even-numbered columns are output separately, so that half of the calculations are performed in the first operation, the remaining half of the calculations are performed in the second operation, and the final calculation result is obtained from these calculation results. I'm straining to get it.

〔Effect of the invention〕

According to this invention, since it is possible to perform an operation within an array in two operations, a sufficiently high operation speed can be obtained.
Since the arithmetic unit can be shared between the first and second calculations, the circuit scale can be greatly reduced and the cost can be made extremely low.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, reference numeral 11 denotes a data selector, and connected to this data selector 11 are a readable and writable line buffer 12 having N lines and a coefficient register 13 having an M.times.N storage section.

Here, the data selector 11 is used by the line buffer 12 to write a signal applied from the outside into the coefficient register 13.

An address controller 14 that controls the data write address is connected to the line buffer 12.

Further, a shift register 15 having an M x N storage section is connected to the line buffer 12I. This shift register 15 stores data for N lives of the line buffer 13 for each line.

A coefficient selector 16 is connected to the coefficient register 13. This selector 16 selects and outputs the odd-numbered columns and the even-numbered columns of the M-column data of the coefficient register 13.

A product-sum unit 17 is connected to the shift register 15 and the coefficient selector 16.

In this product-sum unit 17, at the first operation clock, the odd number columns of the M column data of the shift register 15, that is, 1, 3, 7, are processed.
It outputs the product-sum operation result of the column data of . It is arranged to output the product-sum operation result with the even number column data of the selector 16.

A storage register 18 is connected to the product-sum section 17 . This register 18 stores the first calculation result in the product-sum section 17.

Further, an adder 19 is connected to the product-sum unit 17 and the storage register 18. This adder 19 adds the first calculation result stored in the storage register 18 and the second calculation result from the product-sum unit 17, and outputs the final product-sum calculation result.

Note that the line buffer 12, shift register 15, coefficient register 13 . A more specific connection relationship between the coefficient selector 16 and the product-sum unit F can be shown in FIG.

Next, its operation will be described.

Now, when an external signal is applied to the data selector 11, the selector 11 writes it into the line buffer 12 or the coefficient register 13.

Thereafter, N lines of data in the line buffer 12 are stored line by line in the shift register 15 at once.

If the first operating clock is given in this state,
The odd number column data of 1.3.7-... on the M column side of the shift register 15 and the odd number column data on the M column side of the coefficient register 13 selected by the coefficient selector 1G are given to the product-sum unit 17, It is calculated here. The calculation result in the product-sum unit 17 is temporarily stored in the storage register 18.

Next, when the second operation clock is applied, the even column data of 2, 4, 6, etc. on the M column side of the shift register 15 is shifted to the odd column and then output, and this data and the coefficient selector 161 Trowel Selected Coefficient Register 13
The even column data on the M column side is given to the product-sum unit 17 and calculated. Then, this calculation result and the previous calculation result in the storage register 18 are added together in an adder 19 and outputted as the final product-sum calculation result.

By doing this, it is possible to perform the product-sum calculation within the array with two operation clocks, so that it is possible to obtain a sufficiently high calculation speed, although it is slightly inferior to that described in FIG. 3. In addition, since calculations are performed using the product-sum unit common to both the first and second operation clocks, the circuit scale can be greatly reduced compared to the one shown in Figure 3, making it extremely inexpensive. It is also extremely advantageous for application to devices with limited circuit scale, such as LSIs, which have been attracting attention recently.

Note that the present invention is not limited to the above-mentioned embodiments, and can be implemented with appropriate modifications without changing the gist. It is also possible to construct a register so that the register functions as a shift register. Further, although the coefficient register 13 is used in the above embodiment, the register 13 can be omitted if there is an alternative data source. Further, in the above-described embodiment, an example of a product-sum operation was described, but a circuit ζ in which the coefficient register 13 side has a dictionary function and performs pattern matching with the shift register 15 can also be applied.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram specifically showing the connection relationship of the main parts of the same embodiment, and FIG. 3 is a block diagram showing an example of a conventional high-speed arithmetic device. It is a diagram. 1...Coefficient register 2...Multiplication circuit group 3--
Adder circuit group 11...data selector 12...
Line buffer Engineering 3... Coefficient register 14 - Address controller 15... Shift register 16... Coefficient select...
17--Product-sum section 18...Storage register 1
9...addition section

Claims (2)

[Claims] (1) A line buffer that can be written and read freely and has N lines to which external signals are applied, a shift register that has an M×N storage section that stores the data of this line buffer for each line, and M column data of this shift register. 1. A high-speed arithmetic device comprising means for separately outputting odd-numbered columns and even-numbered columns, performing arithmetic operations on each, and outputting a final arithmetic result from these arithmetic results. (2) The means has a coefficient register having an M×N storage section, and performs an operation between an odd numbered column of M column data of the shift register and an odd numbered column of M column data of the coefficient register. and performs an operation between the even-numbered columns of the M-column data of the shift register and the even-numbered columns of the M-column data of the coefficient register. The high-speed arithmetic device according to item 1.