JP2002374457A - Driver for solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driver for a solid-state image pickup device which suppresses the influence of noise on horizontal transfer pulses and a CCD signal output. SOLUTION: For the horizontal transfer pulses ϕH generated by dividing the frequency of a master clock MCLK by (m), (n) system clocks SCLK1 to SCLKn generated by dividing the frequency of the master clock by (n) ((n) is an even natural number) are outputted delaying the phase by one cycle of the master clock. Consequently, the voltage of the system clock can be varied in the same timing in the cycle of one pixel of the horizontal transfer pulses for all pixels.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for driving a solid-state imaging device such as a CCD.

[0002]

2. Description of the Related Art In recent years, video cameras and digital still cameras using a CCD as a solid-state imaging device have focused on the development of small, lightweight, high-performance, and low-cost cameras, and the simplification of camera systems has been promoted. It is planned.

Hereinafter, the configuration of a general camera system equipped with such a CCD will be described with reference to FIG.

In FIG. 5, reference numeral 50 denotes a solid-state image pickup device represented by a CCD, a two-dimensional photoelectric conversion unit, a vertical transfer unit for reading signal charges from the photoelectric conversion unit and transferring the signal charges in a vertical direction, and a vertical transfer unit. And a horizontal transfer unit for transferring the signal charges sent from the controller to the charge detection unit in the horizontal direction. 51 is an oscillator for outputting a master clock of the camera system, 5
Reference numeral 2 denotes a timing generator (TG) for controlling the driving timing, signal processing pulse, and system clock for the solid-state imaging device, and 53 a vertical driver for level-converting the pulse voltage output from the TG 52 into a driving pulse for the solid-state imaging device. (VDr), 54 is a preprocessing IC for performing interphase double sampling (CDS) and A / D conversion processing, 55
Denotes a digital signal processing device (DSP) for performing pixel interpolation, luminance / color signal processing, and the like, a recording device of a deck unit, and a video output unit.

First, in the TG 52, a horizontal transfer pulse φH generated by dividing the frequency of the master clock MCLK from the oscillator 51 is applied to the horizontal transfer section of the solid-state imaging device 50.

The TG 52 has a V which is a vertical transfer pulse.
After a pulse is output and the level is converted by the VDr 53, it is applied as a vertical transfer pulse φV to the vertical transfer unit of the solid-state imaging device 50, and as a result, a signal output from the solid-state imaging device 50 is obtained. The signal output output from the solid-state imaging device 50 is input to the pre-processing IC 54, and subjected to CDS or A / D conversion processing using the pre-processing IC pulse output from the TG 52. Next, the signal output from the preprocessing IC is DS
Pixel interpolation and luminance / color processing are performed using the signal processing pulse input from the P55 and output from the TG 52, recording is performed on the deck unit, and a video signal is output from the video output unit as necessary. Is output. A reference clock (hereinafter, referred to as a system clock SCLK) of the recording system of the deck unit and the video output unit or other control systems is TG52.
, The master clock MCLK is divided and supplied.

FIG. 6 shows a schematic configuration of a horizontal transfer pulse φH generation unit and a system clock SCLK generation unit in the TG 52 having the above-described camera configuration. 6, reference numeral 60 denotes an input terminal of the master clock MCLK, 61 denotes a frequency dividing circuit that divides the master clock MCLK by m and generates a horizontal transfer pulse φH, 62 denotes an output unit of the frequency dividing circuit 61, and 63 denotes an output unit 62. Output terminal of horizontal transfer pulse φH connected to
Is a frequency dividing circuit for dividing the master clock MCLK by n and generating a system clock SCLK, and 65 is a frequency dividing circuit 64
Is an output terminal of the system clock SCLK connected to the output unit 65. As shown in FIG.
At G52, the master clock MCLK is divided by m and n, respectively, to generate φH and SCLK.
Although φH is generally not two phases but one phase, here, it is simply referred to as φH.

Next, for example, the solid-state imaging device 50 is generally used for digital video camera applications.
The pixel configuration is 60H (H indicates a horizontal scanning direction) × 540 V (V indicates a vertical scanning direction).
An example in which the master clock MCLK is 54 MHz, which is 12 times the recording system clock of the digital video camera, which is 4.5 MHz, and m = 3 and n = 4 will be described as an example. The oscillator 51 has a 54 MHz master clock MC.
LK is output, the master clock MCLK input to the TG 52 is frequency-divided by 3 in the frequency dividing circuit 61, a horizontal transfer pulse φH of 18 MHz is applied to the horizontal transfer section of the solid-state imaging device 50, and Divided to 13.5 MH
The z system clock SCLK is output to the recording system and the video output unit.

FIG. 7 shows φH and S output from TG 52.
4 shows a timing waveform of CLK. φH outputs signal charges for one pixel in the horizontal transfer unit of the solid-state imaging device 50 in one cycle.

The horizontal transfer pulse φH is obtained by dividing the master clock by 3 and the system clock SCLK is obtained by dividing the master clock MCLK by 4. Therefore, the phase relationship between φH and SCLK is determined every 12 periods of MCLK. Will be the same.

With respect to the 12 cycles of MCLK, the number of changes of φH and the rise and fall of SCLK at the time of a logical change including the rise and fall of MCLK with reference to the cycle of φH is as shown in FIG. Pattern A, B,
There are four patterns, C and D.

[0012]

As described above, in the conventional solid-state imaging device driving device, the timing of the voltage change which is the rising and falling timing of the system clock SCLK within the cycle of one pixel of the CCD is determined. Since it differs from pixel to pixel, and since the type of voltage change of the system clock SCLK such as rising or falling also differs from pixel to pixel, it affects φH and CCD signal output, and noise is mixed into the video signal. There's a problem. In the case of the above conventional example, the phase relationship between φH and SCLK becomes the same every 12 cycles of the master clock MCLK, so that a beat of 4.5 MHz is generated.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a driving apparatus for a solid-state image pickup device in which the influence of noise on the horizontal transfer pulse φH and the output of a CCD signal is suppressed. It is in.

[0014]

In order to achieve the above object, a first driving device for a solid-state imaging device according to the present invention is a device for driving a solid-state imaging device with timing pulses generated by a timing generator. Then, the timing generator generates the input first clock (master clock MCL).
K) is divided by m (m is a natural number) to generate a horizontal transfer pulse φH for driving the solid-state imaging device, and the input first clock is divided by n (n is a natural number and an even number). And n clocks (SCLK
1 to SCLKn), a first output terminal for supplying a horizontal transfer pulse φH from the first frequency divider to the outside, and n output units of the second frequency divider. And n second output terminals for supplying one of the n clocks as a system control clock (system clock SCLK1) to the outside, and k (k is ( n-1) -th and (k)
The +1) th clock has a phase difference of one cycle of the first clock.

According to this configuration, the timing of the voltage change of the system clock within one pixel period of the horizontal transfer pulse φH of the solid-state imaging device can be made the same for all the pixels. The influence of noise on the CCD signal output can be suppressed.

In the first driving device, it is preferable that all of the n second output terminals have the same load capacitance.

According to this configuration, not only the timing of the voltage change of the system clock within the period of one pixel of the horizontal transfer pulse φH of the solid-state imaging device but also the current value at the time of the voltage change is the same for all the pixels. Therefore, the influence of noise on the horizontal transfer pulse φH and the CCD signal output can be further suppressed.

In order to achieve the above object, a second driving device for a solid-state imaging device according to the present invention is a device for driving a solid-state imaging device with a timing pulse generated by a timing generation device. , The first entered
A first frequency dividing circuit that divides the clock (master clock MCLK) by m (m is a natural number) to generate a horizontal transfer pulse φH for driving the solid-state imaging device; and converts the input first clock to n (n is a natural number) A) a second frequency divider for dividing the frequency to generate 2n clocks having different phases, a first output terminal for supplying a horizontal transfer pulse φH from the first frequency divider to the outside, and a second frequency divider 2n output terminals respectively connected to 2n output units of the circuit and supplying one of the 2n clocks to the outside as a system control clock (system clock SCLK1), and a second frequency divider The k-th (k is a natural number less than or equal to (2n-1)) and (k + 1) -th clocks output from the circuit are 1/1 of the first clock.
It is characterized by having a phase difference of two cycles.

According to this configuration, the timing of the voltage change of the system clock within the period of one pixel of the horizontal transfer pulse φH of the solid-state imaging device regardless of whether the division ratio n of the second divider circuit is odd or even. Can be made the same for all the pixels, so that the influence of noise on the horizontal transfer pulse φH and the CCD signal output can be suppressed.

In the second driving device, it is preferable that all the load capacitances of the 2n second output terminals be the same.

According to this configuration, not only the timing of the voltage change of the system clock within the period of one pixel of the horizontal transfer pulse φH of the solid-state imaging device but also the current value at the time of the voltage change is the same for all the pixels. Therefore, the influence of noise on the horizontal transfer pulse φH and the CCD signal output can be further suppressed.

In order to achieve the above object, a third driving device for a solid-state image pickup device according to the present invention is a device for driving a solid-state image pickup device with timing pulses generated by a timing generation device. , The first entered
A first frequency dividing circuit that divides the clock (master clock MCLK) by m (m is a natural number) to generate a horizontal transfer pulse φH for driving the solid-state imaging device;
Is a natural number and an even number).
A second frequency divider circuit for generating clocks (SCLK1 to SCLKn), and a first clock and input test signals (TEST1 to TEST (n−
1)), a test circuit block for verifying the operation of the timing generator, a first output terminal for supplying the horizontal transfer pulse φH from the first frequency divider to the outside, and one of the second frequency dividers The output unit is connected to one of the n clocks to control a system control clock (system clock SC).
LK1), a second output terminal to be supplied to the outside, and (n-1) clocks from the second frequency divider circuit in the normal operation mode, and an external test signal in the test mode in the test circuit block. And (n-1) input / output terminals to be supplied to the input / output terminal;
The k-th (k is a natural number less than or equal to (n-1)) and (k + 1) -th clocks output from the second frequency divider have a phase difference of one cycle of the first clock.

According to this configuration, in addition to the advantages of the first driving device, the number of terminals can be reduced because the (n-1) system clock output terminals can be shared with the test terminals not used during mounting. it can.

In the third driving device, it is preferable that the load capacity of the second output terminal and the load capacity of each of the input / output terminals are all the same.

According to this configuration, not only the timing of the voltage change of the system clock within the period of one pixel of the horizontal transfer pulse φH of the solid-state imaging device but also the current value at the time of the voltage change is the same for all the pixels. Therefore, the influence of noise on the horizontal transfer pulse φH and the CCD signal output can be further suppressed.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. The configuration of the camera to which the present invention is applied is the same as that of the conventional example. In the following embodiments, a configuration and a clock generation method of a timing generator TG52, which are characteristic parts of a solid-state imaging device driving device according to the present invention, will be mainly described.

(First Embodiment) First, a driving apparatus for a solid-state imaging device according to a first embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 1 is a block diagram showing an example of the configuration of a timing generator TG52 in a driving device for a solid-state image sensor according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an input terminal of a master clock MCLK, 2 denotes a frequency dividing circuit that divides the master clock MCLK by m and generates a horizontal transfer pulse φH, 3 denotes an output unit of the frequency dividing circuit 2,
Is an output terminal of the horizontal transfer pulse φH connected to the output unit 3, and 5 is the master clock MCLK divided by n (n is a natural number and an even number), and the system clocks SCLK1 and SCL
, SCLKn for generating K2, SCLK3,..., SCLKn, 6 is an output of the frequency divider 5, and 7 is a system clock SCLK1, SCLK2, SCLK connected to the output 6.
3,..., SCLKn output terminals.

The present embodiment is different from the conventional example in that the frequency dividing circuit 5 includes n system clocks SCLK1, SCLK2, SCLK3,.
At the point that the phase difference between the k-th (k is a natural number equal to or less than n−1) -th system clock SCLKk and the (k + 1) -th system clock SCLK (k + 1) has one cycle of the master clock.

As in the conventional example, the master clock MCL
The operation of the present embodiment will be described with an example where K is 54 MHz and m = 3 and n = 4.

The oscillator 51 outputs a 54 MHz master clock MCLK, and the master clock MCLK input to the TG 52 is frequency-divided by 3 in the frequency dividing circuit 2 to obtain 18 MHz.
Hz horizontal transfer pulse φH is applied to the horizontal transfer unit of the solid-state imaging device 50, and the frequency divider 5 divides the master clock MCLK by four, and each phase difference is one cycle of the master clock MCLK. Four 13.5MHz
System clocks SCLK1, SCLK2, SCLK
3. SCLK4 is output, and one of them is used for a recording system and a video output unit.

FIG. 2 shows the horizontal transfer pulse φH output from the TG 52 and the system clocks SCLK1 and SCLK.
2, timing waveforms of SCLK3 and SCLK4 are shown.

As shown in FIG. 2, the system clock SC
LK1 is obtained by dividing the master clock MCLK by four, and the system clock SCLK2 is obtained by dividing the master clock MCLK by four and the system clock SCLK1
Is obtained by delaying the phase by one period of the master clock MCLK. Similarly, the system clock SC
LK3 is obtained by dividing the master clock MCLK by four and delaying the phase of the system clock SCLK2 by one cycle of the master clock MCLK. The system clock SCLK4 divides the master clock MCLK by four. And the system clock SCLK3
Is obtained by delaying the phase by one period of the master clock MCLK.

The horizontal transfer pulse φH outputs signal charges for one pixel in the horizontal transfer section of the solid-state imaging device 50 in one cycle.

The horizontal transfer pulse φH is obtained by dividing the master clock by 3, and the system clocks SCLK1 and SC
Since LK2, SCLK3 and SCLK4 are obtained by dividing the master clock by 4, the horizontal transfer pulse φH and the system clocks SCLK1, SCLK2, SCLK3, SC
LK4 has a phase relationship of 12
It becomes the same every cycle.

With respect to the twelve periods of the master clock MCLK, the horizontal transfer pulse φH at the time of a logical change including the rising and falling of the master clock MCLK and the system clock S with reference to the period of the horizontal transfer pulse φH.
As shown in FIG. 2, the numbers of changes of the rising edges and falling edges of CLK1, SCLK2, SCLK3, and SCLK4 are all the same for each period of the horizontal transfer pulse φH (pattern A).

As described above, according to this embodiment, the horizontal transfer pulse φH obtained by dividing the master clock MCLK by m
In contrast, n system clocks SCLK1 obtained by dividing the master clock MCLK by n (n is a natural number and an even number)
To SCLKn, each phase of which is delayed by one cycle of the master clock MCLK and output.
The timing of the voltage change of the system clock within the period of one pixel of H can be the same for all the pixels. As a result, the horizontal transfer pulse φH and CCD
The effect of noise on the signal output can be suppressed.

Note that n system clocks SCLK1
To SCLKn, the solid-state imaging device is provided by attaching the same load capacitance to the remaining output terminals in accordance with the load capacitance of the output terminal actually used as the system clock. Not only the timing of the voltage change of the system clock within the period of one pixel of the horizontal transfer pulse, but also the current value at the time of the voltage change becomes the same for all the pixels. The influence can be further suppressed.

In the present embodiment, however, the master clock MCLK is divided by n and the system clocks SCLK1 to SCLK1
The frequency dividing ratio n of the frequency dividing circuit 5 for generating CLKn cannot correspond to an odd number.

(Second Embodiment) Next, a second embodiment of the present invention which can cope with an odd division ratio n of the dividing circuit 5 will be described. Note that the configuration of the driving device of the solid-state imaging device according to the present embodiment is the same as that of the first embodiment.

The difference between the present embodiment and the first embodiment is that, when the frequency dividing circuit 5 generates the system clock divided by n, in the first embodiment, k (k is (n-1) The phase difference between the following (natural number) -th and (k + 1) -th system clocks outputs n system clocks corresponding to one cycle of the master clock.
k (k is a natural number less than or equal to (2n-1)) and (k + 1)
The second system clock has a phase difference in that 2n system clocks corresponding to a half cycle of the master clock are output.

Therefore, even when the frequency division ratio n of the system clock is an odd number, the timing of the voltage change of the system clock within one pixel period of the horizontal transfer pulse φH is the same for all the pixels. can do.

As an example, a case where m = 3 and n = 5 will be described with reference to FIG.

FIG. 3 shows a horizontal transfer pulse φH output from TG 52 and system clocks SCLK1 to SCLK1.
The timing waveform of 0 is shown.

As shown in FIG. 3, the system clock SC
LK1 is obtained by dividing the master clock MCLK by 5, the system clock SCLK2 is also divided by 5 from the master clock MCLK, and
LK1 is obtained by being delayed by １ ／ cycle of master clock MCLK. Similarly, the system clock SC
LK3 is also obtained by dividing the master clock MCLK by five and delaying the system clock SCLK2 by a half cycle of the master clock MCLK. The remaining system clocks SCLK4 to SCLK10 are also obtained by delaying by one-half cycle of the master clock. That is, ten system clocks are output from the TG 52.

The horizontal transfer pulse φH outputs signal charges for one pixel in the horizontal transfer section of the solid-state imaging device 50 in one cycle.

The horizontal transfer pulse φH is the master clock M
CLK divided by three, and the system clock SCLK
Since 1 to SCLK10 are obtained by dividing the master clock MCLK by 5, the phase relationship between the horizontal transfer pulse φH and the system clocks SCLK1 to SCLK10 becomes the same every 15 cycles of the master clock MCLK.

With respect to the 15 cycles of the master clock MCLK, the horizontal transfer pulse φH at the time of a logical change including the rising and falling of the master clock MCLK and the system clock S with reference to the cycle of the horizontal transfer pulse φH.
As shown in FIG. 3, the numbers of rising and falling changes of CLK1 to SCLK10 are all the same for each period of the horizontal transfer pulse φH (pattern A).

As described above, according to the present embodiment, the horizontal transfer pulse φH obtained by dividing the master clock MCLK by m is used.
In contrast, 2n system clocks SCLK1 to SCLK1 to SCLK obtained by dividing the master clock MCLK by n (n is a natural number)
CLK2n, each phase is defined as 1 of the master clock MCLK.
Since the output is delayed by a half cycle, the timing of the voltage change of the system clock within the period of one pixel of the horizontal transfer pulse φH can be made the same for all the pixels irrespective of the odd or even number of n. . Thereby, the influence of noise on the horizontal transfer pulse φH and the CCD signal output can be suppressed.

Note that 2n system clocks SCLK
For the first to second output terminals 7 for outputting 1 to SCLK2n, respectively, the same load capacitance is applied to the remaining output terminals in accordance with the load capacitance of the output terminal actually used as the system clock. Not only the timing of the voltage change of the system clock within the period of one pixel of the horizontal transfer pulse of the element but also the current value at the time of the voltage change becomes the same for all the pixels, and the noise to the horizontal transfer pulse φH and the CCD signal output is reduced. Can be further suppressed.

(Third Embodiment) FIG. 4 shows a third embodiment of the present invention.
It is a block diagram showing an example of 1 composition of timing generator TG52 in a drive of a solid-state image sensing device concerning an embodiment. In FIG. 4, 1 is a master clock MCL.
K input terminal, 2 is a frequency dividing circuit for dividing the master clock MCLK by m and generating a horizontal transfer pulse φH, 3 is an output section of the frequency dividing circuit 2, 4 is a horizontal transfer pulse φH connected to the output section 3. Output terminal 5 divides the master clock MCLK by n (n is a natural number and an even number) and outputs the system clock SCLK.
, SCLKn, CLK1, SCLK2, SCLK3,..., SCLKn, 6 is an output of the frequency divider 5, 7 is an output terminal of the system clock SCLK1 connected to one of the outputs 6 of the frequency divider 5 It is.

Reference numeral 8 denotes a bidirectional input / output terminal. The output side is connected to the output section 6 of the frequency divider 5 which is not connected to the output terminal 7 of the system clock SCLK1. 9 is TG
.., TEST (n−) are test circuit blocks for inspection required when the IC 52 is implemented as an IC. The test signals TEST1, TEST2,.
1) is supplied. A control terminal 10 controls switching between the normal operation mode and the test mode.
The bi-directional input / output terminal 8 is controlled by a control signal supplied to the control circuit 2 and outputs a plurality of system clocks SCLK1 to SCLKn generated by the frequency dividing circuit 5 in the normal operation mode. Signals TEST1-TE
ST (n-1) is input and the operation of the TG 52 is verified.

The frequency dividing circuits 3 and 5 of the present embodiment have the first
And the same configuration as the second embodiment, the timing of the voltage change of the system clock within the period of one pixel can be made the same for all the pixels, and the influence of noise on the horizontal transfer pulse φH and the CCD signal output Can be suppressed.

In this embodiment, the number of pins increases because a plurality of system clocks are output. However, by sharing a test input terminal not used in the normal operation mode with the bidirectional input / output terminal 8, the number of pins is increased. Can be suppressed.

The system clock SCLK1 actually used among the n system clocks is output from the output terminal 7, and the first to (n-1) th bidirectional input / output terminals 8
By attaching the same load capacitance to the output terminal 7, not only the timing of the voltage change of the system clock but also the current value at the time of the voltage change within one pixel period of the horizontal transfer pulse of the solid-state imaging device , And the effect of noise on the horizontal transfer pulse φH and the CCD signal output can be further suppressed.

(Other Embodiments) Here, in order to generate a further synchronization signal outside the TG 52, the TG 52 uses, for example, a 27 MHz clock obtained by dividing the 54 MHz master clock MCLK by 2 as a synchronization signal clock. The case of outputting will be described.

In this case, the TG 52 includes an 18-MHz horizontal transfer pulse φH obtained by dividing the 54-MHz master clock by three, and a signal obtained by dividing the 54-MHz master clock by four.
3.5 MHz system clock SCLK1 to SCLK
4 and a 54 MHz master clock MCLK
Two 27 MHz synchronous signal clocks having frequency division and having a phase difference of one cycle of the master clock MCLK are output.

As described above, according to the present embodiment, 54
The master clock MCLK is divided by 4 with respect to the horizontal transfer pulse φH obtained by dividing the master clock MCLK of 3 MHz by 3.
Four divided system clocks SCLK1 to SCLK
4 is output with each phase delayed by one cycle of the master clock MCLK, and two synchronization signal clocks having a phase difference of one cycle of the master clock MCLK obtained by dividing the master clock MCLK by two. Therefore, the timing of the voltage change of the system clock within one pixel period of the horizontal transfer pulse φH can be made the same for all the pixels. Thereby, the influence of noise on the horizontal transfer pulse φH and the CCD signal output can be suppressed.

The four system clocks SCLK1
To SCLK4, the same load capacitance is applied to the remaining three output terminals in accordance with the load capacitance of the output terminal actually used as the system clock. The fifth and sixth output terminals for outputting the synchronization signal clock are provided with the same load capacitance on the other output terminal in accordance with the load capacitance of the output terminal that is actually used as the synchronization signal clock. Not only the timing of the voltage change of the system clock within the cycle of one pixel of the horizontal transfer pulse of the image sensor, but also the current value at the time of the voltage change becomes the same for all pixels, and the horizontal transfer pulse φH and CC
The influence of noise on the D signal output can be further suppressed.

[0060]

As described above, according to the present invention,
The timing of the voltage change of the system clock within the cycle of one pixel can be the same for all pixels, and the influence of noise on the horizontal transfer pulse φH and CCD signal output can be suppressed. It is possible to drastically suppress the deterioration of the video signal due to the interference between a plurality of different pulses.

Thus, conventionally, the CCD drive pulse generator and the system clock generator were generated by separate ICs, and phase control by a PLL or the like was required. It is possible to provide a CCD driving device including a circuit for generating a transfer pulse and an output circuit for a system clock on the same semiconductor substrate without increasing the number of terminals in actual use, and the practical effect is extremely large.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a TG 52 in a driving device of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of a master clock MCLK, a horizontal transfer pulse φH, and system clocks SCLK1 to SCLK4 in FIG. 1;

FIG. 3 is a timing diagram of a master clock MCLK, a horizontal transfer pulse φH, and system clocks SCLK1 to SCLK10 in the second embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration example of a TG 52 in a driving device of a solid-state imaging device according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing one configuration example of a camera system according to a conventional and an embodiment of the present invention.

FIG. 6 shows a TG in a conventional solid-state imaging device driving device.
52 is a block diagram illustrating a configuration example.

7 is a timing chart of a master clock MCLK, a horizontal transfer pulse φH, and a system clock SCLK of FIG. 6;

[Explanation of symbols]

 Reference Signs List 1 master clock input terminal 2 m divider circuit 3 m divider circuit 2 output section 4 horizontal transfer pulse φH output terminal 5 n divider circuit 6 n divider circuit 5 output section 7 system clock output terminal 8 bidirectional Input / output terminals 9 Test circuit block 10 Bidirectional input / output terminal 8 control terminal 50 Solid-state imaging device 51 Oscillator 52 Timing generator TG 53 Vertical driver VDr 54 Preprocessing IC 55 DSP / recording device / video output unit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) // H04N 101: 00 F term (Reference) 4M118 AA05 AB01 BA10 DB09 FA06 5C024 AX01 BX01 CX03 GY01 HX37 JX35

Claims (6)

[Claims] 1. A device for driving a solid-state imaging device with timing pulses generated by a timing generator, wherein the timing generator divides an input first clock by m (m is a natural number),
A first frequency dividing circuit for generating a horizontal transfer pulse for driving the solid-state imaging device; and dividing the input first clock by n (n is a natural number and an even number) to generate n clocks having different phases. A second frequency divider circuit, a first output terminal for supplying the horizontal transfer pulse from the first frequency divider circuit to the outside, and n output units of the second frequency divider circuit,
And n second output terminals for supplying one of the n clocks to the outside as a system control clock, and k (k is equal to or less than (n-1)) output from the second frequency dividing circuit. The solid-state imaging device driving device, wherein the (natural number) -th and (k + 1) -th clocks have a phase difference of one cycle of the first clock. 2. The driving device for a solid-state imaging device according to claim 1, wherein all of the n second output terminals have the same load capacitance. 3. A device for driving a solid-state imaging device with timing pulses generated by a timing generator, wherein the timing generator divides an input first clock by m (m is a natural number),
A first frequency dividing circuit for generating a horizontal transfer pulse for driving the solid-state imaging device; and dividing the input first clock by n (n is a natural number) to generate 2n clocks having different phases. A second frequency divider; a first output terminal for supplying the horizontal transfer pulse from the first frequency divider to the outside; a 2n number of output terminals of the second frequency divider; And 2n second output terminals for supplying one of the clocks as a system control clock to the outside, and k (k is (2n-1)) output from the second frequency divider circuit
The following (natural number) -th and (k + 1) -th clocks have a phase difference of 周期 cycle of the first clock. 4. The driving device for a solid-state imaging device according to claim 3, wherein all of the 2n second output terminals have the same load capacitance. 5. A device for driving a solid-state imaging device with timing pulses generated by a timing generator, wherein the timing generator divides an input first clock by m (m is a natural number),
A first frequency dividing circuit for generating a horizontal transfer pulse for driving the solid-state imaging device; and a second frequency dividing circuit for dividing the first clock by n (n is a natural number and an even number) to generate n clocks having different phases. A divide-by-2 circuit, a test circuit block for receiving the first clock and an input test signal in a test mode and verifying operation of the timing generator, and the horizontal transfer pulse from the first divide circuit And a second output terminal connected to one output unit of the second frequency divider and supplying one of the n clocks to the outside as a system control clock. In the normal operation mode, (n-
1) clocks are output, and in the test mode, (n-1) input / output terminals for supplying the test signal from the outside to the test circuit block, and switching control of signal input / output at the input / output terminals And a control terminal to which a control signal for performing the following is input. The k-th (k is a natural number equal to or less than (n-1))-th and (k + 1) -th clocks output from the second frequency divider circuit are A driving device for a solid-state imaging device, which has a phase difference of one cycle of a clock. 6. The driving device for a solid-state imaging device according to claim 5, wherein the load capacity of the second output terminal and the load capacity of each of the input / output terminals are all the same.