KR20000007551A - Method of filling via contact hole of semiconductor device - Google Patents
Method of filling via contact hole of semiconductor device Download PDFInfo
- Publication number
- KR20000007551A KR20000007551A KR1019980026952A KR19980026952A KR20000007551A KR 20000007551 A KR20000007551 A KR 20000007551A KR 1019980026952 A KR1019980026952 A KR 1019980026952A KR 19980026952 A KR19980026952 A KR 19980026952A KR 20000007551 A KR20000007551 A KR 20000007551A
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- South Korea
- Prior art keywords
- via contact
- contact hole
- semiconductor device
- reflow process
- annealing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 장치의 비아 콘택홀 필링 방법에 관한 것으로서, 보다 상세하게는 어닐링 공정을 수행하여 필 마진을 확보하는 반도체 장치의 비아 콘택홀 필링 방법에 관한 것이다.The present invention relates to a via contact hole filling method of a semiconductor device, and more particularly, to a via contact hole filling method of a semiconductor device to secure a fill margin by performing an annealing process.
통상, 반도체 장치의 제조공정에서는 소자와 소자간을 연결시키거나, 패드(Pad)의 연결 등을 위해서 게이트전극 상부, 소스영역 상부 및 드레인영역 상부 등에 콘택홀(Contact hole)을 형성하고 있다.In the semiconductor device manufacturing process, contact holes are formed in the upper portion of the gate electrode, the upper portion of the source region, and the upper portion of the drain region in order to connect the elements with the elements or to connect the pads.
또한, 최근에 반도체 장치의 고집적화됨에 따라, 반도체 장치의 디자인룰(Design rule)이 점점 작아짐에 따라 콘택홀의 종횡비(Aspect ratio)가 증가하고 있다.In recent years, as the semiconductor device is highly integrated, as the design rule of the semiconductor device decreases, the aspect ratio of the contact hole increases.
상기 콘택홀 사이즈의 감소로 인해 PVD(Physical Vapor Deposition)방식을 이용한 알루미늄(Al)의 필(Fill)은 그 한계에 다다랐다.Due to the reduction in the contact hole size, fill of aluminum (Al) using PVD (Physical Vapor Deposition) has reached its limit.
이를 개선하기 위해 알루미늄 증착 후, 리플로우(Reflow)하는 방법을 택하고 있으나, 이것도 64메가디램(MDRAM) 이후의 차세대 초미세 콘택에서는 메탈(Metal) 콘택뿐만 아니라 비아 콘택에서조차 필링성공 여부를 기대할 수 없는 실정이다.In order to improve this problem, the method of reflowing after aluminum deposition is adopted, but this can be expected to be peeling success not only in metal contact but also via contact in the next-generation ultra-fine contact after 64 megaram (MDRAM). There is no situation.
도1 내지 도3은 종래의 반도체 장치의 비아 콘택홀 필링 방법을 나타낸 공정 단면도들이다.1 to 3 are cross-sectional views illustrating a process of via contact hole filling in a conventional semiconductor device.
종래의 반도체 장치의 비아 콘택홀 필링 방법은, 먼저 도1을 참조하면, 반도체 기판 상에 절연막을 형성한 후, 도2와 같이 비아 콘택홀을 형성한다.In the via contact hole filling method of the conventional semiconductor device, referring to FIG. 1, an insulating film is formed on a semiconductor substrate and a via contact hole is formed as shown in FIG. 2.
도3을 참조하면, 상기 비아 콘택홀 상에 금속막을 증착한 후, 상기 금속막이 형성된 상기 반도체 기판에 리플로우 공정을 수행한다.Referring to FIG. 3, after depositing a metal film on the via contact hole, a reflow process is performed on the semiconductor substrate on which the metal film is formed.
그런데, 상기 비아 콘택홀(24) 하부에 상기 금속막(26)이 다 채워지지 않아, 보이드(18)가 생겨 상기 비아 콘택홀(24) 필 마진을 감소시키는 문제점이 있었다.However, since the metal layer 26 is not completely filled in the lower portion of the via contact hole 24, a void 18 is generated, thereby reducing the fill margin of the via contact hole 24.
본 발명의 목적은, 리플로우 공정 후, 어닐링처리를 함으로써, 알루미늄입자들은 활성화되어 보이드(Void)를 없앨 수 있어 알루미늄 필에 대한 공정상의 마진(Margin)을 확보하는 반도체 장치의 비아 콘택홀 필링 방법을 제공하는 데 있다.An object of the present invention is a method of via contact hole filling in a semiconductor device in which aluminum particles are activated to eliminate voids after the reflow process, thereby securing a process margin for the aluminum fill. To provide.
도1 내지 도3은 종래의 반도체 장치의 비아 콘택홀 필링 방법을 나타낸 공정 단면도들이다.1 to 3 are cross-sectional views illustrating a process of via contact hole filling in a conventional semiconductor device.
도4 내지 도7은 본 발명의 일 실시예에 따른 반도체 장치의 비아 콘택홀 필링 방법을 나타내는 공정 단면도들이다.4 through 7 are cross-sectional views illustrating a method of filling via contact holes in a semiconductor device according to example embodiments.
※ 도면의 주요 부분에 대한 부호의 설명※ Explanation of codes for main parts of drawing
10,20 : 반도체 기판 12,22 : 절연막10,20 semiconductor substrate 12,22 insulating film
14,24 : 비아 콘택홀 16,26 : 금속막14,24: via contact hole 16,26: metal film
18,28 : 보이드(Void)18,28: void
상기 목적을 달성하기 위한 본 발명에 따른 반도체 장치의 비아 콘택홀 필링 방법은, 반도체 기판 상에 형성된 절연막에 비아 콘택홀을 형성하는 단계, 상기 비아 콘택홀에 금속막을 증착하는 단계, 상기 금속막이 형성된 상기 반도체 기판에 리플로우(Reflow) 공정을 수행하는 단계 및 상기 리플로우 공정 후, 어닐링(Annealing) 하는 단계를 포함하여 이루어진다.A via contact hole filling method of a semiconductor device according to the present invention for achieving the above object comprises the steps of: forming a via contact hole in an insulating film formed on a semiconductor substrate, depositing a metal film in the via contact hole, the metal film is formed Performing a reflow process on the semiconductor substrate and annealing after the reflow process.
상기 금속막은 알루미늄막일 수 있다.The metal film may be an aluminum film.
상기 어닐링 온도는 650 내지 670℃인 것을 특징으로 한다.The annealing temperature is characterized in that 650 to 670 ℃.
이하, 본 발명의 구체적인 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도4 내지 도7은 본 발명의 일 실시예에 따른 반도체 장치의 비아 콘택홀 필링 방법을 나타내는 공정 단면도들이다.4 through 7 are cross-sectional views illustrating a method of filling via contact holes in a semiconductor device according to example embodiments.
먼저 도4를 참조하면, 반도체 기판(20) 상에 절연막(22)을 형성한 후, 도5와 같이 비아 콘택홀(24)을 형성한다.Referring first to FIG. 4, after forming the insulating film 22 on the semiconductor substrate 20, the via contact hole 24 is formed as shown in FIG. 5.
도6을 참조하면, 상기 비아 콘택홀(24) 상에 금속막(26)을 형성한 후, 상기 금속막(26)이 형성된 상기 반도체 기판(20)에 리플로우(Reflow) 공정을 수행한다. 상기 금속막(26)은 알루미늄막일 수 있다.Referring to FIG. 6, after the metal layer 26 is formed on the via contact hole 24, a reflow process is performed on the semiconductor substrate 20 on which the metal layer 26 is formed. The metal layer 26 may be an aluminum layer.
도7에 도시된 바와 같이 상기 리플로우 공정후, 어닐링(Annealing) 하여 보이드(28)를 없앤다.As shown in FIG. 7, after the reflow process, annealing is performed to remove the voids 28.
상기 어닐링 온도는 650℃ 내지 670℃ 인 것이며, 바람직하기로는 660℃인 것이다.The annealing temperature is 650 ° C to 670 ° C, preferably 660 ° C.
전술한 바와 같이 리플로우 공정 후, 어닐링 공정을 수행하여 알루미늄입자들이 활성화되어 보이드를 제거할 수 있다.As described above, after the reflow process, the annealing process may be performed to activate the aluminum particles to remove the voids.
따라서, 본 발명에 의하면 리플로우 공정 후, 어닐링처리를 함으로써, 알루미늄입자들이 활성화되어 보이드를 없앨 수 있어 알루미늄 필에 대한 공정상의 마진이 확보되는 효과가 있다.Therefore, according to the present invention, by performing an annealing treatment after the reflow process, the aluminum particles may be activated to eliminate voids, thereby securing a process margin for the aluminum fill.
이상에서 본 발명은 기재된 구체예에 대해서만 상세히 설명되었지만 본 발명의 기술사상 범위 내에서 다양한 변형 및 수정이 가능함은 당업자에게 있어서 명백한 것이며, 이러한 변형 및 수정이 첨부된 특허청구범위에 속함은 당연한 것이다.Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical scope of the present invention, and such modifications and modifications are within the scope of the appended claims.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1998-0026952A KR100505039B1 (en) | 1998-07-04 | 1998-07-04 | Via contact hole filling method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1998-0026952A KR100505039B1 (en) | 1998-07-04 | 1998-07-04 | Via contact hole filling method for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000007551A true KR20000007551A (en) | 2000-02-07 |
| KR100505039B1 KR100505039B1 (en) | 2005-09-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-1998-0026952A KR100505039B1 (en) | 1998-07-04 | 1998-07-04 | Via contact hole filling method for semiconductor device |
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| KR (1) | KR100505039B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100431105B1 (en) * | 2002-07-15 | 2004-05-12 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03139829A (en) * | 1989-10-25 | 1991-06-14 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| KR0170504B1 (en) * | 1995-09-15 | 1999-03-30 | 양승택 | Contact hole burying method |
| KR100217915B1 (en) * | 1996-03-29 | 1999-09-01 | 김영환 | Forming method for contact hole of semiconductor device |
| JPH09306987A (en) * | 1996-05-16 | 1997-11-28 | Ricoh Co Ltd | Manufacture of semiconductor device |
| JP3547027B2 (en) * | 1996-08-30 | 2004-07-28 | 株式会社アルバック | Copper wiring manufacturing method |
-
1998
- 1998-07-04 KR KR10-1998-0026952A patent/KR100505039B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100431105B1 (en) * | 2002-07-15 | 2004-05-12 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
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| Publication number | Publication date |
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| KR100505039B1 (en) | 2005-09-30 |
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