KR100877095B1 - Method of fabricating interconnection in semicondutor device - Google Patents

Method of fabricating interconnection in semicondutor device Download PDF

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KR100877095B1
KR100877095B1 KR1020060137186A KR20060137186A KR100877095B1 KR 100877095 B1 KR100877095 B1 KR 100877095B1 KR 1020060137186 A KR1020060137186 A KR 1020060137186A KR 20060137186 A KR20060137186 A KR 20060137186A KR 100877095 B1 KR100877095 B1 KR 100877095B1
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aluminum
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김현필
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

반도체기판 상에 제1 알루미늄막을 포함하는 하부배선을 형성하고, 하부배선을 절연시키는 금속층간절연막을 형성한 후, 금속층간절연막을 선택적으로 식각하여 제1 알루미늄막을 노출하는 콘택홀을 형성한다. 노출된 제1 알루미늄막에 유발된 표면 산화막을 제거한 후, 표면산화막이 제거된 제1 알루미늄막의 표면을 시드층으로 한 선택적 화학기상증착 방법을 이용하여 상기 금속층간절연막 상에는 제2 알루미늄막의 성장을 배재하고, 상기 제1 알루미늄막 표면 상에는 제2 알루미늄막을 성장시켜 상기 콘택홀 내부에 연결콘택을 형성하는 반도체소자의 연결배선 형성방법을 제시한다. A lower interconnection including a first aluminum layer is formed on the semiconductor substrate, a metal interlayer insulating layer is formed to insulate the lower interconnection, and then the metal interlayer insulating layer is selectively etched to form a contact hole exposing the first aluminum layer. After removing the surface oxide film caused by the exposed first aluminum film, the second aluminum film is grown on the interlayer insulating film by using a selective chemical vapor deposition method using the surface of the first aluminum film from which the surface oxide film is removed as a seed layer. The present invention also provides a method of forming a connection wiring of a semiconductor device in which a second aluminum film is grown on a surface of the first aluminum film to form a connection contact in the contact hole.

금속배선, 금속콘택, 알루미늄, 선택적화학기상증착 Metallization, Metal Contact, Aluminum, Selective Chemical Vapor Deposition

Description

반도체소자의 연결배선 형성방법{Method of fabricating interconnection in semicondutor device}Method of fabricating interconnection in semicondutor device

도 1 내지 도 6은 본 발명에 따른 반도체소자의 연결배선 형성방법을 설명하기 위해 나타내보인 단면도들이다. 1 to 6 are cross-sectional views illustrating a method of forming connection wirings of a semiconductor device according to the present invention.

본 발명은 반도체소자의 제조방법에 관한 것으로, 보다 상세하게는 반도체소자의 연결배선 형성방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming connection wiring of a semiconductor device.

최근 반도체소자의 고집적화 및 고속화됨에 따라, 콘택홀의 선폭이 점점 축소되고, 콘택홀의 길이는 점점 증가하고 있다. 따라서, 콘택홀의 종회비(aspect ratio)가 증가하여 콘택홀 내부에 금속을 불량없이 채우는 기술을 개발하는 노력이 시도되고 있다.In recent years, as the integration and speed of semiconductor devices become higher, the line width of the contact hole is gradually reduced, and the length of the contact hole is gradually increasing. Accordingly, efforts have been made to develop a technique for filling a metal into the contact hole without defect due to an increase in the aspect ratio of the contact hole.

연결 배선 구조는 알루미늄배선들을 텅스텐콘택을 이용하여 연결되게 구성되고 있다. 반도체소자의 선폭이 축소되면서, 텅스텐콘택의 접촉면적이 줄어들고 있어, 콘택 저항이 증가되고 있다. 콘택 저항의 증가에 따라 반도체 소자의 동작 속도가 저하될 수 있다.The connection wiring structure is configured to connect aluminum wirings using tungsten contacts. As the line width of the semiconductor device is reduced, the contact area of the tungsten contact is reduced, and the contact resistance is increased. As the contact resistance increases, an operating speed of the semiconductor device may decrease.

이에 따라, 비저항이 보다 낮은 도전물질로 콘택을 형성하는 시도가 이루어지고 있다. 또한, 콘택홀 크기가 작아짐에 따라, 콘택홀 내부에 채움불량이 유발될 수 있다. 예컨대, 콘택홀의 상부 모서리 부분에서 콘택을 위한 도전층 증착 시, 오버행(overhang)이 발생되거나, 콘택홀 내부가 채워지지 못하는 보이드(void)가 발생될 수 있다. 채움불량이 발생됨에 따라, 콘택 저항이 더욱 증가하거나, 단락이 유발될 수 있어 반도체소자의 신뢰도가 크게 감소 될 수 있다. 따라서, 콘택홀 내부에 도전물질을 채우는 데 있어, 보다 우수한 채움특성을 얻기 위해 다양한 공정 기술을 위한 연구가 요구되고 있다. Accordingly, attempts have been made to form a contact with a conductive material having a lower specific resistance. In addition, as the contact hole size decreases, a filling gap may be caused in the contact hole. For example, when the conductive layer for contact is deposited at the upper edge portion of the contact hole, an overhang may occur or a void in which the inside of the contact hole may not be filled may be generated. As the filling defect occurs, the contact resistance may be further increased, or short circuit may be caused, and thus the reliability of the semiconductor device may be greatly reduced. Therefore, in filling the conductive material inside the contact hole, research for various process technologies is required to obtain better filling characteristics.

본 발명이 이루고자 하는 기술적 과제는 금속배선을 웨팅막으로 이용하고, 선택적 화학기상증착방법을 이용하여 콘택홀을 채워 콘택홀 내부에 보이드를 방지하는 반도체소자의 연결배선 형성방법을 제공하는 데 있다. An object of the present invention is to provide a method for forming a connection wiring of a semiconductor device using a metal wiring as a wetting film and filling the contact holes using a selective chemical vapor deposition method to prevent voids in the contact holes.

상기 기술적 과제를 달성하기 위하여, 본 발명에 따른 연결배선 형성방법은 반도체기판 상에 제1 알루미늄막을 포함하는 하부배선을 형성하는 단계; 상기 하부배선을 절연시키는 금속층간절연막을 형성하는 단계; 상기 금속층간절연막을 선택적으로 식각하여 상기 제1 알루미늄막을 노출하는 콘택홀을 형성하는 단계; 상기 노출된 제1 알루미늄막에 유발된 표면 산화막을 제거하는 단계; 및 상기 표면산화막이 제거된 제1 알루미늄막의 표면을 시드층으로 한 선택적 화학기상증착 방법을 이용하여 상기 금속층간절연막 상에는 제2 알루미늄막의 성장을 배재하고, 상기 제1 알루미늄막 표면 상에는 제2 알루미늄막을 성장시켜 상기 콘택홀 내부에 연결콘택을 형성하는 단계를 포함한다. In order to achieve the above technical problem, the method for forming a connection wiring according to the present invention comprises the steps of forming a lower wiring including a first aluminum film on a semiconductor substrate; Forming a metal interlayer insulating film to insulate the lower wiring; Selectively etching the interlayer dielectric layer to form a contact hole exposing the first aluminum layer; Removing the surface oxide film caused by the exposed first aluminum film; And by using a selective chemical vapor deposition method using the surface of the first aluminum film from which the surface oxide film has been removed as a seed layer, the growth of the second aluminum film is excluded on the interlayer insulating film, and the second aluminum film is formed on the surface of the first aluminum film. And growing a connection contact in the contact hole.

상기 제1 알루미늄막의 상부표면이 노출되게 상기 층간절연막을 선택적으로 식각하는 단계; 및 상기 제1 알루미늄막의 상부표면으로부터 제1 알루미늄막을 더 식각하여 리세스홈을 형성하는 단계를 더 포함할 수 있다. Selectively etching the interlayer insulating film to expose an upper surface of the first aluminum film; And etching the first aluminum film further from the upper surface of the first aluminum film to form a recess groove.

상기 표면 산화막의 제거는 상기 선택적 화학기상 증착의 전 단계로 연속하여 이온화된 아르곤을 이용한 식각공정으로 수행하는 것이 바람직하다.The surface oxide film may be removed by an etching process using argon ionized continuously before the selective chemical vapor deposition.

상기 연결콘택을 형성하는 단계 이후에, 상기 제2 알루미늄막 상에 열처리 공정을 수행하여 상기 제2 알루미늄막을 리플로우 시키는 단계; 및 상기 리플로우된 제2 알루미늄막에 연결되는 상부배선을 상기 금속층간절연막 상에 형성하는 단계를 더 포함할 수 있다.After forming the connection contact, performing a heat treatment process on the second aluminum film to reflow the second aluminum film; And forming an upper wiring connected to the reflowed second aluminum film on the interlayer insulating film.

상기 상부배선은 제3 알루미늄막을 물리기상증착방법을 이용하여 형성하는 것이 바람직하다.The upper wiring is preferably formed by using a physical vapor deposition method of the third aluminum film.

상기 열처리 공정은 상기 상부배선을 증착하는 물리기상증착 장비에서 상기 상부배선을 증착하기 이전에 인 시츄(in-situ)로 수행하는 것이 바람직하다.The heat treatment process is preferably performed in-situ before depositing the upper wiring in the physical vapor deposition equipment for depositing the upper wiring.

상기 하부배선은 제1 알루미늄막 상부에 반사방지막을 더 포함하고, 상기 콘택홀을 형성하는 단계는 상기 금속층간절연막을 선택적으로 식각한 후,상기 반사방지막을 더 식각하여 제1 알루미늄막을 노출시키는 단계를 더 포함할 수 있다.The lower interconnection further includes an anti-reflection film on the first aluminum layer, and the forming of the contact hole may include selectively etching the interlayer dielectric layer, and then etching the anti-reflection layer to expose the first aluminum layer. It may further include.

도 1 내지 도 6은 본 발명에 따른 반도체소자의 연결배선 형성방법을 설명하기 위해 나타내 보인 단면도들이다.1 to 6 are cross-sectional views illustrating a method of forming connection wirings of a semiconductor device according to the present invention.

도 1을 참조하면, 반도체기판(100) 상에 하부배선을 위한 제1 알루미늄막을 형성하고, 제1 알루미늄막 상에 반사방지막(ARC;Anti-Reflection layer Coating)을 형성한다. 하부배선을 형성하기 이전에, 반도체기판 상에 소정의 하부구조 예컨대, 게이트전극, 비트라인 및 캐패시터등이 형성되고, 하부구조들은 층간절연막으로 절연되어 있으며, 층간절연막을 관통하여 하부구조를 전기적으로 연결시키기 위한 연결콘택들이 형성될 수 있다. Referring to FIG. 1, a first aluminum film for lower wiring is formed on the semiconductor substrate 100, and an anti-reflection layer coating (ARC) is formed on the first aluminum film. Prior to forming the lower interconnection, a predetermined substructure, for example, a gate electrode, a bit line, and a capacitor, is formed on the semiconductor substrate, and the substructures are insulated with an interlayer insulating film, and penetrate the interlayer insulating film to electrically connect the substructure. Connection contacts for connecting may be formed.

반사방지막은 예컨대, 티타늄질화막으로 형성될 수 있다. 반사방지막은 노광공정 시, 금속에 의한 노광원의 난반사를 방지하여 제1 알루미늄막을 원하는 선폭으로 패터닝할 수 있다. The antireflection film may be formed of, for example, a titanium nitride film. The anti-reflection film may pattern the first aluminum film to a desired line width by preventing diffuse reflection of the exposure source by the metal during the exposure process.

노광 및 식각공정을 수행하여 반사방지막 패턴(111) 및 제1 알루미늄막 패턴(110)을 형성한다. 제1 알루미늄막 패턴(110)은 반도체기판(100)의 불순물 영역, 게이트전극, 비트라인 및 캐패시터의 상부전극을 전기적으로 연결시키기 위한 배선으로 이용될 수 있다. The anti-reflection film pattern 111 and the first aluminum film pattern 110 are formed by performing an exposure and etching process. The first aluminum film pattern 110 may be used as a wiring for electrically connecting the impurity region of the semiconductor substrate 100, the gate electrode, the bit line, and the upper electrode of the capacitor.

제1 알루미늄막 패턴(110)이 형성된 반도체기판(100) 상에 금속층간절연막(IMD;Inter Metal Dielectrics)(120)을 형성한다. 금속층간절연막(120)은 반도체소자가 고집적화됨에 따라, 서로 다른 특성을 가진 절연물질을 예컨대, 제1 절연막(121), 제2 절연막(123) 및 제3 절연막(125)의 3층 구조로 형성할 수 있다. 이때, 금속층간절연막(120)은 산화막 예컨대, 고밀도플라즈마산화막(High Density Plasma-Oxide), PETEOS(Plasma Enhanced Tetra Ethyl Ortho Silicate), LP(Low Pressure)TEOS, BPSG(Boron Phosphorus Silicate Glass), PSG(Phosphorus Silicate Glass), USG(Un-doped Silicate Glass) 및 FSG(Fluorinated Silicate Glass)을 포함하는 그룹에서 어느 하나 이상을 선택하여 형성될 수 있다. An intermetal dielectric (IMD) 120 is formed on the semiconductor substrate 100 on which the first aluminum film pattern 110 is formed. As the semiconductor interlayer insulating film 120 is highly integrated, an insulating material having different characteristics may be formed in a three-layer structure of, for example, the first insulating film 121, the second insulating film 123, and the third insulating film 125. can do. In this case, the interlayer dielectric 120 may be formed of an oxide film, for example, high density plasma oxide (POSMA), plasma enhanced tetra ethyl ortho silicate (PETOS), low pressure (TEOS), boron phosphorus silicate glass (PSG), or PSG (PSG). It may be formed by selecting any one or more from the group containing Phosphorus Silicate Glass (USG), Un-doped Silicate Glass (USG), and Fluorinated Silicate Glass (FSG).

도 2를 참조하면, 3층 구조의 금속층간절연막(120)을 선택적으로 식각하여 제1 알루미늄막 패턴(110)을 노출시키는 콘택홀(130) 형성한다. 이때, 금속층간절연막(120)을 식각하는 과정에서, 다른 특성을 가진 절연막으로 인해 식각률 차이가 발생될 수 있다. 3층 구조의 금속층간절연막(120)의 경우, 제1 절연막(121)과 제2 절연막(123)의 경계부분을 기준으로 네가티브한 경사(slope)(135)를 가진 콘택홀(130) 프로파일이 발생 될 수 있다. 제2 절연막(123)과 제3 절연막(125)과의 경계부분을 기준으로 또 다른 경사(137)를 가진 콘택홀(130) 프로파일이 발생 될 수 있다. Referring to FIG. 2, a contact hole 130 exposing the first aluminum layer pattern 110 is formed by selectively etching the interlayer dielectric layer 120 having a three-layer structure. At this time, in the process of etching the interlayer insulating film 120, the etching rate difference may occur due to the insulating film having a different characteristic. In the case of the three-layer interlayer insulating film 120, a contact hole 130 profile having a negative slope 135 is formed based on a boundary between the first insulating film 121 and the second insulating film 123. Can be caused. A contact hole 130 profile having another slope 137 may be generated based on a boundary between the second insulating layer 123 and the third insulating layer 125.

콘택홀(130) 바닥면은 제1 알루미늄막 패턴(110)을 식각종료층(stop layer)으로 이용하여, 반사방지막 패턴(111)의 상부표면이 노출되게 금속층간절연막(120)을 선택적으로 식각한다. 계속해서 반사방지막 패턴(111)을 더 식각하여 제1 알루미늄막 패턴(110)의 상부 표면을 노출시킨다. 이때, 제1 알루미늄막 패턴(110)의 상부 표면으로부터 제1 알루미늄막 패턴(110)을 더 식각하여 리세스홈(130a)이 유발되게 한다. 리세스홈(130a)은 제1 알루미늄막 패턴(110)의 노출을 신뢰성 있게 할 수 있다. The bottom surface of the contact hole 130 selectively etches the interlayer dielectric layer 120 using the first aluminum layer pattern 110 as a stop layer to expose the upper surface of the antireflection layer pattern 111. do. Subsequently, the anti-reflection film pattern 111 is further etched to expose the upper surface of the first aluminum film pattern 110. At this time, the first aluminum film pattern 110 is further etched from the upper surface of the first aluminum film pattern 110 to cause the recess groove 130a. The recess groove 130a may reliably expose the first aluminum film pattern 110.

도 3을 참조하면, 제1 알루미늄 패턴(110)의 리세스홈(130a) 표면이 대기 중에 노출될 경우, 제1 알루미늄 패턴(110)의 리세스홈(130a) 표면에 자연산화막(131)이 유발될 수 있다.Referring to FIG. 3, when the surface of the recess groove 130a of the first aluminum pattern 110 is exposed to the air, a natural oxide film 131 may be formed on the surface of the recess groove 130a of the first aluminum pattern 110. May be induced.

도 4를 참조하면, 제1 알루미늄막 패턴(110)의 리세스홈(131a) 표면에 선택적 화학기상증착방법을 이용하여 제2 알루미늄막(140)을 성장시킨다. 제2 알루미늄 막(140)을 성장시키기 이전에, 선택적 화학기상증착 챔버 내로 반도체기판(100)을 로딩한 후, 유발된 자연산화막(도 3의 131)을 제거하기 위한 식각공정을 수행한다. Referring to FIG. 4, the second aluminum film 140 is grown on the surface of the recess groove 131a of the first aluminum film pattern 110 by using a selective chemical vapor deposition method. Before growing the second aluminum film 140, the semiconductor substrate 100 is loaded into the selective chemical vapor deposition chamber, and then an etching process for removing the induced natural oxide film (131 of FIG. 3) is performed.

식각공정은 선택적 화학기상증착 챔버 내에 아르곤가스를 공급한 후, 고주파 (RF;radio frequency) 교류(AC) 바이어스를 인가하여 이온화된 아르곤을 형성하고, 반도체기판(100)에 백바이어스(back bias)를 인가하여 수행될 수 있다. 백바이어스에 의해 반도체기판으로 끌려나간 아르곤 이온(Ar+)이 제1 알루미늄막 패턴(110)의 리세스홈(130a) 표면에 유발된 자연산화막을 제거한다. In the etching process, argon gas is supplied into the selective chemical vapor deposition chamber, and then ionized argon is formed by applying a radio frequency (AC) bias, and a back bias is applied to the semiconductor substrate 100. It can be performed by applying. Argon ions (Ar + ) attracted to the semiconductor substrate by the back bias remove the natural oxide film caused on the surface of the recess groove 130a of the first aluminum film pattern 110.

자연산화막(131)이 제거된 제1 알루미늄막 패턴(110)의 리세스홈(130a)의 표면은 제2 알루미늄막을 성장시키는 웨팅층(wetting layer) 및 시드층(seed layer)역할을 할 수 있다. The surface of the recess groove 130a of the first aluminum film pattern 110 from which the natural oxide film 131 is removed may serve as a wetting layer and a seed layer for growing the second aluminum film. .

선택적 화학기상증착방법은 하지막 의존성을 이용하여 절연층 상의 제2 알루미늄막의 증착을 배제하고, 금속층 상에 선택적으로 제2 알루미늄막을 증착한다. 즉, 금속층간절연막(140) 또는 자연산화막(131)이 유발된 제1 알루미늄막 패턴(110) 상에는 알루미늄이 실질적으로 증착되지 않게 된다. 이에 반해, 금속막 예컨대, 자연산화막(131)이 제거된 제1 알루미늄막 패턴(110)의 리세스홈(130a)의 표면 상에 제2 알루미늄막의 증착이 선택적으로 일어난다. The selective chemical vapor deposition method utilizes the underlying film dependency to exclude the deposition of the second aluminum film on the insulating layer, and selectively deposit the second aluminum film on the metal layer. That is, aluminum is not substantially deposited on the first aluminum film pattern 110 in which the metal interlayer insulating film 140 or the natural oxide film 131 is induced. In contrast, deposition of the second aluminum film selectively occurs on the surface of the recess groove 130a of the first aluminum film pattern 110 from which the metal film, for example, the natural oxide film 131 is removed.

알루미늄콘택을 형성하기 위해, 화학기상증착방법을 이용하여 제1 알루미늄을 시드층으로 얇게 형성하고, 물리기상증착방법을 이용한 제2 알루미늄을 형성한 후, 제2 알루미늄을 콘택홀 내부로 깊게 채우기 위한 고온의 열처리 공정을 이용하 는 방법을 고려할 수 있다. 이때, 웨팅층으로 티타늄막 및 티타늄질화막이 제1 알루미늄을 증착하기 이전에 화학기상증착방법으로 형성될 수 있다.  In order to form an aluminum contact, the first aluminum is thinly formed as a seed layer using a chemical vapor deposition method, and after forming the second aluminum using a physical vapor deposition method, the second aluminum is deeply filled into the contact hole. Consideration may be given to using a high temperature heat treatment process. In this case, the titanium film and the titanium nitride film as the wetting layer may be formed by a chemical vapor deposition method before depositing the first aluminum.

그런데, 네가티브한 경사를 가진 콘택홀 프로파일로 인해 웨팅층이 불균일하게 증착될 수 있다. 불균일한 웨팅층 상에 증착되는 제1 알루미늄막은 콘택홀 내부에서 불균일하게 증착되거나, 불완전하게 채워질 수 있다. 제2 알루미늄막을 콘택홀 내부로 깊게 유입하기 위한 열처리 공정 시, 보이드와 같은 채움불량이 발생 될 수 있다. However, due to the contact hole profile having a negative slope, the wetting layer may be unevenly deposited. The first aluminum film deposited on the nonuniform wetting layer may be nonuniformly deposited or incompletely filled in the contact hole. In the heat treatment process for deeply introducing the second aluminum film into the contact hole, a filling defect such as a void may occur.

이를 배제하기 위해, 본 발명의 실시예는 제1 알루미늄막 패턴(110)의 표면층을 제2 알루미늄막(140)의 웨팅층 및 시드층으로 이용한다. 제2 알루미늄막(140)은 선택적 화학기상증착방법에 의해 제1 알루미늄막 패턴(110)의 표면으로부터 성장되고, 콘택홀(130) 측면의 절연층으로부터의 성장은 실질적으로 배제된다. In order to exclude this, an embodiment of the present invention uses the surface layer of the first aluminum film pattern 110 as the wetting layer and the seed layer of the second aluminum film 140. The second aluminum film 140 is grown from the surface of the first aluminum film pattern 110 by a selective chemical vapor deposition method, and growth from the insulating layer on the side of the contact hole 130 is substantially excluded.

이에 따라, 콘택을 위한 알루미늄막 증착 시, 콘택홀(130) 상부 모서리 부분에서 발생되는 오버행 및 보이드 발생을 방지할 수 있다. 제2 알루미늄막(140)이 콘택홀(130) 내부를 불량없이 채울 수 있어 콘택 저항을 감소시킬 수 있다. 또한, 제1 알루미늄막 패턴(110)의 표면을 제2 알루미늄막(140)을 증착하기 위한 시드층으로 이용함으로써, 웨팅층의 증착 공정을 생략할 수 있다. Accordingly, when the aluminum film for contact is deposited, it is possible to prevent the overhang and voids generated in the upper edge portion of the contact hole 130. The second aluminum layer 140 may fill the inside of the contact hole 130 without defect, thereby reducing the contact resistance. In addition, by using the surface of the first aluminum film pattern 110 as a seed layer for depositing the second aluminum film 140, the deposition process of the wetting layer can be omitted.

도 5 및 도 6을 참조하면, 상부배선을 위해 물리기상증착방법으로 제3 알루미늄막(150)을 증착한다. 제3 알루미늄막(150)을 증착하기 이전에, 반도체기판(100) 상에 제1 열처리 공정을 수행한다. 제1 열처리 공정은 상부배선을 형성하는 물리기상증착 챔버 내에서 연속적으로 수행될 수 있다. 제1 열처리공정은 물리 기상증착 챔버 내에 반도체기판(100)을 로딩한 후, 히팅을 이용해 실질적으로 반도체기판(100)에 열을 가한 상태에서 아르곤가스를 공급하여 제2 알루미늄막(140)을 리플로우 시킨다. 제2 알루미늄막의 리플로우에 의해 제2 알루미늄막(140)의 표면 거칠기(roughness)가 완화될 수 있다. 또한, 제2 알루미늄막(140)의 유동이 활발히 일어나 콘택홀(130) 내부에서 성장된 제2 알루미늄막(140)이 치밀하게 될 수 있다. 5 and 6, a third aluminum film 150 is deposited by physical vapor deposition for the upper wiring. Before depositing the third aluminum film 150, a first heat treatment process is performed on the semiconductor substrate 100. The first heat treatment process may be continuously performed in the physical vapor deposition chamber forming the upper wiring. In the first heat treatment process, the semiconductor substrate 100 is loaded into the physical vapor deposition chamber, and then argon gas is supplied in a state in which heat is applied to the semiconductor substrate 100 using heating to ripple the second aluminum layer 140. Low The surface roughness of the second aluminum film 140 may be relaxed by the reflow of the second aluminum film. In addition, since the flow of the second aluminum film 140 is actively generated, the second aluminum film 140 grown in the contact hole 130 may be denser.

제3 알루미늄막(150) 상에 반사방지막 예컨대, 티타늄질화막(151)을 증착한 후, 제2 열처리 공정을 수행한다. 제2 열처리 공정은 제3 알루미늄막(150)을 상대적으로 낮은 온도에서 진행될 수 있다. 콘택홀(130) 내부에 채워진 제2 알루미늄막(140)으로 인해, 콘택홀 내부로 도전물질을 깊게 유입하기 위한 열처리 공정보다 낮은 온도에서 진행될 수 있다. 이에 따라, 열부하(thermal buddget)에 따른 콘택 저항을 감소시킬 수 있다. After depositing an anti-reflection film such as a titanium nitride film 151 on the third aluminum film 150, a second heat treatment process is performed. The second heat treatment process may proceed the third aluminum film 150 at a relatively low temperature. Due to the second aluminum layer 140 filled in the contact hole 130, the process may be performed at a lower temperature than a heat treatment process for deeply introducing a conductive material into the contact hole. Accordingly, the contact resistance due to the thermal budd can be reduced.

제3 알루미늄막(150) 및 티타늄질화막(151)을 패터닝하여 상부배선과 하부배선과 전기적으로 접속하는 배선구조를 형성한다. The third aluminum film 150 and the titanium nitride film 151 are patterned to form a wiring structure electrically connected to the upper wiring and the lower wiring.

이상 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않으며, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능함은 당연하다. Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

지금까지 설명한 바와 같이, 본 발명에 따른 반도체 소자의 연결배선 형성방법은, 하부배선을 웨팅층 및 시드층으로 이용하여 콘택홀 내부에만 선택적으로 알루미늄막을 증착하여 보이드 발생을 방지하여 균일하게 채울 수 있다. As described above, in the method of forming the connection wiring of the semiconductor device according to the present invention, by using the lower wiring as the wetting layer and the seed layer, an aluminum film may be selectively deposited only inside the contact hole to prevent voids and to be uniformly filled. .

이에 따라, 낮은 접촉저항을 갖는 금속콘택을 형성하여 신뢰성 있는 반도체소자를 형성할 수 있다. 또한 공정을 단순화할 수 있어 제조단가를 절감할 수 있다. Accordingly, it is possible to form a reliable semiconductor device by forming a metal contact having a low contact resistance. In addition, the process can be simplified, reducing manufacturing costs.

Claims (7)

반도체기판 상에 제1 알루미늄막을 포함하는 하부배선을 형성하는 단계;Forming a lower wiring including a first aluminum film on the semiconductor substrate; 상기 하부배선을 절연시키는 금속층간절연막을 형성하는 단계;Forming a metal interlayer insulating film to insulate the lower wiring; 상기 금속층간절연막을 선택적으로 식각하여 상기 제1 알루미늄막의 상부 표면을 노출시키는 콘택홀을 형성하는 단계; Selectively etching the interlayer dielectric layer to form a contact hole exposing an upper surface of the first aluminum layer; 상기 제1 알루미늄막을 상부 표면으로부터 더 식각하여 리세스홈을 형성하는 단계; Etching the first aluminum film further from an upper surface to form a recess groove; 상기 리세스 홈이 형성된 제1 알루미늄막에 유발된 표면 산화막을 제거하는 단계; 및Removing the surface oxide film caused on the first aluminum film in which the recess groove is formed; And 상기 표면산화막이 제거된 제1 알루미늄막의 표면을 시드층으로 한 선택적 화학기상증착 방법을 이용하여 상기 금속층간절연막 상에는 제2 알루미늄막의 성장을 배재하고, 상기 제1 알루미늄막 표면 상에는 제2 알루미늄막을 성장시켜 상기 콘택홀 내부에 연결콘택을 형성하는 단계를 포함하는 반도체소자의 연결배선 형성방법.By using a selective chemical vapor deposition method using the surface of the first aluminum film from which the surface oxide film has been removed as a seed layer, growth of the second aluminum film is excluded on the interlayer insulating film, and a second aluminum film is grown on the surface of the first aluminum film. And forming a connection contact in the contact hole. 삭제delete 제1항에 있어서,The method of claim 1, 상기 표면 산화막의 제거는 상기 선택적 화학기상 증착의 전 단계로 연속하 여 이온화된 아르곤을 이용한 식각공정으로 수행하는 반도체소자의 연결배선 형성방법.And removing the surface oxide film by an etching process using ionized argon continuously before the selective chemical vapor deposition. 제1항에 있어서,The method of claim 1, 상기 연결콘택을 형성하는 단계 이후에,After forming the connection contact, 상기 제2 알루미늄막 상에 열처리 공정을 수행하여 상기 제2 알루미늄막을 리플로우 시키는 단계; 및Reflowing the second aluminum film by performing a heat treatment process on the second aluminum film; And 상기 리플로우된 제2 알루미늄막에 연결되는 상부배선을 상기 금속층간절연막 상에 형성하는 단계를 더 포함하는 반도체소자의 연결배선 형성방법.And forming an upper wiring connected to the reflowed second aluminum film on the interlayer insulating film. 제4항에 있어서,The method of claim 4, wherein 상기 상부배선은 제3 알루미늄막을 물리기상증착방법을 이용하여 형성하는 반도체소자의 연결배선 형성방법.The upper wiring is a method of forming a connection wiring of a semiconductor device to form a third aluminum film using a physical vapor deposition method. 제4항에 있어서,The method of claim 4, wherein 상기 열처리 공정은 상기 상부배선을 증착하는 물리기상증착 장비에서 상기 상부배선을 증착하기 이전에 인 시츄(in-situ)로 수행하는 반도체소자의 금속배선 형성방법.The heat treatment process is a metal wiring forming method of a semiconductor device performed in-situ prior to depositing the upper wiring in the physical vapor deposition equipment for depositing the upper wiring. 제1항에 있어서,The method of claim 1, 상기 하부배선은 제1 알루미늄막 상부에 반사방지막을 더 포함하고, 상기 콘택홀을 형성하는 단계는 상기 금속층간절연막을 선택적으로 식각한 후, 상기 반사방지막을 더 식각하여 제1 알루미늄막을 노출시키는 단계를 더 포함하는 반도체소자의 금속배선 형성방법.The lower interconnection further includes an anti-reflection film on the first aluminum layer, and the forming of the contact hole may include selectively etching the interlayer dielectric layer and then etching the anti-reflection layer to expose the first aluminum layer. Metal wiring forming method of a semiconductor device further comprising.
KR1020060137186A 2006-12-28 2006-12-28 Method of fabricating interconnection in semicondutor device KR100877095B1 (en)

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