KR100687869B1 - Method of forming semiconductor condtact - Google Patents

Method of forming semiconductor condtact Download PDF

Info

Publication number
KR100687869B1
KR100687869B1 KR1020040082649A KR20040082649A KR100687869B1 KR 100687869 B1 KR100687869 B1 KR 100687869B1 KR 1020040082649 A KR1020040082649 A KR 1020040082649A KR 20040082649 A KR20040082649 A KR 20040082649A KR 100687869 B1 KR100687869 B1 KR 100687869B1
Authority
KR
South Korea
Prior art keywords
film
alps
depositing
forming
contact
Prior art date
Application number
KR1020040082649A
Other languages
Korean (ko)
Other versions
KR20060033499A (en
Inventor
은병수
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020040082649A priority Critical patent/KR100687869B1/en
Publication of KR20060033499A publication Critical patent/KR20060033499A/en
Application granted granted Critical
Publication of KR100687869B1 publication Critical patent/KR100687869B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 반도체 소자의 콘택 형성방법에 관한 것으로 반도체기판 위에 층간절연막을 식각하여 콘택홀을 형성하는 단계와 상기 콘택홀에 Nb 막을 증착하는 단계와 상기 Nb 막 상에 ALPS Al 시드막을 증착하는 단계와 상기 ALPS Al 막상에 고온의 Al 막을 증착하는 단계로 부터 콘택을 형성하여 이상물질인 TiAl3의 생성을 막아 비아저항을 낮추고, 비아의 매립불량을 방지하며 취약한 EM 특성을 개선할 수 있는 효과가 있다.The present invention relates to a method for forming a contact of a semiconductor device, the method comprising: forming a contact hole by etching an interlayer insulating film on a semiconductor substrate; depositing an Nb film in the contact hole; and depositing an ALPS Al seed film on the Nb film; Forming a contact from the step of depositing a high temperature Al film on the ALPS Al film to prevent the generation of the abnormal material TiAl 3 has the effect of reducing the via resistance, preventing vias buried poor and improve the weak EM characteristics. .

ALPS Al 시드(seed), Nb, EM(Electro Migration) ALPS Al seed, Nb, EM (Electro Migration)

Description

반도체 소자의 콘택 형성방법{Method of forming semiconductor condtact}Method of forming a semiconductor contact

도 1은 종래기술에 따른 콘택 형성 과정에서 TiAl3에 의해 형성되는 보이드를 보여주는 도면이다.1 is a view showing a void formed by TiAl 3 in the process of forming a contact according to the prior art.

도 2a 내지 2e는 본 발명의 일 실시예에 따른 반도체 소자의 콘택 형성 과정을 순차적으로 도시한 공정 단면도이다. 2A through 2E are cross-sectional views sequentially illustrating a process of forming a contact of a semiconductor device according to an embodiment of the present invention.

*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 반도체기판 12 : 층간절연막10 semiconductor substrate 12 interlayer insulating film

13 : 콘택홀 14 : Nb 막13 contact hole 14 Nb film

16 : ALPS Al 시드(seed)막 18 : Al 막16: ALPS Al seed film 18: Al film

본 발명은 반도체 소자의 콘택 형성 방법에 관한 것으로, 특히 ALPS(Aluminum Low Pressure Seed) 공정에서 TiAl3의 생성에 의한 비아(via) 매립 문제를 해결하여 EM 신뢰성 및 비아저항 특성을 향상시키는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact in a semiconductor device, and more particularly, to a method for improving EM reliability and via resistance characteristics by solving a via filling problem caused by TiAl 3 generation in an ALPS (Aluminum Low Pressure Seed) process. will be.

최근까지 반도체소자 제조에 있어서, 콘택 또는 비아(via) 형성 공정은 텅스 텐 플러그 및 텅스텐 에치백(each-back)을 이용한 공정이 주로 사용되어 왔다. 텅스텐 플러그 및 텅스텐 에치백 공정의 경우, 오랜 기간 동안 많은 연구가 진행되어 공정 안정성이 높다는 장점이 있는 반면, 텅스텐 플러그의 장벽 금속(barrier metal)과 텅스텐 플러그 및 텅스텐 에치백 공정으로 인하여 공정수가 많아 공정 단가가 높다는 단점이 있다.Until recently, in the manufacturing of semiconductor devices, a process using a tungsten plug and a tungsten etch-back has been mainly used as a contact or via forming process. In the case of tungsten plug and tungsten etchback process, many researches have been conducted for a long time, and thus the process stability is high.However, due to the barrier metal of tungsten plug and the tungsten plug and tungsten etchback process, the number of processes is high. The disadvantage is that the unit price is high.

따라서 기존의 텅스텐 플러그 공정과는 달리 텅스텐 플러그 및 에치백 공정을 생략함으로써 비아(Via)와 금속 배선을 동시에 형성할 수 있는 ALPS(Aluminum Low Pressure Seed) 방법을 사용하여 원가를 절감하고 공정을 단순화하고 있다.Therefore, unlike the conventional tungsten plug process, by eliminating the tungsten plug and etch back process, the ALPS (Aluminum Low Pressure Seed) method, which can form vias and metal wires simultaneously, reduces costs and simplifies the process. have.

기존의 ALPS(Aluminum Low Pressure Seed) 공정은 우선, 장벽금속으로 컬리메이트 Ti(collimate Ti) 막을 500Å 정도의 두께로 증착한 후 상온의 ALPS 챔버(chamber)에서 ALPS Al 시드(seed)막을 3000Å 정도의 두께로 증착한다. 이후 450℃의 고온 챔버에서 90초 정도 사전가열(preheating)한 후 5000Å의 두께의 고온의 Al 막을 증착한다. The conventional ALPS (Aluminum Low Pressure Seed) process first deposits a collimate Ti (collimate Ti) film with a barrier metal thickness of about 500 ms and then deposits an ALPS Al seed film of about 3000 ms in an ALPS chamber at room temperature. Deposit to thickness. After the preheating for about 90 seconds in a high temperature chamber of 450 ℃ and deposited a high-temperature Al film of 5000 Å thickness.

상기 공정에서 ALPS Al 시드막을 비아의 측면에서 바닥까지 단선 없이 연속적으로 증착하는 것이 중요한데, 증착된 ALPS Al 시드막에 단선이 발생하면 이후에 증착되는 Al막이 웨팅 되지 않아 비아 바닥까지 골고루 매립되지 않기 때문이다. In this process, it is important to continuously deposit the ALPS Al seed film from the side of the via to the bottom without disconnection, because if a disconnection occurs in the deposited ALPS Al seed film, the Al film deposited thereafter is not wetted and is not evenly filled to the bottom of the via. to be.

그런데 종래기술에 의한 ALPS(Aluminum Low Pressure Seed) 공정에서는 Al막을 증착하기 위한 사전가열 공정 중 비아 측면에 코팅된 ALPS Al 시드막이 비아 하부의 Ti막과 반응하여 TiAl3로 변화하는 문제가 발생한다. However, in the ALPS process, the ALPS Al seed film coated on the side of the via reacts with the Ti film under the via to change to TiAl 3 during the preheating process for depositing the Al film.

이렇게 형성된 TiAl3는 Al 배선의 비저항을 증가 시킬 뿐만 아니라 EM(ElectroMigration)에 대한 저항을 취약하게 한다. 더욱이 비아 입구에 형성된 TiAl3에 의해 ALPS Al 시드막에 단선이 발생하여 이후에 증착되는 Al막이 비아에 골고루 매립되지 않는 문제가 발생한다. Thus formed TiAl 3 not only increases the specific resistance of the Al wiring but also weakens the resistance to EM (ElectroMigration). In addition, a disconnection occurs in the ALPS Al seed film due to TiAl 3 formed at the inlet of the via, so that the Al film deposited thereafter is not evenly embedded in the via.

이러한 경우, 비아(via)의 저면(Bottom)에 도 1에 도시한 바와 같은 보이드(void)가 형성되어 비아저항을 상승시키는 문제점과 아울러 비아 EM을 측정하는 경우 보이드가 형성된 비아에서 집중적인 불량(Fail) 현상이 발견되어 소자의 신뢰성에도 상당한 문제점이 발생한다.In this case, a void as shown in FIG. 1 is formed on the bottom of the via, thereby increasing the via resistance, and when the via EM is measured, intensive defects in the void having the via ( Fail phenomenon is found, which causes considerable problems in device reliability.

본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 콘택홀에 장벽금속으로 Nb 막을 증착하여 TiAl3가 형성되는 것을 방지함으로써, 비아에 의한 보이드가 형성되는 것을 방지하여 저항을 낮추고, EM 특성을 향상시킬 수 있는 반도체 소자의 콘택 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, by depositing an Nb film with a barrier metal in the contact hole to prevent the formation of TiAl 3 , to prevent the formation of voids by vias to lower the resistance, EM It is an object of the present invention to provide a method for forming a contact of a semiconductor device capable of improving characteristics.

상기 목적을 달성하기 위해 본 발명의 반도체소자의 콘택 형성 방법은 반도체기판상의 층간절연막을 형성한 후, 층간 절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계와, 상기 콘택홀에 Nb 막을 증착하는 단계와, 상기 Nb막 상에 ALPS Al 시드 막을 증착하는 단계와, 상기 ALPS Al막 상에 Al 막을 증착하는 단계를 포함하여 이루어진다. In order to achieve the above object, the method for forming a contact of a semiconductor device of the present invention comprises forming an interlayer insulating film on a semiconductor substrate, selectively etching the interlayer insulating film, and forming a contact hole, and depositing a Nb film in the contact hole. And depositing an ALPS Al seed film on the Nb film, and depositing an Al film on the ALPS Al film.                     

상기 증착되는 Nb 막은 250~350Å의 두께로 형성되며, ALPS Al 시드막은 1400~1600Å의 두께로 증착되는 것이 바람직하다.The deposited Nb film is formed to a thickness of 250 ~ 350Å, the ALPS Al seed film is preferably deposited to a thickness of 1400 ~ 1600Å.

또한, 상기 Al 막을 증착하는 단계는 440℃~460℃로 사전가열하는 단계와 고온의 Al 막을 250~350Å의 두께로 증착하는 단계를 포함하여 이루어진다.In addition, the step of depositing the Al film comprises a step of preheating to 440 ℃ ~ 460 ℃ and depositing a high temperature Al film to a thickness of 250 ~ 350Å.

본 발명의 이점 및 특징, 그리고 이를 달성하는 방법은 첨부된 도면과 함께 상세하게 후술되어 있는 실시예들을 참조하면 명확해질 것이다. 그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라, 이 실시예들을 벗어나 다양한 형태로의 구현이 가능하다. 한편, 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성 요소를 지칭한다.Advantages and features of the present invention, and a method of achieving the same will be apparent with reference to the embodiments described below in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms beyond the embodiments. In addition, like reference numerals refer to like elements throughout the specification.

이하 도면에 따라 상기 발명의 실시예를 상세히 설명한다. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a는 본 발명의 일 실시예에 따른 반도체 소자의 콘택 형성 과정 중 콘택홀을 형성하는 방법을 도시한 공정 단면도이다.2A is a cross-sectional view illustrating a method of forming a contact hole during a contact forming process of a semiconductor device according to an embodiment of the present invention.

콘택홀(13)은 도 2a에 도시된 바와 같이, 반도체기판(10)상에 층간절연막(12)을 형성한 후, 층간절연막(12)을 선택적으로 식각(eaching)하여 반도체기판(10)의 표면 일부 영역을 노출시켜 형성한다. As shown in FIG. 2A, the contact hole 13 forms an interlayer insulating film 12 on the semiconductor substrate 10, and then selectively etches the interlayer insulating film 12 to form the semiconductor substrate 10. It is formed by exposing a portion of the surface.

층간절연막(12)은 통상의 절연막의 두께보다 두껍게 형성하며, FSG(Fluoro Silicate Glass), 블랙다이아몬드, 실크 등의 저유전율 절연막 가운데 하나로 형성하는 것이 바람직하다.The interlayer insulating film 12 is formed to be thicker than the thickness of an ordinary insulating film, and preferably formed of one of low dielectric constant insulating films such as Fluoro Silicate Glass (FSG), black diamond, and silk.

도 2b는 본 발명의 일 실시예에 따른 반도체 소자의 콘택 형성 과정 중 콘택홀에 장벽금속인 Nb막의 증착 모습을 도시한 공정 단면도이다. FIG. 2B is a cross-sectional view illustrating a deposition process of an Nb film as a barrier metal in a contact hole during a contact forming process of a semiconductor device according to an exemplary embodiment of the present invention.                     

도 2b를 참고하면 본 발명의 일실시예에 의한 장벽금속의 증착은 우선, 형성된 콘택홀(13)의 부산물을 제거하기 위해 RF(Radio Frequency) 건식세정을 실시한 후, 콘택홀의 일정영역 상에 이루어진다. 상기 장벽금속으로 사용하는 금속 Nb(니오비움)은 원자번호 41, 원자량 92.9064, 녹는점 2468℃, 끓는점 3300℃, 비중 8.56(25℃)인 성질을 갖는 금속이다.Referring to FIG. 2B, the deposition of the barrier metal according to an embodiment of the present invention is performed on a predetermined region of the contact hole after performing RF (Radio Frequency) dry cleaning to remove the by-products of the formed contact hole 13. . Metal Nb (niobium) used as the barrier metal is a metal having a property of atomic number 41, atomic weight 92.9064, melting point 2468 ° C, boiling point 3300 ° C, specific gravity 8.56 (25 ° C).

증착방법으로는 고전압에 의해 이온화된 Ar 가스를 사용하여 타겟으로부터 금속 입자를 떼어내어 금속박막을 입히는 방법인 스퍼터링(sputtering)이나 기체를 열분해하여 화학반응을 일으키게 하여 증착하는 CVD(Chemical Vapor Deposition)를 이용할 수 있다.As a deposition method, CVD (Chemical Vapor Deposition) is formed by sputtering, which is a method of removing metal particles from a target and coating a metal thin film by using Ar gas ionized by high voltage, and thermally decomposing a gas to cause a chemical reaction. It is available.

본 발명의 일실시예에 의한 장벽금속 Nb막(14)은 전력 6kW 조건 이온화된 Ar 가스의 유량이 55sccm인 공정조건에서 250Å~350Å 두께로 증착된다. 종래 기술과 달리 장벽금속으로 컬리메이트 Ti 막 대신 Nb막(14)을 증착함에 따라 ALPS 공정중 Al막을 증착하기 위한 사전 가열 과정에서 이상물질인 TiAl3의 발생을 방지할 수 있는바 이하 공정에서 자세히 살펴본다.The barrier metal Nb film 14 according to an embodiment of the present invention is deposited to a thickness of 250 kPa to 350 kPa under a process condition in which a flow rate of ionized Ar gas is 55 sccm under a power of 6 kW. Unlike the prior art, by depositing the Nb film 14 instead of the coarse Ti film as the barrier metal, it is possible to prevent the occurrence of an abnormal substance TiAl 3 in the pre-heating process for depositing the Al film during the ALPS process. Take a look.

도 2c는 본 발명의 일 실시예에 따른 반도체 소자의 콘택 형성 과정에서 ALPS Al 시드막이 증착되는 모습을 도시한 공정 단면도이다.2C is a cross-sectional view illustrating a process of depositing an ALPS Al seed film during a contact formation process of a semiconductor device according to an embodiment of the present invention.

ALPS 공정은 저온에서 ALPS Al(16)을 증착한 다음 바로 고온에서 Al을 증착하여 비아(via)와 라인을 동시에 형성하므로 기존의 텅스텐 플러그 및 에치백 공정을 생략할 수 있는 장점과 비아 자체의 낮은 비저항으로 인하여 비아 자체의 저항도 낮출 수 있기 때문에 소자의 속도를 향상시킬 수 있는 장점을 갖는다. The ALPS process simultaneously deposits ALPS Al (16) at low temperature and then Al at high temperature to form vias and lines at the same time, thus eliminating the conventional tungsten plug and etch back process and lowering the vias itself. Due to the specific resistance, the resistance of the via itself can also be lowered, thereby increasing the speed of the device.                     

도 2c를 참고하면 ALPS Al 시드막(16)은 1400Å~1600Å의 두께로 Nb막(14) 상에 증착 된다. 이때, ALPS Al 시드막(16)의 증착은 ALPS 챔버(chamber)에서 15-20kW의 전력으로 이온화된 Ar 가스가 5~10 sccm 유량을 갖고, 압력 0.3~0.4 mtorr, 투사 거리(throw distance) 15~25cm 인 공정조건에서 이루어진다. 여기서, 낮은 전력으로 증착하는 이유는 ALPS Al 시드(16)의 증착 속도를 늦추어 비아(via) 속으로 Al이 모세관 현상으로 쉽게 타고 들어가 비아필(via fill)하기 위함이다. Referring to FIG. 2C, an ALPS Al seed film 16 is deposited on the Nb film 14 to a thickness of 1400 Å to 1600 Å. At this time, the deposition of the ALPS Al seed film 16 is the Ar gas ionized with an electric power of 15-20kW in the ALPS chamber has a flow rate of 5 ~ 10 sccm, pressure 0.3 ~ 0.4 mtorr, throw distance 15 Process conditions of ~ 25cm The reason for the low power deposition is to slow down the deposition rate of the ALPS Al seed 16 so that Al can easily enter the via into capillarity via via fill.

한편, 증착되는 ALPS Al 시드(16)는 단선없이 비아의 측면에서 바닥까지 연속적으로 증착되어야한다. 그래야 이 후에 Al을 증착할 때 동일한 물질위에서 쉽게 웨팅(wetting)되어 비아의 바닥까지 골고루 매립이 가능하기 때문이다. Meanwhile, the deposited ALPS Al seed 16 should be continuously deposited from the side of the via to the bottom without disconnection. This is because when later Al is deposited, it is easily wetted on the same material and evenly fills the bottom of the via.

도 2d는 본 발명의 일 실시예에 따른 반도체 소자의 콘택 형성 과정 중 Al막의 증착 방법을 도시한 공정 단면도이다.      2D is a cross-sectional view illustrating a method of depositing an Al film during a contact forming process of a semiconductor device according to an embodiment of the present invention.

도 2d에서 도시한 바와 같이, 본 발명의 일 실시예에 따른 Al(18)막의 증착은 고온의 Al 챔버(chamber)에서 90초 정도 사전 가열(preheating)을 실시하는 단계와 고온의 Al막(18)을 증착하는 단계로 이루어진다.As shown in FIG. 2D, the deposition of the Al 18 film according to an embodiment of the present invention is performed by preheating for about 90 seconds in a high temperature Al chamber and the high temperature Al film 18. ) Is deposited.

상기 사전 가열 단계에서 이미 증착된 ALPS Al 시드막(seed)이 장벽금속으로 사용된 Nb막(14)과 반응하여 TiAl3로 변화하지 않으므로, 장벽금속으로 컬리메이트 Ti를 사용한 경우와 같이 증착된 ALPS Al 시드막의 단선이 발생하지 않는다. 상기 고온의 Al막(18)의 증착은 3-5kW의 전력으로 이온화된 Ar 가스가 압력 1~1.5 mtorr에서 40~50 sccm 유량을 갖고, 투사 거리(throw distance) 4~6cm인 공정조건에서 6000Å~7000Å의 두께로 이루어진다. Since the ALPS Al seed film deposited in the pre-heating step does not change to TiAl 3 by reacting with the Nb film 14 used as the barrier metal, the ALPS deposited as in the case of using the titanium Ti as the barrier metal. Disconnection of the Al seed film does not occur. The high temperature Al film 18 is deposited at 6000 kW under process conditions in which Ar gas ionized at a power of 3-5 kW has a flow rate of 40 to 50 sccm at a pressure of 1 to 1.5 mtorr and a throw distance of 4 to 6 cm. It is made up to a thickness of 7000Å.

이때, 증착되는 Al막(18)은 단선 없이 증착된 ALPS Al 시드(16)에 웨팅(wetting)되어 비아의 측면에서 바닥까지 골고루 매립된다. 이때, 증착되는 Al막(18) 자체의 선저항 자체도 대단히 감소하여 소자의 속도가 향상된다. At this time, the deposited Al film 18 is wetted to the ALPS Al seed 16 deposited without disconnection and is evenly embedded from the side of the via to the bottom. At this time, the line resistance itself of the deposited Al film 18 itself is also greatly reduced, thereby improving the speed of the device.

또한, 저항이 높은 TiAl3가 형성되지 않으므로 비아(via) 저항이 40% 정도 개선되고, 종래 기술에 비해 두배 정도 개선된 5 정도의 AR(Aspect Ratio, 가로폭과 세로폭의 비) 특성을 갖는 비아(via)의 매립이 가능하다. In addition, since TiAl 3 , which has high resistance, is not formed, the via resistance is improved by about 40%, and has an AR (Aspect Ratio) ratio of about 5, which is about twice the improvement of the prior art. Vias may be buried.

한편, 본 발명의 일 실시예 의해 Nb막(14)을 장벽금속으로 사용하는 경우 얻을 수 있는 또 다른 장점은 EM(Electro Migration)특성의 획기적인 향상이다.On the other hand, according to one embodiment of the present invention is another advantage that can be obtained when using the Nb film 14 as a barrier metal is a significant improvement in the EM (Electro Migration) characteristics.

Nb막(14)을 장벽금속으로 사용하여 TiAl3의 형성을 방지하면, 온도 상승이 없어 장벽금속막과 Al막 사이가 안정된다. 그 결과 EM의 주요확산 경로가 되는 계면 문제가 해결되고, 라이프타임(lifetime)의 증가를 가져와 EM 특성의 신뢰성이 향상된다.When the Nb film 14 is used as the barrier metal to prevent the formation of TiAl 3 , there is no temperature rise, and thus, the barrier metal film and the Al film are stabilized. As a result, the interface problem, which is the main diffusion path of EM, is solved, and the lifetime is increased, thereby improving the reliability of EM characteristics.

고온의 Al 라인까지 증착한 후에는 도 2e에 도시한 바와 같이, Al 라인의 패턴을 생성하게 된다.After deposition up to a high temperature Al line, as shown in FIG. 2E, a pattern of the Al line is generated.

Al 라인의 패턴은 ARC(Anti Reflective coating)막으로 Ti/TiN을 증착한 후 포토리소그라피(photo-lithography) 및 식각(eaching) 공정을 통해 형성한다. 식각 공정은 Al 식각(eaching) 공정과 동일한 조건으로 이루어 진다. 구체적인 공정 조건은 압력이 10 mtorr 이고 Cl2기체의 유량 160 sccm, BCl3의 유량 80 sccm 이다. The Al line pattern is formed by depositing Ti / TiN with an ARC (Anti Reflective coating) film through photo-lithography and etching. The etching process is performed under the same conditions as the Al etching process. Specific process conditions are pressure 10 mtorr, flow rate 160 sccm of Cl 2 gas, flow rate 80 sccm of BCl 3 .

본 발명에 의하면, 콘택홀에 장벽금속으로 Nb 막을 증착하여 TiAl3가 형성되는 것을 방지함으로써, 비아에 의한 보이드가 형성되는 것을 방지하여 저항을 낮추고, EM 특성을 향상시킬 수 있는 반도체 소자의 콘택 형성 방법을 제공할 수 있는 효과가 있다.According to the present invention, by forming an Nb film with a barrier metal in the contact hole to prevent TiAl 3 from being formed, the formation of a contact of a semiconductor device capable of preventing voids from forming vias and lowering resistance and improving EM characteristics. It has the effect of providing a method.

Claims (6)

반도체기판상의 층간절연막을 형성한 후, 층간 절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계와;Forming an interlayer insulating film on the semiconductor substrate and then selectively etching the interlayer insulating film to form contact holes; 상기 콘택홀에 Nb 막을 증착하는 단계와;Depositing an Nb film in said contact hole; 상기 Nb막 상에 ALPS Al 시드 막을 증착하는 단계와;Depositing an ALPS Al seed film on the Nb film; 상기 ALPS Al막 상에 Al 막을 증착하는 단계; Depositing an Al film on the ALPS Al film; 를 포함하여 이루어지는 반도체소자의 콘택 형성 방법.Method for forming a contact of a semiconductor device comprising a. 제 1항에 있어서, 상기 증착되는 Nb 막은 250~350Å의 두께인 것을 특징으로 하는 반도체소자의 콘택 형성 방법.The method of claim 1, wherein the deposited Nb film is 250 to 350 microns thick. 제 1항에 있어서, 상기 증착되는 ALPS Al 시드막은 1400~1600Å의 두께인 것을 특징으로 하는 반도체소자의 콘택 형성 방법.The method of claim 1, wherein the deposited ALPS Al seed film has a thickness of 1400 to 1600 Å. 제 1항에 있어서, 상기 Al 막을 증착하는 단계는 사전 가열하는 단계와;The method of claim 1, wherein depositing the Al film comprises: preheating; 고온의 Al 막을 증착하는 단계;Depositing a hot Al film; 를 포함하여 이루어지는 반도체소자의 콘택 형성 방법.Method for forming a contact of a semiconductor device comprising a. 제 3항에 있어서, 상기 사전가열은 440℃~460℃로 가열하는 것을 특징으로 하는 반도체소자의 콘택 형성 방법.The method of claim 3, wherein the preheating is heated to 440 ° C. to 460 ° C. 5. 제 4항에 있어서, 상기 증착되는 고온의 Al막은 250~350Å의 두께인 것을 특징으로 하는 반도체소자의 콘택 형성 방법.5. The method of claim 4, wherein the deposited high temperature Al film is 250 to 350 microns thick.
KR1020040082649A 2004-10-15 2004-10-15 Method of forming semiconductor condtact KR100687869B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020040082649A KR100687869B1 (en) 2004-10-15 2004-10-15 Method of forming semiconductor condtact

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040082649A KR100687869B1 (en) 2004-10-15 2004-10-15 Method of forming semiconductor condtact

Publications (2)

Publication Number Publication Date
KR20060033499A KR20060033499A (en) 2006-04-19
KR100687869B1 true KR100687869B1 (en) 2007-02-27

Family

ID=37142616

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020040082649A KR100687869B1 (en) 2004-10-15 2004-10-15 Method of forming semiconductor condtact

Country Status (1)

Country Link
KR (1) KR100687869B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11189681B2 (en) 2018-09-03 2021-11-30 Samsung Display Co., Ltd. Organic light emitting diode display and manufacturing method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101907971B1 (en) * 2011-07-07 2018-10-16 주식회사 원익아이피에스 Method of depositing metal for fabricating contact plugs of semiconductor device
USD773538S1 (en) 2015-03-26 2016-12-06 Samsung Electronics Co., Ltd. Refrigerator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020002737A (en) * 2000-06-30 2002-01-10 박종섭 Method of forming a contact plug using a Al in a semiconductor
KR100410690B1 (en) * 2001-12-29 2003-12-18 주식회사 하이닉스반도체 Method for fabricating contact of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020002737A (en) * 2000-06-30 2002-01-10 박종섭 Method of forming a contact plug using a Al in a semiconductor
KR100410690B1 (en) * 2001-12-29 2003-12-18 주식회사 하이닉스반도체 Method for fabricating contact of semiconductor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
1004106900000 *
1020020002737 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11189681B2 (en) 2018-09-03 2021-11-30 Samsung Display Co., Ltd. Organic light emitting diode display and manufacturing method thereof

Also Published As

Publication number Publication date
KR20060033499A (en) 2006-04-19

Similar Documents

Publication Publication Date Title
KR100220935B1 (en) Process for forming metal contact
JP2003273212A (en) Laminate structure and its manufacturing method
KR100687869B1 (en) Method of forming semiconductor condtact
KR100476710B1 (en) Method of forming metal line of semiconductor device
KR100877095B1 (en) Method of fabricating interconnection in semicondutor device
KR20000059312A (en) Method for forming contact of semiconductor device
KR100307827B1 (en) Metal wiring contact formation method of semiconductor device
KR101185853B1 (en) Method for forming metal line of semiconductor device
KR100645930B1 (en) Method for Forming of Copper Line of Semiconductor Device
KR100237682B1 (en) Method of forming interconnector of semiconductor device
JP3745460B2 (en) Wiring formation method of semiconductor device
KR100617046B1 (en) method for forming metal line of semiconductor device
KR100587594B1 (en) Method for forming metal wiring semiconductor device
KR100325597B1 (en) Method for forming contact hole in semiconductor device
KR100241505B1 (en) Method for manufacturing film thwarting diffusion of semiconductor device
KR100623594B1 (en) Methodo for forming Al line of semiconductor device by using refractory metal liner
KR20020048720A (en) A method for forming damascene metal wire using copper
KR100831674B1 (en) Method for forming wire layers of semiconductor device
KR101161665B1 (en) Method for forming multi layer metal wiring of semiconductor device
KR100702803B1 (en) Method for forming metal wiring layer of semiconductor device
KR20120024907A (en) Method for forming metal line of semiconductor device
KR20020002737A (en) Method of forming a contact plug using a Al in a semiconductor
KR20080011618A (en) Method for forming metal interconnection layer of semiconductor device
KR20050087471A (en) Method for forming metal line of semiconductor device
KR19990005816A (en) Contact Forming Method of Semiconductor Device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110126

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee