KR20050009652A - Method of forming metal line in semiconductor device - Google Patents
Method of forming metal line in semiconductor device Download PDFInfo
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- KR20050009652A KR20050009652A KR1020030049467A KR20030049467A KR20050009652A KR 20050009652 A KR20050009652 A KR 20050009652A KR 1020030049467 A KR1020030049467 A KR 1020030049467A KR 20030049467 A KR20030049467 A KR 20030049467A KR 20050009652 A KR20050009652 A KR 20050009652A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것이다.The present invention relates to a method for forming metal wiring of a semiconductor device.
최근 반도체소자가 점차적으로 고집적화 및 고밀도화됨에 따라 다마신 공정을 통해 형성하는 비아에는 저항이 작은 구리를 사용하고 있다.Recently, as semiconductor devices are gradually integrated and densified, copper having low resistance is used for vias formed through the damascene process.
종래 기술에 따라 비아를 형성하는 공정을 설명하면, 금속배선물질이 매몰된층간절연막 상부에 비아홀을 정의하는 포토레지스트 패턴을 형성한 후 이를 식각마스크로 식각공정을 수행하여 비아홀을 형성한다. 이어서 이 비아홀에 금속배선물질을 매립하여 비아를 형성한다.Referring to the process of forming a via according to the prior art, after forming a photoresist pattern defining a via hole on the interlayer insulating film in which the metal wiring material is buried, the via hole is formed by performing an etching process with an etching mask. Subsequently, a metal wiring material is embedded in the via hole to form a via.
이때 비아홀에 매립된 금속배선물질은 구리를 사용하는 데, 이 구리를 비아매립금속으로 사용할 때 다른 막질로 확산되는 것을 방지하기 위해 확산방지막을 형성하게 된다.In this case, the metal wiring material embedded in the via hole uses copper, and when the copper is used as the via buried metal, a diffusion barrier layer is formed to prevent diffusion of the copper into another film.
이 확산방지막으로 SiC막을 주로 사용하는 데, 이 SiC막은 상기 비아홀 매립물질인 구리와 접착력이 불량하여 소자의 특성을 열화시키는 문제점이 있다.The SiC film is mainly used as the diffusion barrier, and the SiC film has a problem of degrading the characteristics of the device due to poor adhesion to copper, which is the via hole filling material.
상술한 문제점을 해결하기 위한 본 발명의 목적은 비아 매립금속인 구리물질과 이의 확산을 방지하기 위한 확산방지막간의 접착력을 증대시켜 소자의 특성열화를 방지할 수 있는 반도체소자의 금속배선 형성방법을 제공함에 있다.An object of the present invention for solving the above problems is to provide a method for forming a metal wiring of a semiconductor device that can prevent the deterioration of the characteristics of the device by increasing the adhesion between the copper material of the via buried metal and the diffusion barrier to prevent the diffusion thereof. Is in.
도 1 및 도 2는 본 발명의 바람직한 실시예인 반도체소자의 금속배선 형성방법을 설명하기 위한 단면도들이다.1 and 2 are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to an exemplary embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10: 층간절연막 12: 비아10: interlayer insulating film 12: via
14: 확산방지막14: diffusion barrier
상술한 목적을 달성하기 위한 본 발명의 사상은 상면이 노출된 비아가 형성된 층간절연막을 형성하는 단계, 상기 층간절연막이 형성된 결과물에 세정공정 및 전처리공정을 수행하는 단계 및 상기 결과물 상에 SiCN막인 확산방지막을 형성하는 단계를 포함한다.The idea of the present invention for achieving the above object is to form an interlayer insulating film having vias exposed through the upper surface, to perform a cleaning process and a pretreatment process on the resultant product formed with the interlayer insulating film and diffusion of a SiCN film on the resultant Forming a protective film.
상기 확산방지막의 유전상수를 낮추기 위해 상기 SiCN막에 SiC막을 형성하는단계를 더 포함하는 것이 바람직하다.It is preferable to further include forming a SiC film on the SiCN film in order to lower the dielectric constant of the diffusion barrier film.
상기 SiCN막은 SiC막에 100~ 2000sccm 정도의 NH3가스 또는 200~ 10000sccm 정도의 N2가스 중 어느 하나의 가스를 통해 도핑하여 형성하는 것이 바람직하다.The SiCN film is preferably formed by doping the SiC film through any one of NH 3 gas of about 100 to 2000 sccm or N 2 gas of about 200 to 10000 sccm.
이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세히 설명한다. 그러나 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있지만 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안 된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해 제공되어지는 것이다. 따라서, 도면에서의 막의 두께 등은 보다 명확한 설명을 강조하기 위해서 과장되어진 것이며, 도면상에서 동일한 부호로 표시된 요소는 동일한 요소를 의미한다. 또한 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다 또는 접촉하고 있다 라고 기재되는 경우에, 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제 3의 막이 개재되어질 수도 있다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, although the embodiments of the present invention may be modified in many different forms, the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Accordingly, the thickness of the film and the like in the drawings are exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings mean the same elements. In addition, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.
도 1 및 도 2는 본 발명의 바람직한 실시예인 반도체소자의 금속배선 형성방법을 설명하기 위한 단면도들이다.1 and 2 are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to an exemplary embodiment of the present invention.
도 1을 참조하면, 금속물질이 매립된 제1 층간 절연막(미도시)상에 제2 층간 절연막(10)을 형성하고, 그 상부에 비아홀을 정의하는 포토레지스트 패턴(미도시)을 형성한 후 이를 식각마스크로 식각공정을 수행하여 비아홀을 형성한다. 이 비아홀에 금속물질을 매립한 후 CMP공정과 같은 평탄화공정을 수행하여 비아(12)를 형성한다.Referring to FIG. 1, after forming a second interlayer insulating film 10 on a first interlayer insulating film (not shown) in which a metal material is embedded, and forming a photoresist pattern (not shown) defining a via hole thereon. The etching process is performed using an etching mask to form a via hole. The via 12 is formed by filling a metal material in the via hole and performing a planarization process such as a CMP process.
한편, 제2 층간절연막(10)은 저유전상수를 가진 저유전막질이고, 비아홀에 매립되어 비아를 형성하는 금속물질은 구리인 것이 바람직하다.On the other hand, the second interlayer insulating film 10 is a low dielectric film having a low dielectric constant, and the metal material buried in the via holes to form vias is preferably copper.
이 결과물에 세정공정 및 전처리 공정을 수행하는 데, 이때 세정공정은 NH3또는 H2플라즈마 공정을 통해 수행한다.The resultant is subjected to a cleaning process and a pretreatment process, wherein the cleaning process is performed through an NH 3 or H 2 plasma process.
도 2를 참조하면, 결과물 상에 SiC막에 질소 이온이 도핑된 SiCN막(14)을 형성한다. 이 SiCN막(14)은 하부의 비아(12)가 확산되는 것을 방지하기 위한 확산방지막이다. SiCN막을 형성하기 위해, SiC막에 수행되는 도핑공정은 100~ 2000sccm 정도의 NH3가스 또는 200~ 10000sccm 정도의 N2가스를 사용한다. 이로써 형성되는 SiCN막은 200Å 정도의 두께이다.Referring to FIG. 2, a SiCN film 14 doped with nitrogen ions is formed on the SiC film. The SiCN film 14 is a diffusion barrier film for preventing the lower via 12 from diffusing. In order to form the SiCN film, the doping process performed on the SiC film uses NH 3 gas of about 100 to 2000 sccm or N 2 gas of about 200 to 10000 sccm. The SiCN film thus formed has a thickness of about 200 GPa.
한편, SiCN막(16) 상부에 SiC막(18)을 더 적층하여 형성함으로써, 확산방지막의 실제 측정되는(effective) 유전상수(k)는 낮아진다. 즉, SiCN막(16)의 유전상수는 5 정도인데, SiCN막(16)과 SiC막(18)이 적층된 막질의 유전상수는 4.5정도로써, 낮은 유전상수를 가질 수 있도록 한다.On the other hand, by further stacking the SiC film 18 on the SiCN film 16, the effective dielectric constant k of the diffusion barrier film is lowered. That is, the dielectric constant of the SiCN film 16 is about 5, and the dielectric constant of the film quality in which the SiCN film 16 and the SiC film 18 are laminated is about 4.5, so that the dielectric constant can be low.
종래에는 이 확산 방지막으로 SiC막을 사용하여 구리물질로 매립된 비아와의 접착력이 저하되는 문제가 있었는데, 본 발명에서는 SiC막에 질소이온을 도핑한 SiCN막을 사용하여 구리물질로 매립된 비아와의 접착력이 증대된다.Conventionally, there was a problem in that the adhesion to the via buried with the copper material was reduced by using the SiC film as the diffusion barrier, but in the present invention, the adhesion with the via buried with the copper material was used using the SiCN film doped with nitrogen ions in the SiC film. Is increased.
다시 말해, 종래의 SiC막을 확산 방지막으로 사용할 경우, 구리의 확산을 방지하는 정도 즉, 구리의 활성에너지(activation energy)가 약 0.6정도이고, SiCN막을 확산 방지막으로 사용할 경우 구리의 활성에너지는 0.8이상이다.In other words, when the conventional SiC film is used as the diffusion barrier, copper diffusion is prevented, that is, the activation energy of copper is about 0.6, and when the SiCN film is used as the diffusion barrier, the copper active energy is 0.8 or more. to be.
본 발명에 의하면, SiC막에 질소이온을 도핑한 SiCN막을 확산방지막으로 사용함으로써, 구리물질로 매립된 비아와 확산방지막간의 접착력을 증대시켜 소자의 특성열화를 방지하게 된다.According to the present invention, by using the SiCN film doped with nitrogen ions in the SiC film as a diffusion barrier, the adhesion between the via buried with the copper material and the diffusion barrier is increased to prevent deterioration of device characteristics.
이상에서 살펴본 바와 같이 본 발명에 의하면, SiC막에 질소이온을 도핑한 SiCN막을 확산방지막으로 사용함으로써, 구리물질로 매립된 비아와 확산방지막간의 접착력을 증대시켜 소자의 특성열화를 방지하게 되는 효과가 있다.As described above, according to the present invention, by using a SiCN film doped with nitrogen ions in the SiC film as a diffusion barrier, it is possible to increase the adhesion between vias buried with copper material and the diffusion barrier to prevent deterioration of device characteristics. have.
본 발명은 구체적인 실시 예에 대해서만 상세히 설명하였지만 본 발명의 기술적 사상의 범위 내에서 변형이나 변경할 수 있음은 본 발명이 속하는 분야의 당업자에게는 명백한 것이며, 그러한 변형이나 변경은 본 발명의 특허청구범위에 속한다 할 것이다.Although the present invention has been described in detail only with respect to specific embodiments, it is apparent to those skilled in the art that modifications or changes can be made within the scope of the technical idea of the present invention, and such modifications or changes belong to the claims of the present invention. something to do.
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| KR1020030049467A KR100541153B1 (en) | 2003-07-18 | 2003-07-18 | Method of forming metal line in semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100771370B1 (en) * | 2005-12-29 | 2007-10-30 | 동부일렉트로닉스 주식회사 | Metal line in semiconductor device and fabricating method thereof |
| KR100910443B1 (en) * | 2007-10-08 | 2009-08-04 | 주식회사 동부하이텍 | Method for forming copper line |
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2003
- 2003-07-18 KR KR1020030049467A patent/KR100541153B1/en active IP Right Grant
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100771370B1 (en) * | 2005-12-29 | 2007-10-30 | 동부일렉트로닉스 주식회사 | Metal line in semiconductor device and fabricating method thereof |
| KR100910443B1 (en) * | 2007-10-08 | 2009-08-04 | 주식회사 동부하이텍 | Method for forming copper line |
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