KR20000004227A - Method for forming a storage electrode of semiconductor devices - Google Patents
Method for forming a storage electrode of semiconductor devices Download PDFInfo
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- KR20000004227A KR20000004227A KR1019980025657A KR19980025657A KR20000004227A KR 20000004227 A KR20000004227 A KR 20000004227A KR 1019980025657 A KR1019980025657 A KR 1019980025657A KR 19980025657 A KR19980025657 A KR 19980025657A KR 20000004227 A KR20000004227 A KR 20000004227A
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- forming
- tungsten silicide
- polysilicon layer
- silicide layer
- storage electrode
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- 238000003860 storage Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 54
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 32
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000000460 chlorine Substances 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000012298 atmosphere Substances 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 150000003376 silicon Chemical class 0.000 claims description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 2
- 229910052801 chlorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000003795 chemical substances by application Substances 0.000 claims 1
- 239000012299 nitrogen atmosphere Substances 0.000 claims 1
- 238000004151 rapid thermal annealing Methods 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 전하저장 전극의 표면을 요철 형태로 형성하여 저장용량을 증대시킬 수 있는 전하저장 전극 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a charge storage electrode capable of increasing the storage capacity by forming the surface of the charge storage electrode in an uneven form.
일반적으로 반도체 소자가 고집적화 되어감에 따라 캐패시터가 차지하는 면적은 점차 줄어들고 있는 실정이다. 그럼에도 불구하고 소자를 구동시키기 위해서는 최소한의 정전용량을 필요로 하고 있다. 이에 따라 일정량의 이상의 정전용량 확보 측면에서 캐패시터의 전하저장 전극을 3 차원 구조로 형성하여 유효 표면적을 증대시키고 있다. 이와 같은 3 차원 구조의 전하저장 전극은 실린더 구조, 핀 구조 및 스택 구조 등이 있다. 일예로, 실린더(cylinder)형 전하저장 전극의 경우에는 이러한 문제점을 해결하기 위하여 실린더의 높이를 증가시키는 방법이 있으나, 이는 소자의 셀과 주변회로 간의 단차 증가를 유발시켜 후속 공정인 금속배선 공정에 어려움이 있으므로 높이를 증가시키는데 한계가 있다.In general, as semiconductor devices are highly integrated, the area occupied by capacitors is gradually decreasing. Nevertheless, minimal capacitance is required to drive the device. Accordingly, in order to secure a certain amount of abnormal capacitance, the charge storage electrode of the capacitor is formed in a three-dimensional structure to increase the effective surface area. Such three-dimensional charge storage electrodes include a cylinder structure, a fin structure and a stack structure. For example, in the case of a cylinder type charge storage electrode, there is a method of increasing the height of the cylinder to solve this problem, but this causes an increase in the level difference between the cell of the device and the peripheral circuit, which is a subsequent process for the metal wiring process Because of difficulty, there is a limit to increasing the height.
상기한 바와 같이, 유효 표면적을 증대시키기 위해 여러 가지 형상의 변형된 전하저장 전극이 연구되어 왔으나, 이에 한계가 있으며 보다 근본적인 해결방안이 요구 되었다.As described above, various shapes of modified charge storage electrodes have been studied to increase the effective surface area, but there are limitations and more fundamental solutions are required.
따라서, 본 발명은 전하저장 전극의 표면을 요철 형태로 형성하여 저장능력을 증대할 수 있고, 또한 종래 모든 타입의 전하저장 전극에 적용할 수 있는 전하저장 전극 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a charge storage electrode that can increase the storage capacity by forming the surface of the charge storage electrode in an uneven form, and can be applied to all types of charge storage electrodes.
상술한 목적을 달성하기 위한 본 발명은 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판상에 층간 절연막 형성 및 패터닝으로 콘택홀을 형성하는 단계와; 상기 전체 구조상에 폴리실리콘층 및 텅스텐 실리사이드층을 순차적으로 형성한 후, 급속 열처리를 실시하여 상기 텅스텐 실리사이드층에 실리콘 클러스터를 형성하는 단계와; 상기 텅스텐 실리사이드층에 비해 상기 실리콘 클러스터 및 상기 폴리실리콘층의 식각이 빠른 식각제를 이용한 플라즈마 건식 식각 공정을 상기 텅스텐 실리사이드층이 완전히 제거되는 시점까지 진행하고, 이로 인하여 상기 폴리실리콘층의 표면에 요철이 형성되는 단계와; 요철 표면을 갖는 상기 폴리실리콘층을 패터닝하여 전하저장 전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object comprises the steps of forming a contact hole by forming and patterning an interlayer insulating film on a substrate formed with a number of elements for forming a semiconductor device; Sequentially forming a polysilicon layer and a tungsten silicide layer on the entire structure, and then performing rapid heat treatment to form silicon clusters on the tungsten silicide layer; The plasma dry etching process using an etchant having a faster etching of the silicon cluster and the polysilicon layer than the tungsten silicide layer is performed until the tungsten silicide layer is completely removed, thereby causing irregularities on the surface of the polysilicon layer. Is formed; And patterning the polysilicon layer having an uneven surface to form a charge storage electrode.
도 1(a) 및 도 1(b)는 본 발명에 따른 반도체 소자의 전하저장 전극 형성 방법을 순차적으로 도시한 단면도.1 (a) and 1 (b) are cross-sectional views sequentially illustrating a method of forming a charge storage electrode of a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
11 : 반도체 기판 12 : 층간 절연막11 semiconductor substrate 12 interlayer insulating film
13 : 콘택홀 14 : 폴리실리콘층13 contact hole 14 polysilicon layer
15 : 텅스텐 실리사이드층 16 : 실리콘 클러스터15 tungsten silicide layer 16 silicon cluster
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 및 도 1(b)는 본 발명에 따른 반도체 소자의 전하저장 전극 형성 방법을 순차적으로 도시한 단면도이다.1 (a) and 1 (b) are cross-sectional views sequentially illustrating a method of forming a charge storage electrode of a semiconductor device according to the present invention.
도 1(a)를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(11)상에 층간 절연막(12)을 형성한 후, 상기 층간 절연막(12)의 선택된 부분에 콘택 마스크층(Contact Mask Layer)을 이용한 패터닝으로 콘택홀(Contact Hole; 13)을 형성한다. 콘택홀(13)이 형성된 전체 구조상에 폴리실리콘(14) 및 텅스텐 실리사이드(Tungsten Silicide; 15)를 순차적으로 증착한다. 급속 열처리(Rapid Thermal Process)를 실시하여 텅스텐 실리사이드층(15)에 실리콘 클러스터(Silicon Cluster; 16)를 형성한다.Referring to FIG. 1A, an interlayer insulating film 12 is formed on a semiconductor substrate 11 on which various elements for forming a semiconductor device are formed, and then a contact mask layer is formed on a selected portion of the interlayer insulating film 12. A contact hole 13 is formed by patterning using a contact mask layer. Polysilicon 14 and tungsten silicide 15 are sequentially deposited on the entire structure in which the contact hole 13 is formed. A rapid thermal process is performed to form a silicon cluster 16 on the tungsten silicide layer 15.
상기에서, 폴리실리콘층(14)은 1000 내지 1500Å 정도 형성되고, 텅스텐 실리사이드층(15)은 저압 화학 기상 증착법(LPCVD)에 의해 1000 내지 2500Å 정도로 형성된다. 실리콘 클러스터(16)는 텅스텐 실리사이드층(15)을 800 내지 1050℃ 정도의 질소(N2) 분위기에서 30 내지 60초간 급속 열처리하므로서 형성되는데, 이것은 텅스텐 실리사이드층(15)의 조성이 불균일 하게 되기 때문이다. 즉, 급속 열처리를 가함에 따라 원자들의 이동이 충분히 이루어지지 않기 때문에 실리콘 클러스터(16)가 형성된다. 텅스텐 실리사이드층의 조성이 불균일 하게 되는 원인에 대해, ‘텅스텐 실리사이드 대 실리콘의 식각 특성, J.V.S.T, B15(5), p1752, 1997.’을 참조 하였다.In the above description, the polysilicon layer 14 is formed at about 1000 to 1500 kPa, and the tungsten silicide layer 15 is formed at about 1000 to 2500 kPa by low pressure chemical vapor deposition (LPCVD). The silicon cluster 16 is formed by rapidly heat-treating the tungsten silicide layer 15 in a nitrogen (N 2 ) atmosphere at about 800 to 1050 ° C. for 30 to 60 seconds, because the composition of the tungsten silicide layer 15 becomes nonuniform. to be. That is, the silicon cluster 16 is formed because the rapid movement of the atoms does not sufficiently move the atoms. For the cause of the non-uniformity of the tungsten silicide layer, see Tungsten Silicide to Silicon Etch Characteristics, JVST, B15 (5), p1752, 1997.
도 1(b)를 참조하면, 실리콘 클러스터(16) 및 폴리실리콘층(14) 대(對) 텅스텐 실리사이드층(15)의 식각율이 2 : 1 인 식각제를 사용한 플라즈마 건식 식각(Plasma Dry Etch) 공정을 통해, 상기 텅스텐 실리사이드층(15)에 형성된 실리콘 클러스터(16)를 식각하여 텅스텐 실리사이드층(15)의 표면에 요철을 형성한 후, 요철이 형성된 상기 텅스텐 실리사이드층(15)을 마스크로 사용하여 폴리실리콘층(14)을 식각하므로서, 폴리실리콘층(14)의 표면에 요철을 형성한다. 이때, 상기 플라즈마 건식 식각은 텅스텐 실리사이드층(15)이 완전히 제거되는 시점까지 실시된다. 이후, 요철 표면을 갖는 폴리실리콘층(14)을 패터닝하여 접촉 면적이 증대된 전하저장 전극(14)을 형성한다.Referring to FIG. 1B, a plasma dry etch using an etchant having an etching rate of 2: 1 between the silicon cluster 16 and the polysilicon layer 14 versus the tungsten silicide layer 15 is shown. By etching the silicon clusters 16 formed on the tungsten silicide layer 15 to form irregularities on the surface of the tungsten silicide layer 15, and then using the tungsten silicide layer 15 having the irregularities as a mask. By using this to etch the polysilicon layer 14, irregularities are formed on the surface of the polysilicon layer 14. In this case, the plasma dry etching is performed until the tungsten silicide layer 15 is completely removed. Thereafter, the polysilicon layer 14 having the uneven surface is patterned to form the charge storage electrode 14 having an increased contact area.
상기에서, 플라즈마 건식 식각 공정은 염소(chlorine) 또는 불소(flourine)계 가스를 사용하며, 15 내지 120 Cl2, 5 내지 20 SF6, 5 내지 10 O2가스 분위기에서 3 내지 15mT의 압력, 100 내지 380W의 전력하에서 실시된다. 이때, 실리콘 클러스터(16) 및 폴리실리콘층(14)은 텅스텐 실리사이드층(15)에 비해 식각이 약 2 배 가량 빠르므로, 텅스텐 실리사이드층(15) 내의 실리콘 클러스터(14) 부분의 식각이 빠르게 일어난다. 이에 따라, 폴리실리콘층(14)이 실리콘 클러스터(14) 하부에서 먼저 노출된다. 또한, 노출된 하부 폴리실리콘층(14)도 텅스텐 실리사이드층(15) 보다 식각이 빠르므로 토폴러지(topology)를 더욱 굴곡지게 한다. 즉, 실리콘 클러스터(16)로 인하여 생긴 머폴로지(morphology)가 폴리실리콘층(14)이 노출되면서 더욱 심화된다. 상기와 같은, 식각의 차이에 대해서는 ‘텅스텐 실리사이드 대 실리콘의 식각 특성, J.V.S.T, B15(5), p1752, 1997.’에 언급되어 있다.In the above, the plasma dry etching process uses a chlorine or fluorine-based gas, a pressure of 3 to 15 mT in a atmosphere of 15 to 120 Cl 2 , 5 to 20 SF 6 , 5 to 10 O 2 gas, 100 To 380W. At this time, since the etching of the silicon cluster 16 and the polysilicon layer 14 is about twice as fast as that of the tungsten silicide layer 15, the etching of the silicon cluster 14 part in the tungsten silicide layer 15 occurs quickly. . Accordingly, the polysilicon layer 14 is first exposed under the silicon cluster 14. In addition, the exposed lower polysilicon layer 14 also etches faster than the tungsten silicide layer 15, thereby making the topology more curved. That is, the morphology (morphology) caused by the silicon cluster 16 is further intensified as the polysilicon layer 14 is exposed. As described above, the difference in etching is mentioned in the etching properties of tungsten silicides versus silicon, JVST, B15 (5), p1752, 1997.
상술한 바와 같이, 본 발명은 텅스텐 실리사이드층에 급속 열처리로 실리콘 클러스터를 형성하고, 상기 실리콘 클러스터 및 폴리실리콘층과 텅스텐 실리사이드층과의 식각 차이를 이용하여 표면이 요철 형태인 전하저장 전극을 형성하므로서, 종래 전하저장 전극의 형상 변화없이 기억용량을 증대시키고, 또한 소자의 집적도 증가에 따른 생산성을 향상시키는데 탁월한 효과가 있다.As described above, the present invention forms a silicon cluster on the tungsten silicide layer by rapid heat treatment, and forms a charge storage electrode having an uneven surface by using an etching difference between the silicon cluster and the polysilicon layer and the tungsten silicide layer. In addition, there is an excellent effect to increase the storage capacity without changing the shape of the conventional charge storage electrode and to improve the productivity by increasing the integration degree of the device.
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