KR100388476B1

KR100388476B1 - A method for forming storage node in semiconductor device

Info

Publication number: KR100388476B1
Application number: KR1019950005246A
Authority: KR
Inventors: 황준
Original assignee: 주식회사 하이닉스반도체
Priority date: 1995-03-14
Filing date: 1995-03-14
Publication date: 2004-02-25
Also published as: KR960035980A

Abstract

PURPOSE: A method for forming a storage node electrode of a semiconductor device is provided to be capable of improving capacitance and integration degree. CONSTITUTION: A conductive layer(3) as a storage node electrode is formed on a lower layer(1) with an interlayer dielectric(2). A metal film is formed on the conductive layer. The particle size of the metal film is enlarged by annealing. Concave and convex are formed on the surface of the metal film by selectively etching the grain boundary of the metal film. Then, the conductive layer is selectively etched by using the metal film with concave and convex as a mask.

Description

A method for forming storage node in semiconductor device

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 전하저장전극 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for forming a charge storage electrode of a semiconductor device.

일반적으로, 캐패시터의 정전용량(capacitance)은 캐패시터 유전막의 두께에 반비례하고, 전하저장전극의 표면적 및 캐패시터 유전막의 유전률에 비례하고 있다.In general, the capacitance of the capacitor is inversely proportional to the thickness of the capacitor dielectric film, and is proportional to the surface area of the charge storage electrode and the dielectric constant of the capacitor dielectric film.

특히, DRAM(Dynamic Random Access Memory) 소자를 제조하기 위해서는 작은크기에 비해 상대적으로 큰 정전용량을 가지는 캐패시터가 필수적으로 요구되고 있다.In particular, in order to manufacture a DRAM (Dynamic Random Access Memory) device, a capacitor having a relatively large capacitance compared to a small size is required.

이와 같은 과제를 해결하고자 현재 사용되고 있는 단순 스택구조와 같은 2차원 구조를 가진 캐패시터의 전하저장전극 구조에서, 캐패시터 유전막의 두께를 감소시킴으로써 캐패시터의 정전용량을 증가시키는 방법이 대두되고 있으나, 이는 누설전류 증가 등의 문제점이 발생하고 있다.In order to solve such a problem, in the charge storage electrode structure of a capacitor having a two-dimensional structure such as a simple stack structure currently used, a method of increasing the capacitance of a capacitor by reducing the thickness of the capacitor dielectric film is emerging. Problems such as increase are occurring.

본 발명은 동일한 디자인 룰(Design rule)에서도 큰 정전용량을 가지고, 이에 따라 소자의 집적도를 향상시킬 수 있는 반도체 소자의 전하저장전극 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a charge storage electrode of a semiconductor device, which has a large capacitance even in the same design rule, thereby improving the degree of integration of the device.

제 1A 도 내지 제 1D 도는 본 발명의 일실시예에 따른 반도체 소자의 전하저장전극 형성 공정을 도시한 도면.1A to 1D illustrate a process of forming a charge storage electrode of a semiconductor device according to an embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 간단한 설명** Brief description of symbols for the main parts of the drawings *

1 : 하부층 2 : 층간절연막1: lower layer 2: interlayer insulating film

3 : 제1폴리실리콘막 6 : 유전막3: first polysilicon film 6: dielectric film

7 : 제2폴리실리콘막7: second polysilicon film

상기 목적을 달성하기 위한 본 발명은, 소정의 하부공정이 완료된 하부층 상부에 전하저장전극용 전도막을 형성하는 제1 단계; 상기 전하저장전극용 전도막 상부에 금속막을 형성하는 제2 단계; 상기 금속막의 입자크기를 크게 형성하기 위한 열처리를 실시하는 제3 단계; 상기 제3 단계를 마친 상기 금속막의 일부를 식각하되, 상기 금속막의 입자간 경계부위를 식각하여 상기 금속막 표면에 요철을 형성하는 제4 단계; 상기 제4 단계를 마친 상기 금속막을 식각 마스크로 하여 상기 전하저장전극용 전도막의 일부 두께를 식각하는 제5 단계; 및 상기 금속막을 제거하는 제6 단계를 포함하여 이루어진다.The present invention for achieving the above object, the first step of forming a conductive film for the charge storage electrode on the lower layer of the predetermined lower process is completed; Forming a metal film on the conductive film for the charge storage electrode; A third step of performing a heat treatment to form a large particle size of the metal film; Etching a portion of the metal film after the third step, and forming irregularities on the surface of the metal film by etching the boundary portions between the particles of the metal film; A fifth step of etching a part thickness of the conductive film for the charge storage electrode by using the metal film having finished the fourth step as an etching mask; And a sixth step of removing the metal film.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

제 1A 도 내지 제 1D 도는 본 발명의 일실시예에 따른 반도체 소자의 전하저장전극 형성 공정을 도시한 공정도이다.1A to 1D are process diagrams illustrating a process of forming a charge storage electrode of a semiconductor device according to an exemplary embodiment of the present invention.

본 발명은 먼저, 제 1A 도에 도시된 바와 같이 활성영역(소스 또는 드레인과 같은 영역으로서, 도면에는 도시되지 않음) 및 전하저장전극 형성을 위한 콘택홀(Contact hole, 도면에는 도시되지 않음)과 같은 소정의 하부공정이 완료된 하부층(1) 상부에 소자간의 절연을 위한 층간절연막(2)을 형성한 후 층간절연막(2) 상부에 전하저장전극용 전도막인 제1폴리실리콘막(3)을 형성한다. 이때, 제1폴리실리콘막(3)은 활성영역 및 콘택홀을 통하여 콘택되도록 형성한다.First, the present invention relates to an active region (region such as a source or a drain, not shown in the drawing) and a contact hole (not shown in the drawing) for forming a charge storage electrode, as shown in FIG. After forming the interlayer insulating film 2 to insulate the devices on the lower layer 1 where the predetermined lower step is completed, the first polysilicon film 3 serving as the conductive film for the charge storage electrode is formed on the interlayer insulating film 2. Form. In this case, the first polysilicon film 3 is formed to be contacted through the active region and the contact hole.

이어서, 제1폴리실리콘막(3)이 전기적인 전도성을 갖도록 하기 위한 불순물 이온주입을 실시한다. 계속하여, 제1폴리실리콘막(3) 상부에 450 ~ 550Å 정도의 두께를 가지는 금속막(4)을 형성한다. 이때, 금속막(4)은 알루미늄막을 사용하여 스퍼터링(Sputtering)법으로 형성한다.Subsequently, impurity ion implantation is performed to make the first polysilicon film 3 have electrical conductivity. Subsequently, a metal film 4 having a thickness of about 450 to 550 kPa is formed on the first polysilicon film 3. At this time, the metal film 4 is formed by the sputtering method using an aluminum film.

다음으로, 제 1B 도에 도시된 바와 같이 금속막(4)의 입자(Grain) 크기를 크게 하기 위하여 핫 플레이트 오븐(Hot plate oven) 방식으로 300 ~ 400℃의 온도에서 1 ~ 5분 정도 열처리를 수행한 후 입자 경계(Grain boundary) 부위의 금속막(4)을 제거하기 위해 식각타겟을 300 ~ 400Å 정도로 설정하여 금속막(4)을 전면식각한다. 이때, 입자 경계 부위의 금속막(4)이 다른 부위의 금속막(4) 보다 상대적으로 빠른 속도로 식각되기 때문에 금속막(4) 입자 경계 부위의 제1폴리실리콘막(3)이 일부 노출된다.Next, as shown in FIG. 1B, in order to increase the grain size of the metal film 4, heat treatment is performed for about 1 to 5 minutes at a temperature of 300 to 400 ° C. using a hot plate oven method. After performing the etching process, the etching target is set to about 300 to 400Å to remove the metal film 4 at the grain boundary, and the metal film 4 is etched entirely. At this time, since the metal film 4 at the grain boundary portion is etched at a relatively higher speed than the metal film 4 at the other portion, the first polysilicon film 3 at the grain boundary portion of the metal film 4 is partially exposed. .

계속해서, 제 1C 도에 도시된 바와 같이 잔류되어 있는 금속막(입자 경계 부위를 제외한 금속막)(4)을 식각 마스크로 한 선택식각을 수행하여 노출된 제1폴리실리콘막(3)을 300 ~ 500Å 정도의 두께만큼 제거한 후 잔류하는 금속막(4)을 완전히 제거함으로써, 제1폴리실리콘막(3) 표면에 요철(凹凸)이 형성되도록 한다. 이어서, 전하저장 전극 영역이 정의된 감광막 패턴(5)을 형성한다.Subsequently, as shown in FIG. 1C, selective etching is performed using the remaining metal film (the metal film excluding the grain boundary portion) 4 as an etching mask to thereby expose the exposed first polysilicon film 3 to 300. By removing the metal film 4 remaining after the thickness is removed by a thickness of about 500 kPa, the unevenness is formed on the surface of the first polysilicon film 3. Subsequently, a photoresist pattern 5 having defined charge storage electrode regions is formed.

다음으로, 제 1D 도에 도시된 바와 같이 감광막 패턴(5)을 식각 마스크로 하여 제1폴리실리콘막(3)을 선택 식각하여 캐패시터의 전하저장전극 형성공정을 완료한다. 계속하여, 전체 구조 표면을 따라 ONO(Oxide-Nitride-Oxide)막과 같은 유전막(6)을 형성한 후 전체구조 상부에 플레이트 전극인 제2폴리실리콘막(7)을 형성한다.Next, as illustrated in FIG. 1D, the first polysilicon film 3 is selectively etched using the photoresist pattern 5 as an etching mask to complete the process of forming the charge storage electrode of the capacitor. Subsequently, after forming a dielectric film 6 such as an oxide-nitride-oxide (ONO) film along the entire structure surface, a second polysilicon film 7 which is a plate electrode is formed on the entire structure.

이렇듯, 본 발명은 전하저장전극의 표면에 요철을 형성시켜 전하저장전극의 표면적을 향상시킴으로써, 동일한 디자인 룰에서도 큰 정전용량을 가지는 캐패시터를 제조할 수 있게 한다.As such, the present invention improves the surface area of the charge storage electrode by forming irregularities on the surface of the charge storage electrode, thereby making it possible to manufacture a capacitor having a large capacitance even under the same design rule.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명은 동일한 디자인 룰에서도 큰 정전용량을 가지는 효과가 있으며, 이에 따라 집적도를 향상시킬 수 있는 효과가 있다.The present invention has the effect of having a large capacitance even in the same design rule, and thus has the effect of improving the degree of integration.

Claims

A first step of forming a conductive film for an electron storage electrode on the lower layer in which a predetermined lower process is completed;

Forming a metal film on the conductive film for the charge storage electrode;

A third step of performing a heat treatment to form a large particle size of the metal film;

Etching a portion of the metal film after the third step, and forming irregularities on the surface of the metal film by etching the boundary portions between the particles of the metal film;

A fifth step of etching a part thickness of the conductive film for the charge storage electrode by using the metal film having finished the fourth step as an etching mask; And

Sixth step of removing the metal film

Method for forming a charge storage electrode of a semiconductor device comprising a.

The method of claim 1,

The metal film,

A method for forming a charge storage electrode of a semiconductor device, characterized in that formed by a sputtering method to a thickness of 450 ~ 550Å.

The method of claim 1,

The metal film,

A charge storage electrode forming method for a semiconductor device, characterized in that the aluminum film.

The method of claim 1,

The third step,

Method for forming a charge storage electrode of a semiconductor device, characterized in that performed for 1 to 5 minutes at a temperature of 300 ~ 400 ℃.

The method according to claim 1 or 4,

The third step,

Method for forming a charge storage electrode of a semiconductor device, characterized in that carried out by a hot plate oven (Hot Plate Oven) method.

The method of claim 1,

The fourth step,

And etching to expose a portion of the conductive film for the charge storage electrode.

The method of claim 1,

The fifth step,

And a portion of the upper portion of the conductive film for the charge storage electrode is etched at about 300 to 500 kV.

The method of claim 1,

The fourth step,

A charge storage electrode forming method of a semiconductor device, characterized in that performed by the front dry etching method.