KR20000001539A - Method for manufacturing semiconductor devices - Google Patents
Method for manufacturing semiconductor devices Download PDFInfo
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- KR20000001539A KR20000001539A KR1019980021862A KR19980021862A KR20000001539A KR 20000001539 A KR20000001539 A KR 20000001539A KR 1019980021862 A KR1019980021862 A KR 1019980021862A KR 19980021862 A KR19980021862 A KR 19980021862A KR 20000001539 A KR20000001539 A KR 20000001539A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Abstract
Description
본 발명은 반도체장치의 제조 방법에 관한 것으로서, 특히, 할로(Halo) 구조를 갖는 CMOS 트랜지스터의 제조 공정을 단순화시킬 수 있는 반도체장치의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of simplifying a manufacturing process of a CMOS transistor having a halo structure.
반도체장치가 고집적화 됨에 따라 각각의 셀은 미세해져서 내부의 전계 강도가 증가하게된다. 이러한 전계 강도의 증가는 소자 동작시 드레인 부근의 공핍층에서 채널영역의 캐리어를 가속시켜 게이트산화막으로 주입시키는 핫 캐리어 효과(hot carrier effect)를 일으킨다. 이렇게 게이트산화막에 주입된 캐리어는 반도체기판과 게이트산화막의 계면에 준위를 생성시켜 드레쉬홀드 전압(threshold voltage)을 변화시키거나 상호 컨덕턴스를 저하시켜 소자 특성을 저하시킨다. 그러므로, 핫 캐리어 효과에 의한 소자 특성의 저하를 감소시키기 위해 트랜지스터에 저도핑드레인(Lightly Doped Drain : 이하, LDD라 칭함) 등과 같이 드레인 구조를 변화시킨 구조를 사용한다.As semiconductor devices become more integrated, each cell becomes finer, and the internal electric field strength increases. This increase in electric field strength causes a hot carrier effect in which the carrier of the channel region is accelerated and injected into the gate oxide layer in the depletion layer near the drain during operation of the device. The carrier injected into the gate oxide film generates a level at the interface between the semiconductor substrate and the gate oxide film, thereby changing the threshold voltage or decreasing mutual conductance, thereby degrading device characteristics. Therefore, in order to reduce the deterioration of device characteristics due to the hot carrier effect, a structure in which the drain structure is changed in the transistor, such as a lightly doped drain (hereinafter referred to as LDD), is used.
그리고, 채널의 길이가 짧아짐에 따른 펀치 쓰루(punch through) 현상을 방지하기 위해 게이트를 형성한 후 LDD를 형성하기 전에 기판의 활성영역의 농도를 높이기 위하여 소오스/드레인 형성용 불순물이온과 반대 도전형의 불순물을 이온주입하는 할로LDD(halo LDD) 구조를 형성한다.In order to increase the concentration of the active region of the substrate before forming the LDD after forming the gate to prevent the punch through phenomenon due to the shortening of the channel, the conductivity type opposite to the source / drain formation impurity ion A halo LDD (halo LDD) structure is formed to ion-implant impurities.
도 1a 내지 도 1e는 종래 기술에 따른 반도체장치의 제조 방법을 도시하는 공정도이다.1A to 1E are process drawings showing a method of manufacturing a semiconductor device according to the prior art.
종래에는 도 1a에 나타낸 바와 같이 반도체기판(11)의 소정 부분에 LOCOS(Local Oxidation of Silicon) 방법과 같은 통상적인 소자 격리 방법으로 필드산화막(12)을 형성하여 반도체기판(11)의 활성영역을 한정하고 상기 반도체기판(11)에 각각의 마스크를 사용하여 상기 각각의 활성영역에 p웰(13) 및 n웰(14)을 형성한다. 상기의 p웰(13) 및 n웰(14)에 각각 n형 및 p형의 불순물을 이온주입하여 상기 각각 웰의 표면에 제 1 및 제 2 채널영역(15)(16)을 형성한다.In the related art, as shown in FIG. 1A, the field oxide film 12 is formed on a predetermined portion of the semiconductor substrate 11 by a conventional device isolation method such as a local oxide of silicon (LOCOS) method to form an active region of the semiconductor substrate 11. The p wells 13 and the n wells 14 are formed in the respective active regions by using respective masks on the semiconductor substrate 11. N-type and p-type impurities are ion-implanted into the p wells 13 and n wells 14, respectively, to form first and second channel regions 15 and 16 on the surfaces of the wells, respectively.
그리고, 도 1b에 나타낸 바와 같이 상기 반도체기판(11) 상에 열산화의 방법으로 게이트산화막(17)을 형성하고 상기 게이트산화막(17) 상에 화학적 기상 증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 불순물이 도핑된 다결정실리콘을 증착하여 다결정실리콘층을 형성한 후, 상기 다결정실리콘층 및 게이트산화막(17)을 패터닝하여 상기 n웰(13) 및 p웰(14) 상의 소정 부분에 게이트산화막(17)을 개제시킨 게이트(18)를 형성한다. 그런 다음에 상기 반도체기판(11) 상에 상기 게이트(18)를 덮도록 포토레지스트를 도포하고 노광 및 현상하여 상기 p웰(13) 상에만 잔류하는 제 1 마스크층(19)을 형성하고, 상기 제 1 마스크층(19) 및 상기 n웰(14) 상에 형성된 게이트(18)를 마스크로 사용하여 상기 n웰(14)에 상기 n웰(14)과 도전형이 같은 인(P)을 경사 이온주입(Tilt Ion Implantation)하여 제 1 할로영역(20)을 형성하며, 상기 제 1 마스크층(19) 및 게이트(18)를 마스크로 사용하여 상기 제 1 할로영역(20)이 형성된 n웰(14)에 상기 n웰(14)과 도전형이 다른 붕소(B)를 저농도로 이온주입하여 LDD구조를 형성하기 위한 저농도 p형 불순물영역(21)을 형성한다.1B, a gate oxide film 17 is formed on the semiconductor substrate 11 by thermal oxidation, and chemical vapor deposition (hereinafter, referred to as CVD) is performed on the gate oxide film 17. Polycrystalline silicon is deposited to form a polysilicon layer, and then the polysilicon layer and the gate oxide layer 17 are patterned to gate at predetermined portions on the n well 13 and the p well 14. A gate 18 having the oxide film 17 interposed therebetween is formed. Then, a photoresist is applied on the semiconductor substrate 11 to cover the gate 18, and the photoresist is exposed and developed to form a first mask layer 19 remaining only on the p well 13. A phosphor 18 having the same conductivity type as the n well 14 is inclined to the n well 14 by using a first mask layer 19 and a gate 18 formed on the n well 14 as a mask. An n well in which the first hollow region 20 is formed by implanting the first hollow region 20 by using ion implantation and using the first mask layer 19 and the gate 18 as a mask. 14, a low concentration p-type impurity region 21 for forming an LDD structure is formed by ion implantation of boron (B) having a different conductivity type from that of the n well 14.
그런 다음, 도 1c에 나타낸 바와 같이 상기 제 1 마스크층(19)을 제거하고 상기 반도체기판(11)의 상기 n웰(14) 상에만 잔류하는 제 2 마스크층(22)을 형성한다. 상기 반도체기판(11)에 상기 제 2 마스크층(22) 및 상기 p웰(13) 상에 형성된 게이트(18)를 마스크로 사용하여 노출된 상기 p웰(13)에 상기 p웰(13)과 도전형이 같은 붕소(B)를 경사 이온주입하여 제 2 할로영역(23)을 형성하고 다시 상기 p웰(13)에 상기 p웰(13)과 도전형이 다른 아세닉(As)을 저농도로 이온주입하여 저농도 n형 불순물영역(24)을 형성한다.Then, as shown in FIG. 1C, the first mask layer 19 is removed and the second mask layer 22 remaining only on the n well 14 of the semiconductor substrate 11 is formed. The p well 13 may be exposed to the p well 13 exposed by using the second mask layer 22 and the gate 18 formed on the p well 13 as a mask. Boron (B) having the same conductivity type is inclined to form a second hollow region 23, and again, the p well 13 has a low concentration of acenic (As) having a different conductivity type from the p well 13. Ion implantation forms the low concentration n-type impurity region 24.
그리고, 도 1d에 나타낸 바와 같이 상기 잔류하는 제 2 마스크층(22)을 제거하고 상기 반도체기판(11) 상에 상기 게이트(18)를 덮도록 질화막 또는 산화막을 형성하고 에치백하여 상기 n웰(13) 및 p웰(14) 상의 게이트(18) 측면에 절연 측벽(25)을 형성한다. 그런 다음 상기 반도체기판(11)의 p웰(13) 상에만 잔류하는 제 3 마스크층(26)을 형성하고, 상기 제 3 마스크층(26) 및 상기 n웰(14)에 형성된 게이트(18) 및 측벽(25)을 마스크로 사용하여 노출된 상기 n웰(14)에 상기 n웰(14)과 도전형이 다른 붕소를 고농도로 이온주입하여 상기 n웰(14)에 소오스/드레인영역으로 사용되는 고농도 p형 불순물영역(27)을 형성한다.As shown in FIG. 1D, a nitride film or an oxide film is formed and etched back to remove the remaining second mask layer 22 and cover the gate 18 on the semiconductor substrate 11. 13 and an insulating side wall 25 on the side of the gate 18 on the p well 14. Then, a third mask layer 26 remaining only on the p well 13 of the semiconductor substrate 11 is formed, and the gate 18 formed in the third mask layer 26 and the n well 14 is formed. And boron having a different conductivity type from the n well 14 is exposed to the n well 14 exposed using the sidewall 25 as a mask to be used as a source / drain region in the n well 14. A high concentration p-type impurity region 27 is formed.
그런 후에, 도 1e와 같이 상기 잔류하는 제 3 마스크층(26)을 제거하고 상기 반도체기판(11)의 n웰(14) 상에만 잔류하는 제 4 마스크층(28)을 형성하고, 상기 노출된 p웰(13)에 상기 제 4 마스크층(28), 게이트 및 측벽(18)(25)을 마스크로 사용하여 상기 p웰(13)과 도전형이 다른 불순물을 고농도로 이온주입하여 상기 p웰(13)에 소오스/드레인영역으로 사용되는 n형 고농도불순물영역(29) 및 접합부의 전계를 완화시키는 완충영역(30)을 형성한다. 상기에서 아세닉과 인의 투영 비정(Projected Range)이 서로 다르기 때문에 아세닉의 주입영역과 인의 주입영역이 이중으로 형성되어 고농도 불순물영역(29) 및 완충영역(30)이 형성된다. 상기 완충영역(30)은 상기 고농도 불순물영역(29)을 형성하기 위해 아세닉을 고농도로 이온주입하므로 발생하는 pn 접합으로 인한 전계 강도를 감소시키는 완충역할을 한다.Thereafter, as shown in FIG. 1E, the remaining third mask layer 26 is removed and a fourth mask layer 28 remaining only on the n well 14 of the semiconductor substrate 11 is formed. By using the fourth mask layer 28, the gate and the sidewalls 18, 25 as a mask in the p well 13, impurities having different conductivity types from the p well 13 are ion-implanted at a high concentration. An n-type high concentration impurity region 29 used as a source / drain region and a buffer region 30 for relaxing the electric field of the junction portion are formed in (13). Since the projected range of the acenic and the phosphorus is different from each other, the implanted region of the acenic and the phosphorus implanted region are formed in a double manner to form a high concentration impurity region 29 and a buffer region 30. The buffer region 30 serves as a buffer to reduce electric field strength due to pn junctions generated by ion implantation at high concentration to form the high concentration impurity region 29.
상술한 바와 같이 종래에는 반도체기판에 각각의 p웰 및 n웰용 마스크, p웰의 할로영역과 저농도불순물영역 및 n웰의 할로영역과 저농도불순물영역, 그리고, p웰 및 n웰의 고농도불순물영역용 마스크를 각각의 공정마다 사용하여 할로 LDD구조를 갖는 nMOS 및 pMOS를 형성하였다.As described above, a mask for each p well and n well, a halo region and a low concentration impurity region of the p well, a halo region and a low concentration impurity region of the n well, and a high concentration impurity region of the p well and n well are conventionally described as described above. Masks were used for each process to form nMOS and pMOS with halo LDD structures.
그러나, 종래의 기술에 따른 방법은 각각의 마스크 공정을 수반하므로 공정이 복잡하고 nMOS의 아세닉에 의한 접합부의 전계 강도 증가를 방지하기 위해 인을 동시 이온주입하는 등의 번거로운 문제가 있다.However, since the method according to the related art involves each mask process, the process is complicated, and there are troublesome problems such as simultaneous ion implantation of phosphorus to prevent the increase of the electric field strength of the junction by the nMOS acenic.
따라서, 본 발명의 목적은 할로 구조를 갖는 CMOS를 형성하는 공정에 있어서 공정을 단순화 할 수 있는 반도체장치의 제조 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device which can simplify the process in the process of forming a CMOS having a halo structure.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 제조 방법은 반도체기판의 소정 부분에 필드산화막을 형성하여 활성영역을 한정하고 p웰 및 n웰을 형성하는 공정과, 상기 p웰의 상부 표면에 n 채널영역을 n웰에는 제 1 할로영역 및 상기 제 1 할로영역 상에 p 채널영역을 형성하는 공정과, 상기 p웰 및 n웰에 상기 게이트를 마스크로 사용하여 n형 불순물을 이온주입하여 p웰에 완충영역 및 n웰에 제 2 할로영역을 형성하는 공정과, 상기 p웰에 상기 게이트를 마스크로 사용하여 제 3 할로영역 및 n형의 저농도불순물영역을 형성하는 공정과, 상기 n웰 및 p웰 상에 형성된 게이트의 측면에 측벽을 형성하는 공정과, 상기 n웰에 게이트 및 측벽을 마스크로 사용하여 p형의 고농도불순물영역을 형성하는 공정과, 상기 p웰에 게이트 및 측벽을 마스크로 사용하여 n형의 고농도불순물영역을 형성하는 공정을 구비한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object is to form a field oxide film in a predetermined portion of the semiconductor substrate to define the active region and to form the p well and n well, and to the upper surface of the p well forming a p-channel region on the first halo region and the first halo region in the n-well and the n-type impurity by implanting n-type impurities using the gate as a mask in the p-well and the n-well. Forming a buffer region in the well and a second halo region in the n well, forming a third halo region and an n-type low concentration impurity region using the gate as a mask in the p well, the n well and forming a sidewall on a side of a gate formed on the p well, forming a p-type high concentration impurity region using the gate and the sidewall as a mask in the n well, and forming a gate and sidewall as a mask on the p well use It includes a step of forming a high-concentration impurity region of the n-W.
도 1a 내지 도 1e는 종래 기술에 따른 반도체장치의 제조 방법을 도시하는 공정도.1A to 1E are process drawings showing a method for manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2e은 본 발명의 실시 예에 따른 반도체장치의 제조 방법을 도시하는 공정도.2A to 2E are flowcharts illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 간단한 설명><Brief description of symbols for the main parts of the drawings>
31 : 반도체기판 33 : p웰31 semiconductor substrate 33 p-well
34 : n웰 37 : 제 1 할로영역34: n well 37: first halo region
40 : 완충영역 40-1 : 제 2 할로영역40: buffer region 40-1: second halo region
43 : 제 3 할로영역 44 : n형 저농도불순물영역43: third halo region 44: n-type low concentration impurity region
47 : p형 고농도 불순물영역 49 : n형 고농도불순물영역47: p-type high concentration impurity region 49: n-type high concentration impurity region
이하, 첨부된 도면을 참조하여 본 발명을 설명한다.Hereinafter, with reference to the accompanying drawings will be described the present invention.
도 2a 내지 도 2e는 본 발명의 실시 예에 따른 반도체장치의 제조 방법을 도시하는 공정도이다.2A through 2E are process diagrams illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
본 방법은 도 2a에 나타낸 바와 같이 반도체기판(31)의 소정 부분에 LOCOS 방법과 같은 통상적인 소자 격리 방법으로 필드산화막(32)을 형성하여 상기 반도체기판(31)의 활성영역을 한정하고 상기 반도체기판(31)에 각각의 마스크를 사용하여 상기 필드산화막(32)으로 한정된 각각의 활성영역에 p웰(33) 및 n웰(34)을 형성하고, 상기 p웰(33) 및 n웰(34)에 n형 및 p형의 불순물을 각각 이온주입하여 상기 p웰(33) 및 n웰(34)의 상부 표면에 제 1 및 제 2 채널영역(35)(36)을 형성한다. 이때, 상기 n웰(34)에 제 2 채널영역(36)을 형성하기 전에 상기 n웰(34)의 소정 깊이에 상기 n웰(34)과 같은 도전형의 아세닉(As)을 이온주입하여 제 1 할로영역(37)을 형성하고 상기 제 1 할로영역(37) 상부에 제 2 채널영역(36)을 형성한다.As shown in FIG. 2A, the field oxide film 32 is formed on a predetermined portion of the semiconductor substrate 31 by a conventional device isolation method such as the LOCOS method to define an active region of the semiconductor substrate 31, and P wells 33 and n wells 34 are formed in respective active regions defined by the field oxide layer 32 using respective masks on the substrate 31, and the p wells 33 and n wells 34 are formed. N-type and p-type impurities are ion-implanted, respectively, to form first and second channel regions 35 and 36 on the upper surfaces of the p well 33 and the n well 34. At this time, before forming the second channel region 36 in the n well 34, ion implantation of a conductive type Asnic as the n well 34 is performed at a predetermined depth of the n well 34. A first hollow region 37 is formed and a second channel region 36 is formed on the first hollow region 37.
그리고, 도 2b에 나타낸 바와 같이 상기 p웰(33) 및 n웰(34) 상의 소정 부분에 게이트산화막(38)을 개제시킨 게이트(39)를 형성하고 상기 p웰(33) 및 n웰(34)에 상기 게이트(39) 및 필드절연막(32)을 마스크로 사용하여 n형 불순물인 인(P)을 블랭킷(blanket) 이온주입하여 p웰(33)에는 접합부의 전계 집중을 완화시킬 수 있는 완충영역(40)을 n웰(34)에는 제 2 할로영역(40-1)을 형성한다.As shown in FIG. 2B, a gate 39 having a gate oxide film 38 interposed therebetween is formed in a predetermined portion on the p well 33 and the n well 34, and the p well 33 and the n well 34 are formed. (P) blanket ion implanted with phosphorus (P), an n-type impurity, by using the gate 39 and the field insulating film 32 as a mask in the p-well 33 to buffer the electric field concentration at the junction. A second hollow region 40-1 is formed in the n well 34 in the region 40.
다음에 도 2c와 같이 상기 반도체기판(31)의 상기 n웰(34) 상에만 잔류하는 제 1 마스크층(41)을 형성하고 상기 반도체기판(31)에 상기 제 1 마스크층(41) 및 p웰(33) 상의 게이트(39)를 마스크로 사용하여 상기 p웰(33)과 도전형이 같은 붕소(B)를 경사 이온주입하여 제 3 할로영역(43)을 형성한다. 이어서, 상기 노출된 p웰(33)에 상기 p웰(33)과 도전형이 다른 아세닉(As)을 저농도로 이온주입하여 LDD를 형성하기 위한 저농도 n형 불순물영역(44)을 형성한다.Next, as shown in FIG. 2C, a first mask layer 41 remaining only on the n well 34 of the semiconductor substrate 31 is formed, and the first mask layer 41 and p are formed on the semiconductor substrate 31. Using the gate 39 on the well 33 as a mask, boron B having the same conductivity type as the p-well 33 is inclined and implanted to form a third hollow region 43. Subsequently, a low concentration of n-type impurity region 44 for forming LDD is formed by ion implanting acenic (As) having a different conductivity type from that of the p well 33 into the exposed p well 33.
그리고, 도 2d에 나타낸 바와 같이 상기 제 1 마스크층(41)을 제거하고 상기 반도체기판(31) 상에 상기 게이트(39)를 덮도록 질화막 또는 산화막을 형성하고 에치백하여 상기 p웰(33) 및 n웰(34) 상에 형성된 게이트(39)의 측면에 절연 측벽(45)을 형성한다. 그런 다음 상기 반도체기판(31)의 p웰(33) 상에만 잔류하는 제 2 마스크층(46)을 형성하고, 상기 제 2 마스크층(46) 및 상기 n웰(34) 상에 형성된 게이트(39) 및 측벽(45)을 마스크로 사용하여 노출된 상기 n웰(34)에 상기 n웰(34)과 도전형이 다른 붕소(B)를 고농도로 이온주입하여 상기 n웰(34)의 소오스/드레인영역으로 사용되는 고농도 p형 불순물영역(47)을 형성한다.As shown in FIG. 2D, the p-well 33 is formed by removing the first mask layer 41 and forming a nitride film or an oxide film to cover the gate 39 on the semiconductor substrate 31. And an insulating sidewall 45 formed on the side of the gate 39 formed on the n well 34. Then, the second mask layer 46 remaining only on the p well 33 of the semiconductor substrate 31 is formed, and the gate 39 formed on the second mask layer 46 and the n well 34 is formed. And boron (B) having a different conductivity from the n well 34 are exposed to the n well 34 exposed using the sidewalls 45 as a mask. A high concentration p-type impurity region 47 used as the drain region is formed.
그런 후에, 도 2e와 같이 상기 제 2 마스크층(46)을 제거하고 상기 반도체기판(31)의 n웰(34) 상에만 잔류하는 제 3 마스크층(48)을 형성한 후, 상기 제 3 마스크층(48) 및 상기 p웰(33) 상에 형성된 게이트(39) 및 측벽(45)을 마스크로 사용하여 노출된 상기 p웰(33)에 상기 p웰(33)과 도전형이 다른 아세닉(As)을 고농도로 이온주입하여 p웰(33)의 소오스/드레인영역으로 사용되는 고농도 n형 불순물영역(49)을 형성한다. 상기에서 인의 블랭킷 이온주입으로 형성한 완충영역(40)이 상기 고농도 n형 불순물영역(49)의 접합 전계 강도를 완화시키게된다.Thereafter, as shown in FIG. 2E, the second mask layer 46 is removed, and after forming the third mask layer 48 remaining only on the n well 34 of the semiconductor substrate 31, the third mask is formed. An acenic different in conductivity from the p well 33 to the exposed p well 33 using the gate 48 and the sidewalls 45 formed on the layer 48 and the p well 33 as a mask. (As) is implanted at a high concentration to form a high concentration n-type impurity region 49 used as a source / drain region of the p well 33. In the buffer region 40 formed by the blanket ion implantation of phosphorus, the junction electric field strength of the high concentration n-type impurity region 49 is relaxed.
상술한 바와 같이 본 발명에서는 반도체기판에 n웰 및 p웰을 형성하고 상기 p웰에 제 1 채널영역 및 n웰에 제 1 할로영역과 제 2 채널영역을 형성한다. 그리고 별도의 마스크층을 형성하지 않고 n웰 및 p웰에 인을 블랭킷 이온주입하여 p웰에는 접합부의 전계 강도를 감소시키기 위한 완충영역을, n웰에는 제 2 할로영역을 형성하며, 이후에 세 차례의 마스크층을 형성하고 각각의 마스크층을 마스크로 사용하여 p웰의 제 3 할로영역과 저농도 불순물영역, n웰의 고농도 불순물영역 및 p웰의 고농도 불순물영역을 순차적으로 형성하여 할로 LDD구조를 갖는 nMOS 및 세미 할로 구조를 갖는 pMOS를 형성하였다.As described above, in the present invention, n wells and p wells are formed in a semiconductor substrate, and a first channel region and a first channel region and a second channel region are formed in the p well. In addition, a blanket ion is implanted into the n well and the p well without forming a separate mask layer to form a buffer region in the p well to reduce the electric field strength of the junction, and a second halo region in the n well. A mask layer is formed in turn, and each mask layer is used as a mask to sequentially form a third halo region and a low concentration impurity region of the p well, a high concentration impurity region of the n well, and a high concentration impurity region of the p well to form a halo LDD structure. NMOS having and a pMOS having a semi-halo structure were formed.
따라서, 본 발명에 따른 반도체장치의 제조 방법은 인을 p웰 및 n웰에 블랭킷 이온주입하여 n웰에는 제 2 할로영역을 p웰에는 완충영역을 형성하므로서 노광 및 현상 공정을 감소시킬 수 있고 nMOS에 아세닉과 인을 동시 이온주입하는 번거로움을 해소할 수 있는 이점이 있다.Accordingly, the method of manufacturing a semiconductor device according to the present invention can reduce the exposure and development processes by forming a second halo region in the n well and a buffer region in the p well by implanting phosphorus into the p well and the n well, thereby reducing the nMOS. There is an advantage that can eliminate the trouble of simultaneous ion implantation of phosphonic and phosphorus.
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