KR19990085865A - LOC type leadframe and LOC package using same - Google Patents

Abstract

The LOC type lead frame and the LOC package using the same are formed so that the tie bars as well as the inner leads of the lead frame are positioned on the upper surface of the semiconductor chip, and are bonded to the upper surface of the semiconductor chip by adhesive tape.

Accordingly, the present invention prevents the occurrence of defects such as tilt or shift in the molding process by adhering the semiconductor chip to the tie bar together with the inner leads to strengthen the adhesive force between the semiconductor chip and the lead frame, and furthermore, This prevents the occurrence of defects such as incomplete molding or bending.

Description

LOC type leadframe and LOC package using same

The present invention relates to a LOC package, and more particularly, to a LOC type lead frame, which is capable of preventing occurrence of defects due to movement of a semiconductor chip in a molding process by adhering not only an internal lead but also a tie bar to a semiconductor chip. It is about LOC package used.

As is widely known, in recent years, as the memory capacities of electronic devices and information devices are increased, semiconductor chip devices such as DRAM and SRAM are highly integrated, and chip sizes are gradually increasing. On the other hand, semiconductor chip packages incorporating semiconductor chips are becoming thin and light in accordance with the trend of lighter and smaller electronic devices and information devices.

The semiconductor chip package is roughly classified into a general type using a die pad of a lead frame and a LOC type that bonds a semiconductor chip and an internal lead using an adhesive tape without using a die pad.

In the case of the typical type package, the size of the semiconductor chip was up to 50% compared to the size of the semiconductor chip package, but the share of the semiconductor chip has increased as the share of the semiconductor chip increases by 70-80% due to the multifunction and high integration of the semiconductor chip. There is a limitation in that there is no space for internal lead in the rest of the area except the area. In addition, when the IR (infrared) reflow process proceeds, there was a disadvantage that the crack resistance is weak.

The LOC package can be equipped with a larger size semiconductor chip inside a limited size package, and the interface between the semiconductor chip and the encapsulating molded resin directly bonds with more reliability than a typical type package. That is, in the case of a typical type of package, due to the bubbles generated during the molding process, the incomplete molding phenomenon or the semiconductor chip in which an empty space is embedded in the encapsulant or a groove is formed on the surface of the encapsulation body is tilted by moving up and down. As the phenomenon or the semiconductor chip is shifted to the left and right, the shift phenomenon is frequent, but in the case of the LOC package, such defects are significantly improved. Therefore, LOC packages have been widely applied to high density packages at present.

However, since the size of the semiconductor chip is rapidly decreasing with the development of integrated circuit technology, the size of the semiconductor chip in the mass production stage is often reduced to less than half of the size of the semiconductor chip in the initial stage of development. Therefore, the device that can be packaged only when the LOC type leadframe is applied in the early stage of development is reduced to the size that can be packaged even with a typical type leadframe having a die pad in the mass production stage. To this end, since the location of the bonding pad of the semiconductor chip has to be redesigned, the LOC type lead frame in the early stage of development has been applied to the mass production stage.

In the conventional LOC package, as shown in FIG. 1, opposite inner leads 11 of the LOC type lead frame 10 are formed on both sides of the upper surface of the semiconductor chip 30 by an adhesive tape 20. Bonded to each other, the center pads 31 of the semiconductor chip 30 are electrically connected to each other by the bonding wire 40, and the inner side of the tie bar 13 of the lead frame 10 is spaced at a predetermined interval. It extends in a direction parallel to the corresponding short side side of 30, except for the outer leads 15 of the lead frame 10 is composed of a structure in which the enclosed within the outer boundary line of the encapsulant 50.

However, in the conventional LOC type package, the long side of the upper surface of the semiconductor chip 30 is bonded only to the inner leads 11 of the lead frame 10 by the adhesive tape 20, but the upper surface of the semiconductor chip 30 is used. The short side is not attached to the tie bar 13 at all. As a result, the adhesive force between the semiconductor chip 30 and the lead frame 10 is more likely to be weaker than the high pressure of the molding resin introduced during the molding process, and defects such as tilt or shift of the semiconductor chip 30 occur frequently. This, in turn, provided a direct cause for further exacerbation of defects such as incomplete molding or warping of LOC type packages.

Therefore, an object of the present invention is to increase the adhesion between the semiconductor chip and the lead frame to prevent the occurrence of defects due to the movement of the semiconductor chip in the molding process.

Another object of the present invention is to change the structure of the tie bar to provide an additional adhesion between the semiconductor chip and the tie bar.

Other objects of the present invention will become more apparent from the following detailed description and the accompanying drawings.

1 is an exemplary view showing the structure of an LOC package according to the prior art.

Figure 2 is a schematic diagram showing the structure of a LOC package to which the LOC type leadframe according to the present invention.

Figure 3 is a schematic diagram showing the structure of a LOC package to which a LOC type lead frame according to a modification of the present invention.

<Description of the symbols for the main parts of the drawings>

DESCRIPTION OF SYMBOLS 10 Lead frame 11: Internal lead 13: Tie bar 15: External lead 20: Adhesive tape 30: Semiconductor chip 31: Center pad 40: Bonding wire 50: Encapsulant 100,200: Lead frame 111: Internal lead 111a, 111b: Outermost Internal lead 213a, 213b: outermost internal lead

LOC type lead frame according to the present invention for achieving the above object

In the LOC type lead frame having inner leads having an inner portion located on the upper surface and a tie bar spaced apart from the semiconductor chip to adhere to the adhesive tape on the upper surface of the semiconductor chip,

The inner side of the tie bar is characterized in that it is located on the upper surface for adhesion with the adhesive tape on the upper surface.

The inner part of the tie bar is spaced apart from the inner end of the neighboring outermost inner lead among the inner leads. In addition, the tie bar is cut so that the inner portion of the tie bar is integrally connected to the inner portion of the neighboring outermost inner lead and not connected to the outermost inner leads.

In addition, LOC package using a LOC type lead frame according to the present invention for achieving the above object is

A semiconductor having center pads formed in a central portion of an upper surface thereof;

A lead frame having inner leads adhered to the long side of the upper surface of the semiconductor chip by an adhesive tape, and tie bars adhered to the short side of the upper surface of the semiconductor chip by the adhesive tape;

Bonding wires correspondingly electrically connecting the center pads to the inner leads; And

It characterized in that it comprises an encapsulant for encapsulating the respective parts from the external environment.

According to the present invention, not only the inner leads of the lead frame but also the tie bar are adhered to the semiconductor chip by the adhesive tape to enhance the adhesion between the semiconductor chip and the lead frame. Therefore, in the molding process, defects such as tilt and shift of the semiconductor chip may be prevented, thereby improving reliability of the molding process.

Hereinafter, a LOC type lead frame according to the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are given to the same parts as the conventional parts.

Referring to FIG. 2, opposite inner leads 111 of the LOC type lead frame 100 are bonded to both sides of an upper surface of the semiconductor chip 30 by an adhesive tape 20, and the semiconductor chip 30. The center pads 31 of the lead wire 100 are electrically connected to each other, and the inner side of the tie bar 113 of the lead frame 100 extends across the corresponding short side of the semiconductor chip 30. It is adhered to the adhesive tape 20, and the respective portions except for the outer leads 115 of the lead frame 100 are encapsulated within the outer boundary of the encapsulant 50. Of course, the tie bar 113 and the inner leads 111 may not be bonded to the same adhesive tape 20 but may be bonded to each separate adhesive tape (not shown).

After performing the conventional die attaching process using the LOC type lead frame 100 of the present invention configured as described above, the inner side of the upper side of the upper surface of the semiconductor chip 30 is formed by the adhesive tape 20 unlike the conventional art. The upper side of the upper surface of the semiconductor chip 30 is also bonded to the tie bar 113 by the adhesive tape 20. Therefore, since both the long side and the short side of the upper surface of the semiconductor chip 30 are bonded to the lead frame 100, the adhesive force between the semiconductor chip 30 and the lead frame 100 is enhanced.

Subsequently, the wire bonding process is performed in the same manner as in the prior art to correspond to the inner leads 111 and the center pads 31 of the semiconductor chip 30 to correspond to the bonding wire 33, for example, gold (Au) material. After the electrical connection by the fine wire is carried out in the same manner as in the conventional molding process to protect the respective parts from the external environment to form the encapsulant 50.

At this time, since the semiconductor chip 30 has a bearing force greater than the pressure of the molding resin flowing into the cavity of the molding die (not shown) to form the encapsulant 50, the lead frame (not a tilt or shift) 100).

Meanwhile, the leadframe 200 of the present invention may be configured as shown in FIG. 3 in place of the leadframe 100. That is, the lead frame 200 is integrated with the inner part of the neighboring outermost inner lead 111a while the tie bar 213 extends across the short side of the upper surface of the semiconductor chip 30 to be bonded to the adhesive tape 20. Except that connected to, the same as the structure of the lead frame 100 of FIG. 2 will be omitted for the convenience of description in order to avoid duplication of description.

Here, the tie bars 213 are respectively connected to the outermost inner leads 211a and 211b in order to eliminate an electrical short caused by being integrally connected to both of the outermost inner leads 211a and 211b. Naturally, the tie bars 213a and 213b should be separated.

As described above, the LOC type lead frame and the LOC package using the same according to the present invention are formed so that not only the inner leads of the lead frame but also the tie bar are positioned on the upper surface of the semiconductor chip, and the upper part of the semiconductor chip is formed by adhesive tape. Adhere to the cotton.

Accordingly, the present invention prevents defects such as tilting or shifting in the molding process by adhering the semiconductor chip to the tie bar together with the inner leads to prevent the occurrence of defects such as tilt or shift in the molding process, and further, incomplete molding or warping of the product. It prevents the occurrence of the same defect phenomenon.

On the other hand, it is obvious to those skilled in the art that the present invention is not limited to the contents described in the drawings and detailed description, and can be applied within the scope without departing from the spirit of the present invention.

Claims (4)

In the LOC type lead frame having inner leads having an inner portion located on the upper surface and a tie bar spaced apart from the semiconductor chip to adhere to the adhesive tape on the upper surface of the semiconductor chip, LOC type leadframe, characterized in that the inner portion of the tie bar is located on the upper surface for adhesion with the adhesive tape on the upper surface. The LOC type leadframe of claim 1, wherein an inner portion of the tie bar is integrally connected to a neighboring outermost inner lead among the inner leads. 3. The LOC type leadframe of claim 2, wherein the tie bars are respectively separated into corresponding tie bars of the outermost inner leads to prevent electrical shorting of the outermost inner leads. A semiconductor having center pads formed in a central portion of an upper surface thereof; A lead frame having inner leads and tie bars adhered to each other by an adhesive tape on an upper surface of the semiconductor chip; Bonding wires correspondingly electrically connecting the center pads to the inner leads; And And an encapsulant for encapsulating the respective parts from an external environment.