KR19990070612A - MOS field effect transistor manufacturing method - Google Patents
MOS field effect transistor manufacturing method Download PDFInfo
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- KR19990070612A KR19990070612A KR1019980005563A KR19980005563A KR19990070612A KR 19990070612 A KR19990070612 A KR 19990070612A KR 1019980005563 A KR1019980005563 A KR 1019980005563A KR 19980005563 A KR19980005563 A KR 19980005563A KR 19990070612 A KR19990070612 A KR 19990070612A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 230000005669 field effect Effects 0.000 title description 8
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 8
- 239000001301 oxygen Substances 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 238000000137 annealing Methods 0.000 claims abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 8
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 4
- -1 oxygen ion Chemical class 0.000 description 4
- 230000010354 integration Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 MOSFET 제조방법에 관한 것으로서 소스/드레인 졍션 하부 및 게이트 하단에 위치한 채널영역의 하부 벌크에 매몰산화층을 형성하므로서 셸로우졍션을 형성하여 서브마이크론단위소자에서 발생하는 쇼트채널효과 및 기생캐패시턴스를 감소시키며, 또한 채널영역의 매몰산화층 위에 인트린식 에피택샬층의 형성으로 트랜지스터의 모빌리티를 향상시켜 트랜지스터의 전류 구동력을 증가시킨다.The present invention relates to a method for manufacturing a MOSFET, and by forming a buried oxide layer in the bulk of the channel region located under the source / drain junction and the bottom of the gate, the shallow channel effect and parasitic capacitance generated in the submicron unit device are formed. In addition, the formation of an intrinsic epitaxial layer on the buried oxide layer in the channel region improves the mobility of the transistor, thereby increasing the current driving force of the transistor.
이를 위하여 본 발명은 반도체기판 표면에 제 1 절연막을 형성하는 단계와, 제 1 절연막의 소정부위를 제거하여 게이트형성부위에만 제 1 절연막을 잔류시키는 단계와, 잔류한 제 1 절연막을 마스크로 이용한 산소이온주입을 기판 전면에 실시하는 단계와, 잔류한 제 1 절연막을 제거한 후 어닐링을 실시하여 매몰산화층을 형성하는 단계와, 노출된 반도체기판의 표면에 반도체층을 형성하는 단계와, 반도체층의 표면에 게이트절연막을 형성하는 단계와, 게이트절연막 위에 제 1 도전층을 형성하는 단계와, 제 1 도전층과 게이트절연막의 소정부위를 제거하여 게이트를 패터닝하는 단계와, 게이트 하부에 형성된 매몰산화층을 제외한 나머지 매몰산화층 상부의 반도체기판 내부에 불순물확산영역을 형성하는 단계로 이루어진다.To this end, the present invention comprises the steps of forming a first insulating film on the surface of the semiconductor substrate, removing a predetermined portion of the first insulating film to leave the first insulating film only in the gate forming portion, and using the oxygen remaining the first insulating film as a mask Performing ion implantation on the entire surface of the substrate, removing the remaining first insulating film and performing annealing to form a buried oxide layer, forming a semiconductor layer on the exposed surface of the semiconductor substrate, and a surface of the semiconductor layer. Forming a gate insulating film on the gate insulating film, forming a first conductive layer on the gate insulating film, removing a predetermined portion of the first conductive layer and the gate insulating film, patterning the gate, and removing the buried oxide layer formed under the gate. And forming an impurity diffusion region in the semiconductor substrate above the remaining buried oxide layer.
Description
본 발명은 모스전계효과트랜지스터(MOS field effect transistor, 이하 MOSFET 이라 칭한다) 제조방법에 관한 것으로서, 특히, 단채널을 갖는 모스탠지스터에 있어서 트랜지스터의 소스, 드레인 및 채널영역 하부에 매몰절연층을 형성하여 트랜지스터의 단채널효과(short channel effect)를 개선하고 채널영역에 인트린식 애피택샬층을 형성하여 모빌리티(mobility)를 증가시키므로서 트랜지스터의 구동능력을 향상시킬 수 있는 구조를 갖는 소자를 형성하도록한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS field effect transistor (hereinafter referred to as a MOSFET). In particular, in a MOSFET having a short channel, a buried insulating layer is formed below the source, drain, and channel regions of the transistor. By improving the short channel effect of the transistor and forming an intrinsic epitaxial layer in the channel region to increase the mobility (mobility) to form a device having a structure that can improve the driving capability of the transistor It is about a method.
반도체장치는 양호한 회로 동작 성능과 집적도를 얻기위하여 집적 회로를 구성하는 MOSFET의 크기를 감소시키기 위한 노력의 결과로 반도체장치의 제조기술이 서브미크론(submicron) 단위로 축소(scale down)되었다. 따라서, 집적 회로 의 구성 요소인 단일 MOSFET에 있어서 게이트(gate line)의 폭이 좁아지게 되었으며, 그에 따라 게이트의 선저항이 크게 증가될 뿐만 아니라 인접하는 게이트들 사이의 공간(speace)의 감소에 의한 기생 커패시턴스(parastic capacitance)도 크게 증가되므로 회로의 신호전달 속도가 크게 저하되게 되었다. 즉, 회로의 신호 전달 속도에 영향을 미치는 지연시간(delay time)은 저항(R)과 커패시턴스(C)의 곱인 RC로 표시되는 데, 여기서, 저항(R)은 게이트의 선지항이고, 커패시턴스(C)는 인접하는 게이트 사이의 기생 커패시턴스이다.Semiconductor devices have been scaled down in submicron units as a result of efforts to reduce the size of MOSFETs constituting integrated circuits in order to obtain good circuit operation performance and integration. As a result, the gate line width becomes narrow in a single MOSFET, which is a component of an integrated circuit, and the gate resistance of the gate is not only greatly increased, but also due to the reduction of the peace between adjacent gates. Parasitic capacitance is also greatly increased, resulting in a significant decrease in the signal transmission speed of the circuit. In other words, the delay time affecting the signal transmission speed of the circuit is represented by RC, which is the product of the resistance R and the capacitance C, where the resistance R is the gate term of the gate, and the capacitance ( C) is the parasitic capacitance between adjacent gates.
또한 소자크기가 축소됨에 따라 트랜지스터의 채널길이 역시 줄어들게 되므로 쇼트채널효과(short channel effect)가 발생하게 된다. 쇼트채널효과는 MOSFET 등에서 게이트 길이 즉 소스와 드레인 사이의 간격이 짧아지는 경우에 발생한다. 드레인 전압을 일정하게 유지하고 채널길이를 짧게하면 드레인과 소스로 부터의 공핍층이 게이트 밑의 기판으로 삐져나오게 되기 때문에 채널부분의 전위장벽이 저하하여 드레인 전압의 약간의 증가에 의해 드레인 전류가 급증하고, 이것이 진행되면 공핍층의 접촉에 의한 펀치스루(punch-through)가 생긴다. 이러한 펀치스루 현상을 방지하기 위해서 기판의 공핍층의 폭을 감소시키기 위하여 도핑농도를 증가시킨다.In addition, as the device size is reduced, the channel length of the transistor is also reduced, resulting in a short channel effect. The short channel effect occurs when the gate length, i.e., the gap between the source and the drain, becomes short in a MOSFET or the like. If the drain voltage is kept constant and the channel length is shortened, the depletion layer from the drain and the source will stick out to the substrate under the gate. Therefore, the potential barrier of the channel portion is lowered and the drain current increases rapidly due to the slight increase in the drain voltage. As this progresses, punch-through occurs due to contact of the depletion layer. In order to prevent such a punch-through phenomenon, the doping concentration is increased to reduce the width of the depletion layer of the substrate.
이와 유사하게 또 다른 효과 즉 드레인전위장벽저하(drain-induced barrier lowering, DIBL)가 발생한다. 이는 드레인 전압이 표면전위(surface potential)을 저하시키는 것이다. 결국 기판표면에서의 전위장벽이 낮아지고 채널영역의 실리콘과 산화막의 계면에서 전류가 증가하게 된다.Similarly, another effect arises: drain-induced barrier lowering (DIBL). This is because the drain voltage lowers the surface potential. As a result, the potential barrier at the substrate surface is lowered and the current increases at the interface between the silicon and the oxide film in the channel region.
이러한 쇼트채널효과를 방지하기 위하여 소스/드레인 졍션을 얕게(shallow junction) 형성할 수 있다.In order to prevent such a short channel effect, a source / drain junction may be shallowly formed.
종래 기술은 소스/드레인 졍션을 불순물이온주입후 어닐링(annealing) 공정으로 형성하기 때문에 셸로우졍션을 형성하기 곤란하다.In the prior art, it is difficult to form a shallow junction because the source / drain cushion is formed by an annealing process after impurity ion implantation.
도 1 는 종래 기술에 따른 모스전계효과트랜지스터의 단면도이다.1 is a cross-sectional view of a MOS field effect transistor according to the prior art.
반도체기판인 실리콘기판(1) 위에 게이트절연막(2)이 형성되어 있고 그 위에 패터닝된 도전성을 갖는 도핑된 폴리실리콘으로 이루어진 게이트(5)가 위치한다. 게이트(5)를 마스크로 이용한 이온주입으로 불순물매몰층을 형성한 후 어닐링을 실시하여 형성된 소스(3)/드레인(4) 졍션이 게이트(5) 하단 기판(1) 표면 부위에 위치한다.A gate insulating film 2 is formed on a silicon substrate 1, which is a semiconductor substrate, and a gate 5 made of doped polysilicon having a patterned conductivity is positioned thereon. After forming the impurity buried layer by ion implantation using the gate 5 as a mask, the source 3 / drain 4 section formed by annealing is positioned on the surface of the lower substrate 1 of the gate 5.
그러나, 상술한 종래 기술에 따라 제조된 MOSFET은 어닐링으로 소스/드레인 졍션을 형성하므로 셸로우졍션을 형성하기 곤란하므로 졍션에서의 기생 캐패시턴스가 큰 값을 갖게 되며, 쇼트채널트랜지스터 구현시 졍션의 공핍층에 의한 드레인전위장벽저하(drain-induced barrier lowering, DIBL) 및 펀치스루(punch-through)를 방지할 수 없으며, 채널영역 형성시 문턱전압을 조절하기 위한 이온주입에 기인한 채널에서의 모빌리티(mobility) 감소로 전류구동능력이 저하된다. 이는 고속동작을 요구하는 고집적소자 구현에 곤란한 문제점이 있다.However, since the MOSFET fabricated according to the above-described prior art forms a source / drain junction by annealing, it is difficult to form a shallow junction, so the parasitic capacitance in the junction has a large value. It is not possible to prevent drain-induced barrier lowering (DIBL) and punch-through by the channel, and the mobility in the channel due to ion implantation to adjust the threshold voltage when forming the channel region ) Decreasing current driving ability. This is a difficult problem to implement a high integration device requiring a high speed operation.
따라서, 본 발명의 목적은 소스/드레인 졍션 하부 및 게이트 하단에 위치한 채널영역의 하부 벌크에 매몰산화층을 형성하므로서 셸로우졍션을 형성하여 서브마이크론단위소자에서 발생하는 쇼트채널효과 및 기생캐패시턴스를 감소시키며, 또한 채널영역의 매몰산화층 위에 인트린식 에피택샬층의 형성으로 트랜지스터의 모빌리티를 향상시켜 트랜지스터의 전류 구동력을 증가시키는 모스전계효과트랜지스터 제조방법을 제공하는데 있다.Accordingly, an object of the present invention is to form a shallow oxide by forming a buried oxide layer in the lower bulk of the channel region located under the source / drain junction and the lower gate to reduce the short channel effect and parasitic capacitance occurring in the submicron unit device. In addition, the present invention provides a method for manufacturing a MOS field effect transistor, which increases the current driving force of the transistor by improving the mobility of the transistor by forming an intrinsic epitaxial layer on the buried oxide layer of the channel region.
상기 목적을 달성하기 위한 본 발명에 따른 모스전계효과트랜지스터 제조방법은 반도체기판 표면에 제 1 절연막을 형성하는 단계와, 제 1 절연막의 소정부위를 제거하여 게이트형성부위에만 제 1 절연막을 잔류시키는 단계와, 잔류한 제 1 절연막을 마스크로 이용한 산소이온주입을 기판 전면에 실시하는 단계와, 잔류한 제 1 절연막을 제거한 후 어닐링을 실시하여 매몰산화층을 형성하는 단계와, 노출된 반도체기판의 표면에 반도체층을 형성하는 단계와, 반도체층의 표면에 게이트절연막을 형성하는 단계와, 게이트절연막 위에 제 1 도전층을 형성하는 단계와, 제 1 도전층과 게이트절연막의 소정부위를 제거하여 게이트를 패터닝하는 단계와, 게이트 하부에 형성된 매몰산화층을 제외한 나머지 매몰산화층 상부의 반도체기판 내부에 불순물확산영역을 형성하는 단계로 이루어진다.According to the present invention, there is provided a method of manufacturing a MOS field effect transistor according to the present invention, including forming a first insulating film on a surface of a semiconductor substrate, and removing a predetermined portion of the first insulating film to leave the first insulating film only at the gate forming portion. And performing oxygen ion implantation using the remaining first insulating film as a mask on the entire surface of the substrate, removing the remaining first insulating film, and performing annealing to form a buried oxide layer, and forming a buried oxide layer on the exposed surface of the semiconductor substrate. Forming a semiconductor layer, forming a gate insulating film on the surface of the semiconductor layer, forming a first conductive layer on the gate insulating film, and removing a predetermined portion of the first conductive layer and the gate insulating film to pattern the gate. And an impurity diffusion region in the semiconductor substrate above the remaining buried oxide layer except for the buried oxide layer formed under the gate. A step of forming.
도 1 는 종래 기술에 따른 모스전계효과트랜지스터의 단면도1 is a cross-sectional view of a MOS field effect transistor according to the prior art
도 2a 내지 도 2f는 본 발명에 따른 모스전계효과트랜지스터의 제조공정 단면도2A to 2F are cross-sectional views of a manufacturing process of a MOS field effect transistor according to the present invention.
도 2a 내지 도 2f는 본 발명에 따른 모스전계효과트랜지스터의 제조공정 단면도이다.2A to 2F are cross-sectional views of a manufacturing process of a MOS field effect transistor according to the present invention.
도 2a를 참조하면, 실리콘 반도체기판(21) 표면에 제 1 절연막(22)을 증착하여 형성한 후 제 1 절연막(22)의 표면에 포토레지스트를 도포한 후 게이트형성용 마스크를 이용한 사진공정을 실시하여 포토레지스트패턴(23)을 정의한다.Referring to FIG. 2A, after the first insulating film 22 is formed on the surface of the silicon semiconductor substrate 21, a photoresist is applied to the surface of the first insulating film 22, and then a photo process using a gate forming mask is performed. The photoresist pattern 23 is defined.
도 2b를 참조하면, 포토레지스트패턴(23)을 마스크로 이용한 식각공정을 실시하여 포토레지스트패턴(23)으로 보호되지 아니하는 부위의 제 1 절연막(22)을 제거한 다음 포토레지스트패턴(23)을 제거한다.Referring to FIG. 2B, an etching process using the photoresist pattern 23 as a mask is performed to remove the first insulating layer 22 at a portion not protected by the photoresist pattern 23, and then the photoresist pattern 23 is removed. Remove
그리고 잔류한 제 1 절연막(22)을 마스크로 이용한 산소이온주입을 기판(21) 전면에 실시하여 산소이온매몰층(점선)을 기판(21) 내부에 형성한다. 이때 형성되는 산소이온매몰층(점선)은 잔류한 제 1 절연막(22)의 두께 만큼 매몰 깊이가 차이난다.Oxygen ion implantation using the remaining first insulating film 22 as a mask is applied to the entire surface of the substrate 21 to form an oxygen ion buried layer (dotted line) inside the substrate 21. At this time, the buried depth of the oxygen ion buried layer (dotted line) formed differs by the thickness of the remaining first insulating film 22.
도 2c를 참조하면, 잔류한 제 1 절연막을 제거한 후, 기판(21)에 어닐링을 실시하여 산소이온매몰층의 산소이온들이 기판의 실리콘을 산화시켜 기판벌크내부에 매몰된 형태의 매몰산화층(24)을 형성한다.Referring to FIG. 2C, after removing the remaining first insulating layer, the substrate 21 is annealed to form a buried oxide layer 24 in which oxygen ions in the oxygen ion buried layer oxidize silicon of the substrate to be buried in the substrate bulk. ).
그리고 다시 전면이 노출된 기판(21)의 표면에 실리콘 인트린식 에피택샬층(intrinsic epitaxial layer)(25)을 성장시켜 형성한다.The silicon intrinsic epitaxial layer 25 is grown on the surface of the substrate 21 on which the entire surface is exposed.
도 2d를 참조하면, 에피택샬층(25)의 표면을 열산화시켜 산화막으로 이루어진 게이트절연막(26)을 형성한 다음 다시 그(26) 위에 게이트전극으로 사용될 제 1 도전층(27)을 도핑된 폴리실리콘을 증착하여 형성한다.Referring to FIG. 2D, the surface of the epitaxial layer 25 is thermally oxidized to form a gate insulating film 26 made of an oxide film, and then doped with a first conductive layer 27 to be used as a gate electrode thereon. It is formed by depositing polysilicon.
도 2e를 참조하면, 포토레지스트를 제 1 도전층(27) 위에 도포한 다음 게이트 형성용 마스크를 이용한 사진식각공정을 실시하여 제 1 도전층(27)과 게이트절연막(26)의 소정부위를 제거하여 게이트(27)를 패터닝한다.Referring to FIG. 2E, a photoresist is coated on the first conductive layer 27 and then a photolithography process using a mask for forming a gate is performed to remove predetermined portions of the first conductive layer 27 and the gate insulating layer 26. The gate 27 is patterned by this.
그리고 게이트(27)를 이온주입마스크로 이용한 불순물이온주입을 기판(21)의 전면에 실시하여 소스/드레인 형성을 위한 불순물매몰층(점선)을 형성한다. 이때 형성되는 불순물매몰층은 이전단계에서 형성된 매몰산화층(24) 상부중 소스/드레인 형성부위에만 형성된다.Impurity ion implantation using the gate 27 as an ion implantation mask is performed on the entire surface of the substrate 21 to form an impurity buried layer (dotted line) for source / drain formation. The impurity buried layer formed at this time is formed only at the source / drain formation part of the buried oxide layer 24 formed in the previous step.
도 2f를 참조하면, 소스/드레인 형성용 불순물매몰층의 불순물이온을 어닐링시켜 확산시켜 불순물 확산영역(28, 29)을 형성한다. 이때 확산되는 불순물영역(28, 29)은 확산방향이 측방향으로만 이루어지고 수직하단방향으로는 매립산화층(24)이 확산방해층(stopper)으로 작용하므로 셸로우 소스(28)/드레인(29)졍션을 형성하게 된다. 즉 매립산화층(24)의 깊이를 제어하므로서 소스/드레인 졍션의 기판표면으로 부터의 형성깊이를 제어할 수 있다. 또한 게이트(27) 하단, 즉 채널 하부에 형성된 매몰산화층은 소스(28)/드레인(29) 졍션에 의한 공핍층(depletion)이 형성되는 것을 막아 펀치스루 및 드레인전위장벽저하(drain-induced barrier lowering, DIBL)특성을 개선할 수 있다.Referring to FIG. 2F, impurity ions in the source / drain formation impurity buried layer are annealed and diffused to form impurity diffusion regions 28 and 29. In this case, the impurity regions 28 and 29 to be diffused have a diffusion direction only in the lateral direction, and in the vertical lower direction, the buried oxide layer 24 acts as a diffusion barrier, so that the shallow source 28 / drain 29 To form a section. That is, the depth of formation of the source / drain junction from the substrate surface can be controlled by controlling the depth of the buried oxide layer 24. In addition, the buried oxide layer formed at the bottom of the gate 27, i.e., under the channel, prevents depletion due to the source 28 / drain 29 junction to form a punch-through and drain-down barrier lowering. , DIBL) characteristics can be improved.
따라서, 본 발명은 소스/드레인 졍션 하부 및 게이트 하단에 위치한 채널영역의 하부 벌크에 매몰산화층을 형성하므로서 셸로우졍션을 형성하여 서브마이크론단위소자에서 발생하는 쇼트채널효과 및 기생캐패시턴스를 감소시키며, 또한 채널영역의 매몰산화층 위에 인트린식 에피택샬층의 형성으로 트랜지스터의 모빌리티를 향상시켜 트랜지스터의 전류 구동력을 증가시키므로 고속동작속도를 요구하는 집적회로구현에 적합한 장점이 있다.Therefore, the present invention forms a shallow oxide layer in the lower bulk of the channel region located under the source / drain junction and under the gate to form a shallow junction, thereby reducing the short channel effect and parasitic capacitance occurring in the submicron unit device. The formation of an intrinsic epitaxial layer on the buried oxide layer in the channel region improves the mobility of the transistor to increase the current driving force of the transistor, which is suitable for implementing an integrated circuit requiring a high speed of operation.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100699819B1 (en) * | 2001-01-12 | 2007-03-27 | 삼성전자주식회사 | Method of forming metal-oxide-semiconductor transistor |
| KR100752182B1 (en) * | 2005-10-12 | 2007-08-24 | 동부일렉트로닉스 주식회사 | CMOS image sensor and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100699819B1 (en) * | 2001-01-12 | 2007-03-27 | 삼성전자주식회사 | Method of forming metal-oxide-semiconductor transistor |
| KR100752182B1 (en) * | 2005-10-12 | 2007-08-24 | 동부일렉트로닉스 주식회사 | CMOS image sensor and method for manufacturing the same |
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