KR19990063359A - 접합 패드를 가진 이중 다마스크식 공정 - Google Patents
접합 패드를 가진 이중 다마스크식 공정 Download PDFInfo
- Publication number
- KR19990063359A KR19990063359A KR1019980057481A KR19980057481A KR19990063359A KR 19990063359 A KR19990063359 A KR 19990063359A KR 1019980057481 A KR1019980057481 A KR 1019980057481A KR 19980057481 A KR19980057481 A KR 19980057481A KR 19990063359 A KR19990063359 A KR 19990063359A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- via hole
- insulator layer
- etching
- bond pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
- H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07553—Controlling the environment, e.g. atmosphere composition or temperature changes in shapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/29—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/934—Cross-sectional shape, i.e. in side view
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US8/997,682 | 1997-12-23 | ||
| US08/997,682 US6033984A (en) | 1997-12-23 | 1997-12-23 | Dual damascene with bond pads |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19990063359A true KR19990063359A (ko) | 1999-07-26 |
Family
ID=25544264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980057481A Ceased KR19990063359A (ko) | 1997-12-23 | 1998-12-23 | 접합 패드를 가진 이중 다마스크식 공정 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6033984A (https=) |
| EP (1) | EP0926721A3 (https=) |
| JP (1) | JPH11312704A (https=) |
| KR (1) | KR19990063359A (https=) |
| TW (1) | TW436930B (https=) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4651815B2 (ja) * | 1998-01-23 | 2011-03-16 | ローム株式会社 | ダマシン配線および半導体装置 |
| US6090696A (en) * | 1999-10-20 | 2000-07-18 | Taiwan Semicondutor Manufacturing Company | Method to improve the adhesion of a molding compound to a semiconductor chip comprised with copper damascene structures |
| US6191023B1 (en) * | 1999-11-18 | 2001-02-20 | Taiwan Semiconductor Manufacturing Company | Method of improving copper pad adhesion |
| US6838769B1 (en) | 1999-12-16 | 2005-01-04 | Agere Systems Inc. | Dual damascene bond pad structure for lowering stress and allowing circuitry under pads |
| US6417087B1 (en) * | 1999-12-16 | 2002-07-09 | Agere Systems Guardian Corp. | Process for forming a dual damascene bond pad structure over active circuitry |
| GB2364170B (en) * | 1999-12-16 | 2002-06-12 | Lucent Technologies Inc | Dual damascene bond pad structure for lowering stress and allowing circuitry under pads and a process to form the same |
| US6551856B1 (en) * | 2000-08-11 | 2003-04-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming copper pad redistribution and device formed |
| US6960496B2 (en) * | 2003-04-03 | 2005-11-01 | Taiwan Semiconductor Manufacturing | Method of damascene process flow |
| US20060071304A1 (en) * | 2004-09-29 | 2006-04-06 | International Business Machines Corporation | Structure and layout of a fet prime cell |
| US20060211167A1 (en) * | 2005-03-18 | 2006-09-21 | International Business Machines Corporation | Methods and systems for improving microelectronic i/o current capabilities |
| US7425507B2 (en) * | 2005-06-28 | 2008-09-16 | Micron Technology, Inc. | Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures |
| US20110156260A1 (en) * | 2009-12-28 | 2011-06-30 | Yu-Hua Huang | Pad structure and integrated circuit chip with such pad structure |
| US20120273937A1 (en) * | 2011-04-30 | 2012-11-01 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer |
| US8575022B2 (en) * | 2011-11-28 | 2013-11-05 | International Business Machines Corporation | Top corner rounding of damascene wire for insulator crack suppression |
| US20250062124A1 (en) * | 2023-08-18 | 2025-02-20 | Tokyo Electron Limited | Methods and structures for improving etch profile of underlying layers |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2428373C2 (de) * | 1974-06-12 | 1982-05-27 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum Herstellen von weichlötbaren Anschlußkontakten auf einer Halbleiteranordnung |
| JPS5561027A (en) * | 1978-10-30 | 1980-05-08 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Gas plasma etching |
| US5266446A (en) * | 1990-11-15 | 1993-11-30 | International Business Machines Corporation | Method of making a multilayer thin film structure |
| US5618381A (en) * | 1992-01-24 | 1997-04-08 | Micron Technology, Inc. | Multiple step method of chemical-mechanical polishing which minimizes dishing |
| US5773363A (en) * | 1994-11-08 | 1998-06-30 | Micron Technology, Inc. | Semiconductor processing method of making electrical contact to a node |
| US5516710A (en) * | 1994-11-10 | 1996-05-14 | Northern Telecom Limited | Method of forming a transistor |
| US5534462A (en) * | 1995-02-24 | 1996-07-09 | Motorola, Inc. | Method for forming a plug and semiconductor device having the same |
| US5739563A (en) * | 1995-03-15 | 1998-04-14 | Kabushiki Kaisha Toshiba | Ferroelectric type semiconductor device having a barium titanate type dielectric film and method for manufacturing the same |
| JP2728025B2 (ja) * | 1995-04-13 | 1998-03-18 | 日本電気株式会社 | 半導体装置の製造方法 |
| US5534460A (en) * | 1995-04-27 | 1996-07-09 | Vanguard International Semiconductor Corp. | Optimized contact plug process |
| US5780337A (en) * | 1996-09-23 | 1998-07-14 | United Microelectronics Corporation | Method of fabricating a bit line of a dynamic random access memory |
| US5877076A (en) * | 1997-10-14 | 1999-03-02 | Industrial Technology Research Institute | Opposed two-layered photoresist process for dual damascene patterning |
-
1997
- 1997-12-23 US US08/997,682 patent/US6033984A/en not_active Expired - Lifetime
-
1998
- 1998-10-29 EP EP98120465A patent/EP0926721A3/en not_active Withdrawn
- 1998-11-09 TW TW087118611A patent/TW436930B/zh not_active IP Right Cessation
- 1998-12-22 JP JP10365074A patent/JPH11312704A/ja active Pending
- 1998-12-23 KR KR1019980057481A patent/KR19990063359A/ko not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| EP0926721A2 (en) | 1999-06-30 |
| EP0926721A3 (en) | 2001-12-19 |
| TW436930B (en) | 2001-05-28 |
| JPH11312704A (ja) | 1999-11-09 |
| US6033984A (en) | 2000-03-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
St.27 status event code: A-0-1-A10-A12-nap-PA0109 |
|
| R17-X000 | Change to representative recorded |
St.27 status event code: A-3-3-R10-R17-oth-X000 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-3-3-R10-R13-asn-PN2301 St.27 status event code: A-3-3-R10-R11-asn-PN2301 |
|
| A201 | Request for examination | ||
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
St.27 status event code: N-2-6-B10-B15-exm-PE0601 |
|
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-3-3-R10-R18-oth-X000 |
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| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-3-3-R10-R18-oth-X000 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |