KR19990062217A - Field transistor structure of semiconductor device - Google Patents
Field transistor structure of semiconductor device Download PDFInfo
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- KR19990062217A KR19990062217A KR1019970082528A KR19970082528A KR19990062217A KR 19990062217 A KR19990062217 A KR 19990062217A KR 1019970082528 A KR1019970082528 A KR 1019970082528A KR 19970082528 A KR19970082528 A KR 19970082528A KR 19990062217 A KR19990062217 A KR 19990062217A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 28
- 238000009792 diffusion process Methods 0.000 claims abstract description 26
- 238000002955 isolation Methods 0.000 claims abstract description 18
- 239000000969 carrier Substances 0.000 claims abstract description 11
- 150000002500 ions Chemical class 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims 1
- 229910052709 silver Inorganic materials 0.000 claims 1
- 239000004332 silver Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 230000003068 static effect Effects 0.000 description 13
- 230000005611 electricity Effects 0.000 description 12
- 239000002184 metal Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 정전기방지회로에서 필드트랜지스터의 항복전압을 높이고 전류밀도를 낮추어 소자의 손상을 방지할 수 있도록 한 반도체장치의 필드트랜지스터 구조에 관한 것으로, 낮은 농도로 도핑된 제1웰에 다수캐리어가 도핑된 불순물확산영역과 소자분리막이 형성되는 필드트랜지스터 구조에 있어서, 다수캐리어가 도핑된 불순물확산영역과 소자분리막 하부에 다수캐리어로 도핑된 채널정지층 사이에 불순물확산영역에 도핑된 이온이 낮은 농도로 도핑되어 형성되는 제2웰을 더 포함하여 이루어져 항복전압이 제2웰의 전부위에 걸려 전류밀도를 낮게 하도록 하는 것을 특징으로 한다.The present invention relates to a field transistor structure of a semiconductor device in which a breakdown voltage of a field transistor is increased and a current density is prevented in an antistatic circuit, thereby preventing damage to the device. A plurality of carriers are doped in a low concentration doped first well. In a field transistor structure in which an impurity diffusion region and a device isolation film are formed, a low concentration of ions doped in an impurity diffusion region is formed between an impurity diffusion region doped with multiple carriers and a channel stop layer doped with multiple carriers under the element isolation film. It further comprises a doped second well is formed so that the breakdown voltage across the second well to lower the current density.
Description
본 발명은 반도체장치의 필드트랜지스터 구조에 관한 것으로서, 보다 상세하게는 정전기방지회로에서 필드트랜지스터의 항복전압을 높이고 전류밀도를 낮추어 소자의 손상을 방지할 수 있도록 한 반도체장치의 필드트랜지스터 구조에 관한 것이다.The present invention relates to a field transistor structure of a semiconductor device. More particularly, the present invention relates to a field transistor structure of a semiconductor device in which the breakdown voltage of the field transistor and the current density of the field transistor can be prevented in an antistatic circuit. .
반도체소자의 경우 정전기(Electro Static Charge; ESD)에 의하여 손상을 입게되는데 이는 사람에 의해 발생되는 약 -2,000V의 정전기나, 기계에 의해 발생되는 약 -250V의 정전기에 의해 설명되고 있다.Semiconductor devices are damaged by electrostatic charge (ESD), which is explained by about -2,000V of static electricity generated by humans or about -250V of static electricity generated by machines.
일반적으로 로직칩의 경우 많은 패드가 필요하기 때문에 이로 인하여 정전기의 보호회로의 크기는 한계를 가지며 보통 패드에 제한된 디자인의 형태를 가진다. 이 때문에 로직칩에서의 정전기회로의 구성은 보통 폴리게이트를 이용한 능동트랜지스터의 형태로 구성되어 있다.In general, a large number of pads are required for a logic chip, and thus, the size of the static electricity protection circuit is limited and usually has a pad-limited design. For this reason, the structure of the electrostatic circuit in a logic chip is usually configured in the form of an active transistor using a polygate.
도1은 일반적인 로직칩에서 사용되는 데이터 입출력핀에서 사용되는 정전기방지회로의 대표적인 회로도이다.1 is a representative circuit diagram of an antistatic circuit used in a data input / output pin used in a general logic chip.
도1에 도시된 바와 같이 내부회로(15)와 연결된 패드(10)사이에 게이트와 드레인이 전원전압(Vcc)에 연결되고 소오스가 패드(10)에 연결된 PMOSFET(Q1)와, 게이트와 소오스가 접지(Vss)와 연결되고 드레인이 패드(10)에 연결된 NMOSFET(Q2)와, 게이트와 드레인이 패드(10)에 연결되고 소오스가 접지(Vss)에 연결된 필드 트랜지스터(20)로 이루어진다.As shown in FIG. 1, a gate and a drain are connected to a power supply voltage Vcc between a pad 10 connected to an internal circuit 15, and a PMOSFET Q1 having a source connected to the pad 10, and a gate and a source. NMOSFET Q2 connected to ground Vss and having drain connected to pad 10, and field transistor 20 having a gate and drain connected to pad 10 and a source connected to ground Vss.
정상동작시에는 PMOSFET(Q1)와 NMOSFET(Q2)는 오프되어 데이터의 입출력시 영향을 주지 않지만 패드(10)를 통해 정전기가 유입될 경우에는 전원전압(Vcc)과 접지(Vss)는 모두 접지전위를 가지고 있기 때문에 (+)의 정전기가 유입될 경우에는 PMOSFET(Q1)가 온되어 유입된 정전기는 접지로 흘러가게 되며 (-)의 정전기가 유입될 경우에는 NMOSFET(Q2)가 온되어 유입된 정전기는 접지로 흘러가게 되어 내부회로를 보호하게 된다.In normal operation, the PMOSFET Q1 and the NMOSFET Q2 are turned off and do not affect data input / output, but when static electricity flows through the pad 10, both the power voltage Vcc and the ground Vss are ground potential. If positive (+) static electricity flows in, PMOSFET (Q1) is turned on and the static electricity flows to ground, and when negative (-) static electricity flows, NMOSFET (Q2) is turned on Flows to ground to protect the internal circuits.
그리고 필드 트랜지스터(20)를 이용하여 패드(10)를 통해 높은 전압이 인가될 경우 필드 트랜지스터(20)의 펀치스루효과로 인해 유입된 정전기는 모두 접지로 분산시킬 수 있게 된다.In addition, when a high voltage is applied through the pad 10 using the field transistor 20, all the static electricity introduced due to the punch-through effect of the field transistor 20 may be dispersed to the ground.
도2는 도1의 반도체장치의 정전기방지회로의 필드 트랜지스터 구조를 나타낸 단면도이다.FIG. 2 is a cross-sectional view illustrating a field transistor structure of the antistatic circuit of the semiconductor device of FIG. 1.
도2에 도시된 바와 같이 반도체기판(31)에 형성된 P-Well(32)과, P-Well(32)에 소자간의 분리를 위해 형성된 소자분리막(33)과, 소자분리막(33) 하부에 채널정지를 위해 p+가 이온주입된 채널정지층(36)과, 소자분리막(33) 양쪽으로 n+ 불순물이 확산된 불순물확산영역(34)과, 소자분리막(34) 상부에 형성된 메탈라인(35)으로 이루어진다.As shown in FIG. 2, the P-Well 32 formed on the semiconductor substrate 31, the device isolation film 33 formed on the P-Well 32 to separate the devices, and a channel under the device isolation film 33. A channel stop layer 36 into which p + is implanted to stop, an impurity diffusion region 34 in which n + impurities are diffused into both device isolation layers 33, and a metal line 35 formed on the device isolation layer 34 Is done.
그리고 메탈라인(35)과 불순물확산영역(34)의 일측과 서로 연결되어 정전기 유입단인 패드(10)에 연결되고 불순물확산영역(34)의 타측은 접지(Vss)와 연결된다.The metal line 35 and one side of the impurity diffusion region 34 are connected to each other, and are connected to the pad 10, which is an electrostatic inflow terminal, and the other side of the impurity diffusion region 34 is connected to the ground Vss.
도2에서와 같이 형성된 필드트랜지스터의 작동을 설명하면 다음과 같다.Referring to the operation of the field transistor formed as in Figure 2 as follows.
정전기가 패드(10)로부터 유입되면 소자분리막(33) 하부의 n+ 불순물확산영역(34)과 채널정지층(36)의 p+경계에 정전기 스트레스가 가해져 'A'부분과 같이 취약한 부분이 손상된다.When static electricity flows from the pad 10, an electrostatic stress is applied to the n + impurity diffusion region 34 and the channel stop layer 36 under the device isolation layer 33 to damage a weak portion such as an 'A' portion.
일반적인 동작시 패드(10)를 통해 정전기가 가해지면 n+ 불순물확산영역(34)과 채널정지층(36)의 p+사이에 항복현상이 발생하여 전류(I)가 흘러 채널정지층(36)의 p+에 전압이 높아지고 p+와 n+ 사이의 순방향 접합에 의해 접지(Vss)로 방전된다.In the normal operation, when static electricity is applied through the pad 10, a breakdown phenomenon occurs between the n + impurity diffusion region 34 and the p + of the channel stop layer 36 so that the current I flows to p + of the channel stop layer 36. The voltage rises and discharges to ground (Vss) by the forward junction between p + and n +.
이때 소자분리막(33) 하부의 농도가 높은 n+와 p+ 접합이 공핍층이 얇아 항복전압이 낮아지므로 방전전류(I)의 패스가 좁은 면적으로 형성되어 전류밀도가 높아지고 열의 발생으로 소자가 손상된다는 문제점이 있다.In this case, since the n + and p + junctions in the lower portion of the device isolation layer 33 have a low depletion layer due to a thin depletion layer, a path of the discharge current I is formed in a narrow area, resulting in high current density and damage to the device due to heat generation. There is this.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 다수캐리어가 도핑된 불순물확산영역과 소자분리막 하부에 다수캐리어로 도핑된 채널정지층 사이에 불순물확산영역에 도핑된 이온이 낮은 농도로 도핑된 웰을 형성하여 공핍층이 두껍게 형성되도록 한 반도체장치의 필드트랜지스터 구조를 제공함에 있다.The present invention was created to solve the above problems, and an object of the present invention is an ion doped in an impurity diffusion region between an impurity diffusion region doped with multiple carriers and a channel stop layer doped with multiple carriers under the device isolation layer. The present invention provides a field transistor structure of a semiconductor device in which a well-doped well is formed to form a thick depletion layer.
도1은 일반적인 필드트랜지스터를 사용한 정전기방지회로를 나타낸 회로도이다.1 is a circuit diagram showing an antistatic circuit using a general field transistor.
도2는 일반적으로 정전기방지회로에 사용되는 필드트랜지스터의 구조를 나타낸 단면도이다.2 is a cross-sectional view showing a structure of a field transistor generally used in an antistatic circuit.
도3은 본 발명에 의한 반도체장치의 필드트랜지스터 구조를 나타낸 단면도이다.3 is a cross-sectional view showing a field transistor structure of the semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10 : 패드 15 : 내부회로10: pad 15: internal circuit
20 : 필드트랜지스터 31 : 기판20: field transistor 31: substrate
32 : P-Well 33 : 소자분리막32: P-Well 33: device isolation film
34 : 불순물확산영역 35 : 메탈라인34 impurity diffusion region 35 metal line
36 채널정지층 40 : N-Well36 Channel Stop Floor 40: N-Well
상기와 같은 목적을 실현하기 위한 본 발명은 낮은 농도로 도핑된 제1웰에 다수캐리어가 도핑된 불순물확산영역과 소자분리막이 형성되는 필드트랜지스터 구조에 있어서, 다수캐리어가 도핑된 불순물확산영역과 소자분리막 하부에 다수캐리어로 도핑된 채널정지층 사이에 불순물확산영역에 도핑된 이온이 낮은 농도로 도핑되어 형성되는 제2웰을 더 포함하여 이루어진다.The present invention provides a field transistor structure in which an impurity diffusion region and a device isolation film doped with multiple carriers are formed in a first well doped at a low concentration, and an impurity diffusion region and an element doped with multiple carriers are formed. And a second well formed between the channel stop layer doped with a plurality of carriers in the lower part of the separator by a low concentration of ions doped in the impurity diffusion region.
상기와 같이 이루어진 필드트랜지스터는 정전기 스트레스가 가해지면 불순물확산영역을 통해 웰에 고전압이 가해져 웰과 채널정지층사이에 항복효과가 발생되어 전류가 흐를 때 웰의 전부위에 항복전압이 동일하여 방전전류가 분산되어 흐르게 되어 전류밀도가 낮아지게 된다.When the field transistor is configured as described above, when the electrostatic stress is applied, a high voltage is applied to the well through the impurity diffusion region, and a breakdown effect is generated between the well and the channel stop layer. It is dispersed and flows, and the current density is lowered.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도3은 본 발명에 따른 실시예로서 정전기방지회로에 사용되는 필드트랜지스터의 구조를 나타낸 단면도이다.3 is a cross-sectional view showing the structure of a field transistor used in an antistatic circuit as an embodiment according to the present invention.
도3에 도시된 바와 같이 반도체기판(31)에 P-Well(32)이 형성되고, P-Well(32)에 소자간의 분리를 위해 소자분리막(33)이 형성된다. 그리고 소자분리막(33) 하부에 소자분리특성을 향상시키기 위해 높은 농도의 p+이 이온주입된 채널정지층(36)이 형성된다. 또한 소자분리막(33) 양쪽으로 n+ 불순물이 확산된 불순물확산영역(34)이 형성된다. 그리고 불순물확산영역(34)의 일측과 채널정지층(36) 사이에 N-Well(40)이 형성되며, 소자분리막(33) 상부에 메탈라인(35)이 형성되어 메탈라인(35)과 불순물확산영역(34)의 일측과 연결되어 정전기 유입단인 패드에(10) 연결된다. 그리고 불순물확산영역(34)의 타측은 접지(Vss)와 연결된다.As shown in FIG. 3, the P-Well 32 is formed on the semiconductor substrate 31, and the device isolation layer 33 is formed on the P-Well 32 to separate the devices. In addition, a channel stop layer 36 in which a high concentration of p + is implanted is formed under the device isolation layer 33 to improve device isolation characteristics. In addition, an impurity diffusion region 34 in which n + impurities are diffused is formed on both sides of the device isolation layer 33. In addition, an N-Well 40 is formed between one side of the impurity diffusion region 34 and the channel stop layer 36, and a metal line 35 is formed on the device isolation layer 33 to form the metal line 35 and impurities. It is connected to one side of the diffusion region 34 is connected to the pad (10) which is the static inflow terminal. The other side of the impurity diffusion region 34 is connected to the ground Vss.
상기와 같이 이루어진 필드트랜지스터의 작동을 설명하면 다음과 같다.Referring to the operation of the field transistor made as described above is as follows.
패드(10)를 통해 정전기가 유입될 경우 정정기 스트레스가 n+ 불순물확산영역을 통해 N-Well(40)에 고전압이 가해져 N-Well(40)과 p+인 채널정지층(36)사이에 항복효과가 발생하여 채널정지층(36)인 p+에서 불순물확산영역(34)인 n+로 흐르는 순방향 다이오드가 만들어져 유입된 전류가 화살표를 방향으로 흘러 접지(Vss)로 분산된다.When static electricity flows through the pad 10, the corrector stress causes a high voltage to be applied to the N-Well 40 through the n + impurity diffusion region, resulting in a breakdown effect between the N-Well 40 and the channel stop layer 36 that is p +. A forward diode is generated and flows from p +, which is the channel stop layer 36, to n +, which is the impurity diffusion region 34, so that the introduced current flows in the direction of the arrow and is distributed to ground Vss.
이때 N-Well(40)과 채널정지층(36)인 p+사이의 항복전압이 높아져 N-Well(40)의 전부위에 항복전압이 동일하게 분산되어 N-Well(40)의 경계면을 통과하게 됨으로서 전류패스의 전류밀도가 낮아지게 된다.At this time, the breakdown voltage between the N-Well 40 and p +, which is the channel stop layer 36, is increased, so that the breakdown voltage is uniformly distributed over the entirety of the N-Well 40 so as to pass through the boundary of the N-Well 40. The current density of the current path becomes low.
상기한 바와 같이 본 발명은 정전기가 유입되는 불순물확산영역사이에 웰을 형성하여 항복전압이 웰의 전부위에 걸리도록 함으로서 전류패스의 전류밀도를 낮게 할 수 있어 열화에 의한 소자의 손상을 방지할 수 있다는 이점이 있다.As described above, the present invention forms a well between impurity diffusion regions into which static electricity flows so that the breakdown voltage is applied to the entire top of the well, thereby lowering the current density of the current path, thereby preventing damage to the device due to deterioration. There is an advantage.
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| KR0171107B1 (en) * | 1995-05-02 | 1999-02-01 | 문정환 | Esd input protection circuit and its manufacturing method |
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