KR0171107B1 - Esd input protection circuit and its manufacturing method - Google Patents

Abstract

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an ESD input protection circuit and a method of manufacturing the same, and more particularly, to a field oxide film formed by surge voltage at a field edge of a first discharge transistor of an ESD protection circuit, which is an input protection circuit. A higher electric field is formed in the buried impurity layer than the field ion layer in the lower part of the field ion layer formed below the field oxide film of the field transistor so as to be suitable for solving the damage of the field transistor, thereby preventing the field oxide film edge portion from being damaged by the high electric field. In addition, the present invention relates to an ESD input protection circuit for forming a field transistor by adding a process step of forming a high concentration impurity layer in a process following formation of a field ion layer or in a process following formation of a field oxide layer to form such a buried impurity layer, and a method of manufacturing the same.

Description

ESD input protection circuit and manufacturing method

1 is a circuit diagram of an ESD input protection circuit.

2 is a cross-sectional view illustrating a structure of a first discharge transistor of a conventional ESD input protection circuit.

* Explanation of symbols for main parts of the drawings

DESCRIPTION OF SYMBOLS 1 Pad part 2 First transistor for discharge

3: second transistor for discharging 4: high concentration impurity resistance

5: input unit generator 10,20: P-well

11,21: field oxide film 12,22: field ion layer

13,14,24,25: high concentration impurity layer 23: buried impurity layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ESD input protection circuit and a method of manufacturing the same, and more particularly, to a field oxide film formed by surge voltage at a field edge of a first discharge transistor of an ESD protection circuit, which is an input protection circuit. The present invention relates to an ESD input protection circuit and a method of manufacturing the same, which are suitable for solving the damage of the circuit.

The basic component of the ESD input protection circuit, which is a kind of input protection circuit, is a first semiconducting transistor made of a bipolar transistor between the pad part 1 and the inverting element 5 of the input part as shown in FIG. 2), a second discharge transistor 3 made of a ground gate transistor, and a highly concentrated impurity resistor 4 formed of a high concentration impurity layer. The first discharge transistor 2 is an NPN-type bipolar transistor when the lower substrate is a P-type substrate or a P well, and is formed in a field transistor form. Here, the description will be based on the formation of the first discharge transistor on the P well.

Here, in the ESD input protection circuit, the N ⁺ active region is the N + resistor and the N + region on the pad side (when the field transistor is turned on due to the + voltage application to cause a bipolar action, the pad side N + region becomes the collector of the NPN bipolar transistor, The N + region, which is used as an N + resistor, also contributes to electrostatic discharge when the field transistor causes bipolar action. All N + active areas of the ESD protection circuit have a single drain structure without applying an LDD structure. If there is an N- area, heat is generated by the current flowing during the electrostatic discharge due to the large N-resistance. Heat causes junction destruction. In addition, the N + active region is also implanted with a high concentration of doped ion to reduce the N + resistance value.

In the ESD protection circuit, most discharge paths have the field ion layer 12 under the field oxide film 11 formed on the P well 10 as shown in FIG. 2, and have a high concentration on the P wells under the side of the field oxide film 11. N-type impurity layers 13 and 14 are formed, and each N-type impurity layer is formed by a field transistor, which is a first discharge transistor having a structure connected to a pad and a ground power source, and most of the static electricity is prevented by the bipolar action of the field transistor. To discharge. The initial static electricity introduced by the fast reaction is formed through the N + resistance, that is, the discharge path is formed in the ground gate transistor which is the second discharge transistor after the RC delay time. This is to discharge the initial ESD voltage from the ground gate transistor before the field transistor is turned on to prevent the destruction of the gate oxide film when the ESD voltage is applied to the gate side of the initial inverter of the input stage. When discharged from the ground gate transistor, the initial input static electricity discharges most of the static electricity by turning on the field transistor shortly after some time.

In this case, the discharge capacity of the field transistor is mainly related to the junction area and the width of the field transistor. In practice, however, ESD protection circuits cannot be as large in terms of chip size and pad arrangement and should be minimized. This causes problems with the discharge of a large amount of static electricity in small volumes.

It is pointed out as a problem of the prior art that a field ion implantation is performed under the field oxide film, so that a region having a higher impurity level than the lower P well is located, which is a different region in reverse bias between the N + region and the P well junction. The higher the amount of impurities, the narrower the depth of the depletion layer becomes and the stronger the electric field is, the lower the breakdown voltage is. In general, the junction characteristic is vulnerable to sub-defects at the gate edge, which acts as a source of junction leakage current when high voltage is applied.If a strong electric field is applied to the field edge at the time of electrostatic discharge, it is more susceptible to breakage than other parts. There is.

The present invention relates to an ESD input part protection circuit and a method of manufacturing the same for solving the problem of breakage of an edge part of a field transistor which is a first discharge transistor caused by a conventional structural problem.

The ESD input protection circuit according to the present invention includes a plurality of first discharge transistors formed of baripolar transistors on a semiconductor substrate, a plurality of resistors formed in an opposite conductivity type to a lower substrate, and a plurality of MOS transistors having a gate grounded. An ESD input protection circuit including a second discharge transistor and formed between a pad portion and an internal semiconductor element for discharging static electricity drawn from the outside through the pad portion, the semiconductor substrate or well being used as a base region; A field oxide film formed in an isolation region formed between the substrate or the wells, a high concentration impurity layer of a conductivity type opposite to the substrate or wells formed on the lower substrates on both sides of the field oxide film for emitter or collector electrodes, Formed to isolate the impurity layer under the field oxide layer Keen includes the substrate or a well and the ionic field of the same conductivity type, formed between the ionic field of the lower high-concentration impurity layer of impurities of the same conductivity type as said field ion sheath is doped at a high concentration impurity buried layer.

The method of manufacturing an ESD input protection circuit according to the present invention includes a plurality of first discharge transistors formed of baripolar transistors on a semiconductor substrate, a plurality of resistors formed in an opposite conductivity type to a lower substrate, and a MOS transistor with a gate grounded. A method of manufacturing an ESD input protection circuit comprising a plurality of second discharge transistors formed between the pad part and an internal semiconductor element for discharging static electricity drawn from the outside through the pad part, the method comprising: 1) a semiconductor substrate; Or implanting impurity ions of the same conductivity type as the substrate or well into a field region defined on the well to form a field ion layer, 2) forming a field isolation film in the field region, and 3) When a buried ion layer is formed by implanting impurity ions of the same conductivity type as the field ion layer By step and, 4) ion implanting impurities of the substrate or well in the opposite conductivity type to the substrate or welsang excluding the field separator includes the respective steps including the step of forming an electrode for an impurity layer.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 3, the structure of the field transistor of the ESD input protection circuit will be described below.

The field oxide film 21 is formed on the P well 20, the field ion layer 22 is formed under the P well 20, and the buried impurity layer 23 is formed under the field ion layer 22. Then, N-type high concentration impurity layers 24 and 25 are formed on the P well 20 at the lower side of the field oxide film 21.

The ESD input protection circuit of the present invention is a field transistor, which is a first discharge transistor having a structure in which the N-type impurity layers 24 and 25 are connected to a pad and a ground power source, and is mostly due to the bipolar action of the field transistor. To discharge the static electricity. Some fast reactions are applied to the initial static electricity introduced through the M + resistance, that is, after the RC delay time, to form a discharge path in the ground gate transistor, the second discharge transistor, which is used to convert the initial ESD voltage before the field transistor is turned on. The discharge from the transistor prevents the gate oxide from being destroyed when the ESD voltage is applied to the gate side of the inverter at the initial stage of the input stage. When discharged from the ground gate transistor, the initial input static electricity discharges most of the static electricity by turning on the field transistor shortly after some time.

In the structure of the field transistor which is the first discharge transistor, the buried impurity layer 23 formed below the field ion layer 22 of the field oxide layer 21 at a concentration higher than that of the field oxide layer 21 is a field ion layer when high voltage is applied. Compared with 22), a strong electric field is applied to prevent the edge portion of the field oxide film 21 from being damaged.

In addition, the present invention is a method of manufacturing an ESD transistor having such a first discharge transistor,

1) forming a field ion layer by implanting ions of the same conductivity type as the substrate or well into a field region defined on a semiconductor substrate or well;

2) implanting ions of the same conductivity type as the field ion layer in the field region to form a buried ion layer under the field ion layer;

3) forming a field isolation film in the field region;

4) A first discharging transistor is formed by implanting ions of opposite conductivity type as the substrate or well on the substrate or well except the field isolation film to form an impurity layer for the electrode.

At this time, if the substrate or the well type P, is a field ion sheath to BF ₂ ⁺ ion tens KeV, preferably by injection into the energy 60KeV to form a concentration of 3.0 × 10 ¹³ cm ^-3.

Further, by implanting BF ₂ ⁺ ions the ion sheath embedded in hundreds KeV, preferably of energy 120KeV to form a concentration of 1.0 × 10 ¹³ cm ^-3.

In another embodiment of the manufacturing method of the ESD input protection circuit of the present invention,

1) forming a field ion layer by implanting ions of the same conductivity type as the substrate or well into the field region defined on the semiconductor substrate or well;

2) forming a field isolation film in the field region;

3) forming a buried ion layer by implanting ions of the same conductivity type as the field ion layer in the field region;

4) The first discharging transistor is formed by performing each step of forming an impurity layer for an electrode by injecting ions of an opposite conductivity type to the substrate or well on the substrate or well except the field isolation film.

At this time, if the substrate or the well type P, is a field ion sheath to BF ₂ ⁺ ion tens KeV, preferably by injection into the energy 60KeV to form a concentration of 3.0 × 10 ¹³ cm ^-3.

Further, by implanting the ion B ⁺⁺ ion sheath embedded in hundreds KeV, preferably of energy 260KeV to form a concentration of 1.0 × 10 ¹³ cm ^-3.

The discharge path and the like will work in the same way, but it will be possible to reduce the discharge capacity and the size of the ESD protection circuit. If there is a buried P region away from the field region, the strong electric fields that have been applied just below the field will be caught in the region moved into the silicon, causing the fastest breakdown in this region. Therefore, damage at the field edge portion can be reduced.

Increasing the ESD breakdown voltage and improving the discharge power through the present invention will contribute to reducing the chip site in the integrated circuit by reducing the displacement of the ESD protection circuit portion occupying a significant area. It also increases the ESD breakdown voltage, which increases the reliability of the ESD.

Claims (7)

It comprises a plurality of first discharge transistor made of a bipolar transistor on the semiconductor substrate, a plurality of resistors formed in the opposite conductivity type to the lower substrate, and a plurality of second discharge transistor made of a MOS transistor with a gate grounded, An ESD input protection circuit formed between a pad portion and an internal semiconductor element for discharging static electricity drawn from the outside through the pad portion, the ESD input portion protection circuit comprising: a semiconductor substrate or well used as a base region, and an isolation region formed between the substrate or well Isolation between a high concentration impurity layer of opposite conductivity type to the field oxide film formed on the substrate, the substrate or the wells formed on both lower substrates of the field oxide film for emitter or collector electrodes, and the impurity layer under the field oxide film. Same conductivity as the substrate or well formed for And a first impurity transistor comprising a buried impurity layer formed by doping a highly doped impurity of the same conductivity type as said field ion layer between said field ion layer of said field ion layer and said high concentration impurity layer below said field ion layer. Input protection circuit. It comprises a plurality of first discharge transistor consisting of a bipolar transistor on the semiconductor substrate, a plurality of resistors formed in the opposite conductivity type to the lower substrate, and a plurality of second discharge transistor consisting of a MOS transistor with a gate grounded, A method for manufacturing an ESD input protection circuit formed between a pad part and an internal semiconductor element for discharging static electricity introduced from the outside through the pad part, the method comprising: 1) a semiconductor substrate or a well and a field region defined on a well; Implanting impurity ions of the same conductivity type to form a field ion layer, and 2) implanting impurity ions of the same conductivity type as the field ion layer into the field region to form a high concentration of buried ion layer under the field ion layer 3) forming a field isolation film in the field region; And forming an impurity layer of opposite conductivity type to the substrate or well on the substrate or well except for the field isolation layer, thereby forming the first discharge transistor. 3. The method of claim 2, in the case where the substrate or the well type P, ESD input to the field, characterized by forming the ionic concentration of the ion implantation to the BF ₂ ⁺ with energy of 60KeV, 3.0 × 10 ¹³ cm ^-3 Method of manufacturing a protection circuit. 3. The method of claim 2, in the case where the substrate or the well type P, ESD input to the embedded ionic characterized in that to form a concentration of the ion implantation to the BF ₂ ⁺ with energy of 120KeV, 5.0 × 10 ¹³ cm ^-3 Method of manufacturing a protection circuit. It comprises a plurality of first discharge transistor consisting of a bipolar transistor on the semiconductor substrate, a plurality of resistors formed in the opposite conductivity type to the lower substrate, and a plurality of second discharge transistor consisting of a MOS transistor with a gate grounded, A method for manufacturing an ESD input protection circuit formed between a pad part and an internal semiconductor element for discharging static electricity introduced from the outside through the pad part, the method comprising: 1) a semiconductor substrate or a well and a field region defined on a well; Implanting impurity ions of the same conductivity type to form a field ion layer; 2) forming a field isolation film in the field region; and 3) implanting impurity ions of the same conductivity type as the field ion layer in the field region. Forming a buried ion layer; and 4) the group except for the field isolation film. Or forming an impurity layer for an electrode by implanting an impurity layer opposite to the substrate or the well on the well to form an electrode impurity layer to form the first discharge transistor. Method of manufacturing a circuit. The method of claim 5, wherein in the case where the substrate or the well type P, ESD input to the field, characterized by forming the ionic concentration of the ion implantation to the BR ⁺ ₂ in the energy 60KeV, 3.0 × 10 ¹³ cm ^-3 Method of manufacturing a protection circuit. 7. The method of claim 5 or 6, wherein when the substrate or the well is P-type, the buried ion layer is ion implanted with B ⁺⁺ at an energy of 260 KeV to form a concentration of 1.0 x 10 ¹³ cm ^-3 . Method for manufacturing an ESD input protection circuit.