KR100218148B1 - Electrostatic electricity protection citcuit - Google Patents

Abstract

An object of the present invention is to provide an antistatic circuit of a semiconductor device that prevents damage to a portion to which an input pad is connected.

The present invention relates to each Vcc line, an input pad connected to an input pad, the first means for discharging positive static electricity by operating upon inflow of positive static electricity, and the portion and Vss connected to the input pad of the first means. Second means connected between the lines, the first means for discharging negative static electricity by operating upon inflow of negative static electricity, a voltage drop means connected to a portion to which the first means and the second means are connected, and the voltage drop means And third means for discharging secondary static electricity, wherein between the input pad and the first means and between the input pad and the second means, when a voltage of Vcc or more is input through the input pad, the voltage is dispersed. It is characterized by comprising a voltage distribution means to make.

Description

Antistatic Circuits of Semiconductor Devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an antistatic circuit of a semiconductor device, and more particularly, to an antistatic circuit of a semiconductor device capable of preventing overheating of a junction region contacted with a pad during operation of the antistatic circuit.

In general, electrostatic discharge (Electrostatic Discharge) is one of the factors that determine the reliability of the semiconductor chip, and occurs when handling the semiconductor chip or when mounted in the system, damage the chip. Therefore, in order to protect the semiconductor device from static electricity in the peripheral region of the semiconductor device, an antistatic circuit is provided.

A conventional antistatic circuit embedded in a semiconductor chip is shown in FIG.

Referring to FIG. 1, an antistatic circuit unit 2 is connected to the input pad 1, and an input buffer unit 3 is connected to an output terminal of the antistatic circuit unit 2.

Here, the electrostatic circuit unit 2 includes two first and second N-MOS transistors Q1 and Q2 connected in series to respective power lines Vcc and Vss and primarily discharging static electricity. Here, the gate electrodes of the first and second N-MOS transistors Q1 and Q2 are floating, the Vcc voltage is applied to the drain of the first N-MOS transistor Q1, and the source of the second N-MOS transistor Q2 is applied. Vss voltage is applied. At this time, the source of the first N-MOS transistor Q1 and the drain of the second N-MOS transistor Q2 are a common junction region (hereinafter referred to as node 1), and the node 1 has a resistor R for dropping a voltage and an input pad 1. ) Is connected. The resistor R is connected to a field transistor Q3 for secondary discharge of static electricity. The field transistor Q3 has a gate and a source grounded, and a drain thereof is connected to the input buffer unit 3.

In the antistatic circuit unit 2 as described above, when high voltage static electricity of Vcc or more is applied through the input pad 20, the first NMOS transistor Q1 is turned on to discharge static electricity through the Vcc line, and Vss When the following static electricity flows in, the second NMOS transistor Q2 is operated to discharge static electricity.

However, the reverse junction breakdown voltage is applied to the source region of the first NMOS transistor Q1 or the drain region of the second NMOS transistor Q2 connected to the input pad in the antistatic circuit as described above. Overheat. For this reason, the junction area | region was destroyed and the problem which the characteristic of a semiconductor element fell was produced.

Accordingly, an object of the present invention is to provide an antistatic circuit of a semiconductor device which disperses an electric field applied to a junction region when a positive static electricity flows into the input pad so that the junction region is not damaged.

1 is a diagram showing an antistatic circuit of a general semiconductor device.

2 is a diagram showing an antistatic circuit of a semiconductor device according to the present invention.

3 is a circuit diagram schematically showing the voltage spreading means of the present invention.

4 is a cross-sectional view in which the first means of the present invention is formed on a semiconductor substrate.

5 is an equivalent circuit diagram of the first means according to the present invention.

* Explanation of symbols for main parts of the drawings

11 input pad 12 first means

13 second means 14 voltage drop means

15: third means 16A, 16B: voltage dispersion means

In order to achieve the above object of the present invention, the present invention, the first means is connected to each Vcc line, the input pad, the first means for operating upon the inflow of positive static electricity to discharge positive static electricity, A second means connected between the portion connected to the input pad of the first means and the Vss line, the second means for discharging negative static electricity by operating upon inflow of negative static electricity, and a portion to which the first means and the second means are connected; And a third means connected to the voltage drop means connected to the voltage drop means, and to discharge the static electricity secondly, between the input pad and the first means and between the input pad and the second means. It is characterized in that it comprises a voltage dispersing means for dispersing the voltage when a voltage of Vcc or more is input therethrough.

According to the present invention, a voltage dispersing means is provided between an input pad and a MOS transistor to which an input pad is connected. When a voltage of Vcc or more is applied through the input pad, the voltage dispersing means is operated to connect the input pad to the MOS transistor. To prevent overheating of the junction region.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram showing an antistatic circuit of a semiconductor device according to the present invention, and FIG. 3 is a circuit diagram showing a voltage dispersion unit of the present invention.

In the present invention, when a high voltage static electricity flows from the input pad, in order to prevent the high voltage is caught in the junction region of the MOS transistors constituting the antistatic circuit, to partially dissipate the static electricity, first, the antistatic The circuit comprises first means 12 connected in series to respective power lines Vcc, Vss and primarily preventing static electricity, and second means 13, as shown in FIG. An input pad 11 and a voltage drop means 14 are connected to a point 12 connected to the second means 13. The charge lowering means 14 is provided with a third means 15 for secondaryly discharging static electricity.

The first means 12 and the second means 13 are N-MOS transistors with a gate floating thereon, and the voltage drop means is a resistor having a predetermined resistance value, and the third means 15 for secondaryly discharging static electricity. Is a field transistor with a gate and a source grounded.

At this time, the first and second voltage spreading means 16A, 16B are provided between the input pad 11 and the first means 12 and between the input pad 11 and the second means 13. Here, the first and second voltage spreading means 16A and 16B of the present invention have the same structure, and the configuration thereof will be described with reference to FIG.

As shown in FIG. 3, the voltage spreading means 16A and 16B include a fourth means 161 in which at least two MOS transistors in common with a gate and a drain are connected in series, and a first means of the fourth means 161. The fifth means 162 is provided between the fourth means 161 and the input pad 11 in order to prevent a sudden large voltage from being applied to the first MOS transistor. At this time, the fifth means 162 is a resistor having a predetermined resistance value, for example, about 80 to 200?.

In this case, the fourth means 161 adjusts the number n of the MOS transistors so that the voltage dispersion means is operated when the voltage spreading means is equal to or greater than the power supply voltage. That is, the voltage dispersing means 16A, 16B is operated when a voltage equal to the product of the number n of the transistors of the fourth means and the threshold voltage Vth of the MOS transistor is applied. Is adjusted to be greater than Vcc + 1 and less than the junction breakdown voltage. In the present invention, for example, six N-MOS transistors are provided in the fourth means 161. Therefore, the voltage dispersion means of the present invention operates when a voltage of about 6 x Vth flows in through the pad.

FIG. 4 is a cross-sectional view of the first means of FIG. 2 formed on a semiconductor substrate and formed by a known method of a gate electrode (not shown) on a P-type semiconductor substrate 21 provided with a field oxide film 22. N-type high concentration impurities are ion-implanted with the field oxide film 22 interposed therebetween to form source / drain regions 23A and 23B. At this time, a pad voltage is applied to the source region 23A, and a power supply voltage is applied to the drain region 23B.

The P type high concentration impurity region 24 is formed in the region spaced from the source region 23A and the field oxide film. This region is a substrate bias region for applying a predetermined voltage to the semiconductor substrate, and the voltage dispersion means of the present invention is preferably provided between the substrate bias region and the source region to which the pad is connected.

In the antistatic circuit of the semiconductor device of the present invention having such a configuration, the first and second voltage distributing means 16A and 16B are provided between the input pad 11 and the first and second means 12 and 13. Thus, when static electricity of a value larger than the power supply voltage, for example, the Vcc voltage is introduced, the first and second voltage dispersing means are operated so that the substrate region of the first and second means (base region during bipolar operation). As a result, some voltage is dispersed. At this time, since the voltage to be dispersed is larger than the Vcc voltage and smaller than the junction breakdown voltage, a voltage below the junction breakdown voltage is applied to the junction region of the first and second means to which the input pad is connected. Therefore, overheating is prevented in the junction region, and damage to the junction region is prevented.

FIG. 5 is an equivalent circuit diagram of the first means according to the present invention, which is shown as an equivalent circuit between the pad portion and the Vcc or Vss stage of FIG. 3, wherein the collector region of the bipolar transistor, that is, the junction region to which the pad is connected, Between the junction regions where Vcc or Vss is connected, n diodes D are provided as voltage dispersing means so that current flows in a bipolar forward bias at a voltage of (Vcc + 1) V where n diodes are turned on. Therefore, by these n diodes in the present invention, the heat Ic x V generated is reduced to a certain degree, thereby protecting the device.

As described in detail above, according to the present invention, a voltage dispersing means is provided between an input pad and a MOS transistor to which the input pad is connected, and when the Vcc voltage or more is applied through the input pad, the voltage dispersing means is operated. The overheating of the junction region of the MOS transistor to which the input pad is connected is prevented.

Therefore, damage to the junction region is prevented and the characteristics of the semiconductor element are improved.

Claims (10)

A connection between each Vcc line and an input pad, the first means for discharging positive static electricity by operating upon the introduction of positive static electricity, and the portion connected to the input pad of the first means, and the Vss line. Second means for discharging negative static electricity by operating upon inflow of negative static electricity, voltage drop means connected to a portion to which the first means and the second means are connected, and voltage drop means, A third means for discharging static electricity secondly, wherein said voltage dispersing means distributes the voltage when a voltage of Vcc or more is input through the input pad between the input pad and the first means and between the input pad and the second means. An antistatic circuit of a semiconductor device, characterized in that it comprises a. The antistatic circuit of a semiconductor device according to claim 1, wherein the first means and the second means are N-MOS transistors with a gate floating thereon. The method of claim 1, wherein the voltage spreading means comprises: a fourth means in which at least two or more MOS transistors in common with a gate and a drain are connected in series, and to prevent a sudden large voltage from being applied to the first MOS transistor of the fourth means. And a fifth means between the fourth means and the input pad. 4. The antistatic circuit of claim 3, wherein the fifth means is a resistor. The antistatic circuit of claim 4, wherein the resistance has a resistance of about 80 to 200 Ω. 4. The voltage distributing means according to claim 3, wherein the voltage dispersing means operates when a voltage larger than the product of the number n of the MOS transistors of the fourth means and the threshold voltage Vth of the MOS transistors of the fourth means flows. An antistatic circuit of a semiconductor element. 7. The semiconductor device according to claim 3 or 6, wherein the voltage dispersion means is turned on when a value greater than Vcc + 1 (V) and less than a junction breakdown voltage of the first or second means is input. Of antistatic circuit. 4. The antistatic circuit according to claim 1 or 3, wherein the voltage spreading means is connected between an input pad and a portion to which the substrate bias of the first and second means is applied. The antistatic circuit of a semiconductor device according to claim 1, wherein said voltage drop means is a resistor. The antistatic circuit of a semiconductor device according to claim 1, wherein said third means is a field transistor.