KR100520142B1 - A transistor of a high threshold voltage - Google Patents
A transistor of a high threshold voltage Download PDFInfo
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- KR100520142B1 KR100520142B1 KR10-1999-0061862A KR19990061862A KR100520142B1 KR 100520142 B1 KR100520142 B1 KR 100520142B1 KR 19990061862 A KR19990061862 A KR 19990061862A KR 100520142 B1 KR100520142 B1 KR 100520142B1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
Abstract
본 발명은 높은 문턱전압 트랜지스터에 관한 것으로, The present invention relates to a high threshold voltage transistor,
패키지 상태에서 리페어 공정을 가능하게 하는 높은 문턱전압 트랜지스터에 있어서, 제1도전형의 반도체기판과, 상기 반도체기판 상부에 구비되는 게이트전극과, 상기 제1도전형의 반도체기판에 활성영역을 정의하는 소자분리막과, 상기 게이트전극 하측의 소자분리막 하부에 구비되는 제1도전형 또는 제2도전형 웰과, 상기 게이트전극 양측으로 구비되는 제2도전형 또는 제1도전형의 웰과, 상기 제2도전형 및 제1도전형 웰 내부에 구비되는 제2도전형 또는 제1도전형의 고농도 불순물 접합영역과, 상기 제1도전형 또는 제2도전형 웰에 내부에 구비되는 제1도전형 또는 제2도전형 채널을 포함되어 전압인가시 소자의 특성열화를 방지하여 반도체소자의 수율을 향상시킬 수 있는 기술이다. In a high threshold voltage transistor that enables a repair process in a packaged state, an active region is defined on a first conductive semiconductor substrate, a gate electrode provided on the semiconductor substrate, and a first conductive semiconductor substrate. A device isolation film, a first conductive type or a second conductive type well provided under the device isolation film under the gate electrode, a second conductive type or first conductive type well provided on both sides of the gate electrode, and the second High concentration impurity junction regions of the second conductive type or the first conductive type, which are provided in the conductive and first conductive type wells, and the first conductive type or the first conductive type or the second conductive type wells provided in the first conductive type or the second conductive type well. It is a technology that can improve the yield of semiconductor devices by preventing the deterioration of the characteristics of the device when a voltage is applied, including a two-conducting channel.
Description
본 발명은 높은 문턱전압 트랜지스터에 관한 것으로, 특히 고전압에서 드레인 접합영역의 브레이크다운 전압 ( breakdown voltage ) 에 안정적으로 동작할 수 있는 트랜지스터를 구현하는 기술에 관한 것이다. The present invention relates to a high threshold voltage transistor, and more particularly to a technique for implementing a transistor that can operate stably at the breakdown voltage (draindown voltage) of the drain junction region at high voltage.
일반적으로, 전 공정을 다 거친 웨이퍼는 바로 테스트를 하여 리페어 ( repair ) 를 하게 된다. In general, wafers that have been through the entire process are tested and repaired immediately.
그러나, 패키지가 되고 나면 리페어가 불가능해 진다. 이렇게 패키지를 하고 난 후에 페일이 나는 칩이 전체의 5 퍼센트 정도 된다. However, once packaged, repair is impossible. After this package, the failing chip is about 5 percent of the total.
그리하여, 요즘은 패키지를 하고 난 후에도 리페어가 가능하도록 안티 퓨즈 ( anti-fuse ) 를 사용하고 있다. Thus, these days, anti-fuse is used to repair even after package.
그러나, 이것은 기존의 메모리 칩에서 사용하지 않던 고전압을 필요로 하게 된다. However, this requires a high voltage that is not used in conventional memory chips.
그래서, 기존의 주변회로부의 트랜지스터 드레인에 걸리던 전압보다 훨씬 높은 전압이 걸리게 된다. Therefore, a voltage much higher than that of the transistor drain of the existing peripheral circuit part is applied.
기존에 사용하는 트랜지스터는, 웰을 구성하고 그 웰에 트랜지스터 채널용으로 이온주입을 다시 실시한다. 이렇게 형성된 트랜지스터는 채널 농도가 높기 때문에 문턱전압이 대략 1 볼트 근방이다.Conventionally used transistors constitute wells and are ion implanted into the wells again for transistor channels. The transistor formed in this way has a high channel concentration, and thus the threshold voltage is about 1 volt.
그런데 높은 문턱전압 트랜지스터를 위해 마스크 공정을 추가하게 되면 비용 증가뿐만아니라 프로세스 시간도 증가하기 때문에 양산에는 적용할 수 없다. However, the addition of a mask process for high threshold voltage transistors not only increases the cost but also increases the process time, so it is not applicable to mass production.
그리고, 다른 일반적인 트랜지스터 때문에 채널쪽 농도를 마음대로 바꿀수가 없다.And, because of other common transistors, the channel side concentration cannot be changed at will.
상기한 바와같이 종래기술에 따른 반도체소자의 형성방법은, 안티 퓨즈 회로를 사용할때 고전압으로 인하여 트랜지스터의 특성이 열화되고 이를 해결하기 위하여 추가되는 마스크 공정시 공정시간이 증가되어 반도체소자의 생산성을 저하시키는 문제점이 있다. As described above, in the method of forming a semiconductor device according to the related art, when the anti-fuse circuit is used, the characteristics of the transistor are deteriorated due to the high voltage and the process time is increased during the additional mask process to solve the problem, thereby reducing the productivity of the semiconductor device. There is a problem.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 높은 문턱전압 트랜지스터를 구현할 수 있도록 MOS 트랜지스터의 소오스/드레인 접합영역을 소오스/드레인 접합영역과 같은 도전형 웰로 감싸도록 형성하여 반도체소자의 특성 열화를 방지할 수 있는 높은 문턱전압 트랜지스터를 제공하는데 그 목적이 있다. In order to solve the above problems of the prior art, the semiconductor device is formed so as to surround the source / drain junction region of the MOS transistor with a conductive well such as a source / drain junction region so as to realize a high threshold voltage transistor. The purpose is to provide a high threshold voltage transistor that can prevent the
이상의 목적을 달성하기 위해 본 발명에 따른 높은 문턱전압 트랜지스터는, 반도체기판과,상기 반도체기판에서 형성될 트랜지스터의 채널 영역으로 예정된 부분 상에 구비되는 소자분리막과, 상기 소자분리막 하부에 구비되어 채널로 사용되는 제1도전형 웰과, 상기 채널로 사용되는 제1도전형 웰 양측의 반도체기판에 구비되는 제2도전형 웰과,상기 소자분리막 상부에 구비되는 게이트전극과,상기 제2도전형 웰 내부의 반도체기판에 구비되는 제2도전형의 고농도 불순물 접합영역을 포함하는 것을 특징으로 한다. 또한 본 발명의 다른 특징은, 반도체기판과,상기 반도체기판에서 트랜지스터로 예정되어있는 부분에 형성되어있는 제1도전형 웰과, 상기 제1도전형 웰이 형성된 반도체기판에서 형성될 트랜지스터의 채널 영역으로 예정된 부분 상에 구비되는 소자분리막과, 상기 소자분리막 양측의 반도체기판에 구비되는 제2도전형 웰과,상기 소자분리막 상부에 구비되는 게이트전극과,상기 제2도전형 웰 내부의 반도체기판에 구비되는 제2도전형의 고농도 불순물 접합영역을 포함하는 것을 특징으로 한다. 한편, 이상의 목적을 달성하기 위한 본 발명의 원리는,In order to achieve the above object, the high threshold voltage transistor according to the present invention includes a semiconductor substrate, a device isolation layer provided on a portion of the semiconductor substrate to be formed as a channel region of the transistor to be formed, and a lower portion of the device isolation layer provided in a channel. A first conductive well used, a second conductive well provided on a semiconductor substrate on both sides of the first conductive well used as the channel, a gate electrode provided on the device isolation layer, and the second conductive well And a high concentration impurity junction region of the second conductivity type provided in the semiconductor substrate therein. In addition, another feature of the present invention is a semiconductor substrate, a first conductive well formed in a portion of the semiconductor substrate that is intended as a transistor, and a channel region of a transistor to be formed in the semiconductor substrate on which the first conductive well is formed. A device isolation film provided on a predetermined portion, a second conductive well provided on semiconductor substrates on both sides of the device isolation film, a gate electrode provided on the device isolation film, and a semiconductor substrate inside the second conductive well. It is characterized in that it comprises a high concentration impurity junction region of the second conductivity type provided. On the other hand, the principle of the present invention for achieving the above object,
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기존의 채널 도핑 농도에 비해 낮은 웰 도핑 농도로 인하여 채널 저항이 증가되어 문턱전압이 훨씬 높아진 2∼3 볼트 대로 제어할 수 있도록 하기 위하여,In order to be able to control with 2 ~ 3 volts because the channel resistance is increased due to the low well doping concentration compared to the existing channel doping concentration, the threshold voltage is much higher.
NMOS 높은 문턱전압 트랜지스터의 경우, 채널을 피웰로 사용하고, 소오스/드레인 접합영역을 엔웰로 감싼 고농도의 엔형 불순물 접합영역으로 형성하며,In the case of an NMOS high threshold voltage transistor, a channel is used as a pewell, and a source / drain junction region is formed as a high concentration of en-type impurity junction region wrapped with an enwell,
PMOS 높은 문턱전압 트랜지스터의 경우, 채널을 엔웰로 사용하고, 소오스/드레인 접합영역을 피웰로 감싼 고농도의 피형 불순물 접합영역으로 형성하는 것이다. In the case of a PMOS high threshold voltage transistor, a channel is used as an enwell, and a source / drain junction region is formed into a high concentration of the impurity junction region wrapped with a pewell.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 5 는 본 발명의 제1실시예 내지 제5실시예에 따른 높은 문턱전압 트랜지스터를 도시한 단면도로서, 주변회로부에 형성되는 안티 퓨즈 회로 사용시 고전압에 견딜 수 있는 트랜지스터를 형성하는 것이다.1 to 5 are cross-sectional views illustrating a high threshold voltage transistor according to the first to fifth embodiments of the present invention to form a transistor that can withstand a high voltage when using an anti-fuse circuit formed in a peripheral circuit portion.
도 1 은 본 발명의 제1실시예로서, 피형 반도체기판(11)에 활성영역을 정의하는 소자분리막(13)이 형성되고, 상기 소자분리막(13) 양측으로 엔웰(17)이 형성되고, 상기 소자분리막(13) 하측으로 피웰(15)이 형성되고, 상기 소자분리막(13) 상측에 게이트전극(21)이 구비되며, 상기 엔웰(17) 상측에 고농도의 엔형 불순물 접합영역(19)이 형성된 NMOS 이다.FIG. 1 illustrates a device isolation film 13 defining an active region in a semiconductor substrate 11, and an enwell 17 formed on both sides of the device isolation film 13. A pwell 15 is formed below the device isolation layer 13, a gate electrode 21 is provided above the device isolation layer 13, and a high concentration of Y-type impurity junction region 19 is formed above the enwell 17. NMOS.
상기 NMOS 를 형성하는 공정순서는 다음과 같다.The process sequence for forming the NMOS is as follows.
먼저, 반도체기판(11) 상의 활성영역을 정의하는 소자분리막(13)을 형성한다.First, an isolation layer 13 is formed to define an active region on the semiconductor substrate 11.
그리고, 상기 활성영역에 엔형 불순물을 이온주입하여 엔웰(17)을 형성하고 상기 소자분리막(13) 하부로 피형 불순물을 이온주입하여 피웰(15)을 형성한다. In addition, an enwell 17 is formed by ion implantation of an en-type impurity into the active region, and an implanted impurity is implanted into the lower portion of the device isolation layer 13 to form a pewell 15.
그리고, 상기 엔엘(17) 상측의 반도체기판(11) 표면에 고농도의 엔형 불순물을 이온주입하여 엔형 불순물 접합영역(19)을 형성한다. A high concentration of Y-type impurities is ion-implanted on the surface of the semiconductor substrate 11 on the upper side of the EN 17 to form the Y-type impurity junction region 19.
그리고, 상기 소자분리막(13) 상부에 게이트전극(21)을 형성함으로써 NMOS 를 형성한다. 이때, 상기 게이트전극(21)은 폴리실리콘이나 폴리사이드 또는 이와 유사한 특성을 갖는 도전체로 형성한다. An NMOS is formed by forming the gate electrode 21 on the device isolation layer 13. In this case, the gate electrode 21 is made of polysilicon, polyside, or a conductor having similar characteristics.
여기서, 상기 피웰(15)이 NMOS 트랜지스터의 채널로 사용된다. Here, the pewell 15 is used as a channel of the NMOS transistor.
도 2 는 본 발명의 제2실시예로서, 피형 반도체기판(31)에 활성영역을 정의하는 소자분리막(33)이 형성되고, 상기 소자분리막(33) 양측으로 피웰(37)이 형성되고, 상기 소자분리막(33) 하측으로 엔웰(35)이 형성되고, 상기 소자분리막(33) 상측에 게이트전극(41)이 구비되며, 상기 피웰(37) 상측에 고농도의 피형 불순물 접합영역(39)이 형성된 PMOS 이다. FIG. 2 shows a second embodiment of the present invention, in which a device isolation film 33 defining an active region is formed on a to-be-shaped semiconductor substrate 31, and a pewell 37 is formed on both sides of the device isolation film 33. An enwell 35 is formed below the device isolation layer 33, a gate electrode 41 is provided above the device isolation layer 33, and a high concentration of the impurity junction region 39 is formed above the pewell 37. PMOS.
상기 PMOS 를 형성하는 공정순서는 다음과 같다.The process sequence for forming the PMOS is as follows.
먼저, 반도체기판(31) 상의 활성영역을 정의하는 소자분리막(33)을 형성한다. First, an isolation layer 33 defining an active region on the semiconductor substrate 31 is formed.
그리고, 상기 활성영역에 피형 불순물을 이온주입하여 피웰(37)을 형성하고 상기 소자분리막(33) 하부로 엔형 불순물을 이온주입하여 엔웰(35)을 형성한다. Then, the pwell 37 is formed by ion implanting the impurity into the active region, and the enwell 35 is formed by ion implanting the n-type impurity under the device isolation layer 33.
그리고, 상기 피엘(37) 상측의 반도체기판(31) 표면에 고농도의 피형 불순물을 이온주입하여 피형 불순물 접합영역(39)을 형성한다. Then, a high concentration of impurity impurities are implanted into the surface of the semiconductor substrate 31 above the PEL 37 to form the impurity junction region 39.
그리고, 상기 소자분리막(33) 상부에 게이트전극(41)을 형성함으로써 PMOS 를 형성한다. 이때, 상기 게이트전극(21)은 폴리실리콘이나 폴리사이드 또는 이와 유사한 특성을 갖는 도전체로 형성한다. The PMOS is formed by forming the gate electrode 41 on the device isolation layer 33. In this case, the gate electrode 21 is made of polysilicon, polyside, or a conductor having similar characteristics.
여기서, 상기 엔웰(35)이 PMOS 트랜지스터의 채널로 사용된다. Herein, the enwell 35 is used as a channel of the PMOS transistor.
도 3 은 본 발명의 제3실시예로서, 피형 반도체기판(51)에 활성영역을 정의하는 소자분리막(53)이 형성되고, PMOS 가 형성될 부분의 반도체기판(51)에 엔알웰(55)이 형성되고, 상기 소오스/드레인 접합영역에 알웰(57)이 형성되고, 상기 알웰(57)의 반도체기판(51) 표면에 고농도의 피형 불순물 접합영역(59)이 구비되고, 상기 소자분리막(53) 상부에 게이트전극(61)이 형성된 구조의 PMOS 이다. FIG. 3 shows a third embodiment of the present invention, in which a device isolation film 53 defining an active region is formed on an implanted semiconductor substrate 51, and an N-well 55 is formed on a semiconductor substrate 51 in a portion where a PMOS is to be formed. An Alwell 57 is formed in the source / drain junction region, a high concentration of the impurity junction region 59 is formed on the surface of the semiconductor substrate 51 of the Alwell 57, and the device isolation layer 53 is formed. A PMOS having a gate electrode 61 formed thereon.
상기 PMOS 를 형성하는 공정순서는 다음과 같다.The process sequence for forming the PMOS is as follows.
먼저, 반도체기판(51) 상의 활성영역을 정의하는 소자분리막(53)을 형성한다.First, an isolation layer 53 is formed to define an active region on the semiconductor substrate 51.
그리고, 상기 활성영역 엔알웰(55)을 형성한다. 이때, 상기 엔알웰(55)은 후속공정으로 형성되는 알웰(57)을 포함하는 엔웰을 말한다. Then, the active region enellwell 55 is formed. In this case, the enell 55 refers to an enwell including an alwell 57 formed in a subsequent process.
그리고, 상기 PMOS 의 소오스/드레인 접합영역으로 예정된 부분에 피형 불순물을 이온주입하여 알웰(57)을 형성한다.Then, the Alwell 57 is formed by ion implanting an impurity in a portion defined as the source / drain junction region of the PMOS.
그리고, 상기 알웰(57) 상측의 반도체기판(51) 표면에 고농도의 피형 불순물 접합영역(59)을 형성한다.In addition, a high concentration of the impurity junction region 59 is formed on the surface of the semiconductor substrate 51 above the alwell 57.
그리고, 상기 엔알웰(55) 중앙부에 위치한 소자분리막(53) 상측에 게이트전극(61)을 형성한다.In addition, the gate electrode 61 is formed on the device isolation layer 53 positioned in the center of the N-well 55.
이때, 상기 게이트전극(61)은 전체표면상부에 게이트전극용 도전체로 폴리실리콘이나 폴리사이드 또는 이와 유사한 특성을 갖는 도전체를 증착하고 이를 패터닝하여 형성한다.In this case, the gate electrode 61 is formed by depositing and patterning a conductor having polysilicon, polyside, or the like as a conductor for the gate electrode on the entire surface.
여기서, 상기 PMOS 트랜지스터의 채널은 상기 상기 엔알웰(55) 중앙부에 위치한 소자분리막(53) 하측 엔알웰(55)에 형성된다. Here, the channel of the PMOS transistor is formed in the n-well 55 under the device isolation layer 53 positioned in the center of the N-well 55.
도 4 는 본 발명의 제4실시예로서, 피형 반도체기판(71)에 활성영역을 정의하는 소자분리막(73)이 형성되고, PMOS 트랜지스터가 형성될 영역에 엔알웰(75)이 형성되고, 상기 소오스/드레인 접합영역에 알웰(79)이 형성되고, 상기 알웰(79)의 반도체기판(71) 표면에 고농도의 피형 불순물 접합영역(81)이 구비되고, 게이트전극의 예정된 영역 하측의 채널 영역이 엔알웰과 피형 반도체기판이 혼합된 피채널(77)이 구비되며, 상기 소자분리막(73) 상부에 게이트전극(83)이 형성된 구조의 PMOS 이다. FIG. 4 is a fourth embodiment of the present invention, in which a device isolation film 73 defining an active region is formed in an implanted semiconductor substrate 71, and an N-well 75 is formed in a region where a PMOS transistor is to be formed. An alwell 79 is formed in the source / drain junction region, a high concentration of the impurity junction region 81 is formed on the surface of the semiconductor substrate 71 of the alwell 79, and a channel region under the predetermined region of the gate electrode is formed. An N-well and an implanted semiconductor substrate are provided with a mixed channel 77, and a PMOS structure in which a gate electrode 83 is formed on the isolation layer 73.
이때, 상기 혼합된 피채널(77)은 상기 소자분리막(73) 하부로 부터 상기 엔알웰(75)을 통과하여 상기 반도체기판(71)에 걸쳐 형성된다.In this case, the mixed channel 77 is formed over the semiconductor substrate 71 by passing through the N-well 75 from the lower portion of the device isolation layer 73.
여기서, 도 4a 는 본 발명의 제4실시예에 따른 높은 문턱전압 트랜지스터의 단면도이고, 도 4b 는 상기 도 4a 의 혼합된 피채널(77)을 도시한 평면도로서, 상기 혼합된 피채널(77)은 엔알웰과 피형 반도체기판을 서로 이웃하지 않도록 메쉬구조로 형성하여 채널의 불순물 농도를 감소시킴으로써 공핍영역을 증가시켜 소자의 구동시 고전압을 사용할 수 있도록 한다. 이때, 상기 혼합된 피채널(77)은 메쉬구조의 마스크를 이용한 임플란트 공정으로 형성할 수 있다.상기 PMOS 를 형성하는 공정순서는 다음과 같다.4A is a cross-sectional view of a high threshold voltage transistor according to a fourth embodiment of the present invention, and FIG. 4B is a plan view illustrating the mixed channel 77 of FIG. 4A. The N-well and the shaped semiconductor substrate are formed in a mesh structure so as not to be adjacent to each other to reduce the impurity concentration of the channel, thereby increasing the depletion region so that high voltage can be used when driving the device. In this case, the mixed channel 77 may be formed by an implant process using a mask having a mesh structure. The process sequence for forming the PMOS is as follows.
삭제delete
먼저, 반도체기판(71) 상의 활성영역을 정의하는 소자분리막(73)을 형성한다.First, an isolation layer 73 defining an active region on the semiconductor substrate 71 is formed.
그리고, 상기 활성영역 피형과 엔형의 불순물을 이온주입하여 엔알웰(75)을 형성하되, PMOS 의 게이트전극으로 예정된 부분 하측에 엔알웰(75)과 피형 반도체기판(71)이 혼합된 피채널(77)을 형성한다. 여기서, 상기 혼합된 피채널(77)은 피형 반도체기판(71)과 엔알웰(75)을 형성하는 엔형 불순물이 각각 서로 이웃하지 않도록 메쉬 형태로 배열된 평면구조로 형성된 것이다. In addition, an N-well 75 is formed by ion implantation of the active region P-type and N-type impurities, and an N-well 75 and a P-type semiconductor substrate 71 are mixed under a predetermined portion of the PMOS gate electrode. 77). Here, the mixed channel 77 is formed in a planar structure arranged in a mesh so that the n-type impurities forming the to-be-shaped semiconductor substrate 71 and the N-well 75 are not adjacent to each other.
그리고, 상기 소오스/드레인 접합영역으로 예정된 부분에 피형 불순물을 이온주입하여 알웰(79)을 형성하고, 그 상측인 반도체기판(71) 표면에 고농도의 피형 불순물 접합영역(81)을 형성한다.Then, the Alwell 79 is formed by ion implanting the impurity into the portion predetermined as the source / drain junction region, and a high concentration of the impurity junction region 81 is formed on the surface of the semiconductor substrate 71 on the upper side thereof.
그리고, 상기 반도체기판(71)의 전체표면상부에 게이트전극용 도전체를 일정두께 형성하고 이를 패터닝하여 게이트전극(83)을 형성한다.In addition, a gate electrode conductor is formed on the entire surface of the semiconductor substrate 71 at a predetermined thickness to pattern the gate electrode 83.
도 5 는 본 발명의 제5실시예로서, 5 is a fifth embodiment of the present invention.
피형 반도체기판(91)에 활성영역을 정의하는 소자분리막(93)이 형성되고, 소오스/드레인 접합영역으로 예정된 영역에 알웰(95)이 형성되고, 상기 알웰(95)의 반도체기판(91) 표면에 고농도의 피형 불순물 접합영역(97)이 구비되고, 게이트전극으로 예정된 영역 하측의 채널 영역이 피형 반도체기판(91)으로 형성되고, 상기 소자분리막(93) 상부에 게이트전극(93)이 형성된 구조의 PMOS 이다. An isolation layer 93 defining an active region is formed on the semiconductor semiconductor 91, and an alwell 95 is formed in a region defined as a source / drain junction region, and the surface of the semiconductor substrate 91 of the alwell 95 is formed. A high concentration of the dopant impurity junction region 97 is provided in the structure, and a channel region under the region intended as the gate electrode is formed of the semiconductor substrate 91 and the gate electrode 93 is formed on the device isolation layer 93. Is PMOS.
상기 PMOS 를 형성하는 공정순서는 다음과 같다.The process sequence for forming the PMOS is as follows.
먼저, 반도체기판(91) 상의 활성영역을 정의하는 소자분리막(93)을 형성한다. First, an isolation layer 93 is formed to define an active region on the semiconductor substrate 91.
그리고, 상기 소자분리막(93)을 마스크로하여 상기 반도체기판(91)에 피형 불순물을 이온주입하여 알웰(95)을 형성한다. An Alwell 95 is formed by ion implanting a dopant impurity into the semiconductor substrate 91 using the device isolation layer 93 as a mask.
그리고, 상기 알웰(95) 상측의 반도체기판(91) 표면에 고농도의 피형 불순물을 이온주입하여 고농도의 피형 불순물 접합영역(97)을 형성한다. In addition, a high concentration of the dopant impurity junction region 97 is formed by ion implantation of a high concentration of the dopant impurity on the surface of the semiconductor substrate 91 above the alwell 95.
그 다음, 상기 소자분리막(93) 상부에 게이트전극(99)을 형성한다. Next, a gate electrode 99 is formed on the device isolation layer 93.
이때, 상기 게이트전극(99)은 전체표면상부에 게이트전극용 도전체인 폴리실리콘, 폴리사이드 또는 이와 유사한 특성을 갖는 도전체를 일정두께 형성하고 이를 패터닝하여 형성한다. In this case, the gate electrode 99 is formed by forming a predetermined thickness and patterning a conductor having a property such as polysilicon, polyside, or the like for the gate electrode on the entire surface.
여기서, 상기 PMOS 의 채널은 상기 게이트전극(99) 하부의 피형 반도체기판(91)에 형성된다. Here, the channel of the PMOS is formed on the to-be-shaped semiconductor substrate 91 under the gate electrode 99.
이상에서 설명한 바와같이 본 발명에 따른 높은 문턱전압 트랜지스터는, 전압 인가시 브레이크다운 전압이 증가되고 그로인하여 고전압을 필요로 하는 안티 퓨즈 회로의 이용을 가능하고 페키지 상태에서도 리페어 공정을 용이하게 함으로써 반도체소자의 수율을 향상시킬 수 있는 효과를 제공한다.As described above, the high threshold voltage transistor according to the present invention increases the breakdown voltage when the voltage is applied, thereby enabling the use of an anti-fuse circuit requiring a high voltage and facilitating the repair process even in a package state. It provides an effect that can improve the yield.
도 1 내지 도 5 는 본 발명의 제1실시예 내지 제5실시예에 따른 높은 문턱전압 트랜지스터를 도시한 단면도 및 평면도.1 to 5 are cross-sectional views and plan views showing a high threshold voltage transistor according to the first to fifth embodiments of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11,31,51,71,91 : 반도체기판 13,33,53,73,93 : 소자분리막11,31,51,71,91: semiconductor substrate 13,33,53,73,93: device isolation film
15,37,79 : 피웰 ( p-well ) 17,35 : 엔웰 ( n-well )15,37,79: p-well 17,35: n-well
19 : 엔형 불순물 접합영역 21,41,61,81,99 : 게이트전극19: Y-type impurity junction region 21,41,61,81,99: gate electrode
39,59,81,97 : 피형 불순물 접합영역 55,75, : 엔알웰 ( nr-well )39,59,81,97: type impurity junction region 55,75,: nr-well
57,95 : 알웰 ( r-well ) 57,95 r-well
77 : 엔알웰과 피형 반도체기판의 혼합된 피채널 ( mixed p-ch ) 77: mixed p-ch of ENwell and the semiconductor substrate
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62166562A (en) * | 1986-01-20 | 1987-07-23 | Fujitsu Ltd | Manufacture of image sensor |
| JPS6367772A (en) * | 1986-09-09 | 1988-03-26 | Fuji Xerox Co Ltd | Image sensor and manufacture of same |
| JPH0613598A (en) * | 1992-06-24 | 1994-01-21 | Fuji Xerox Co Ltd | Manufacture of transparent electrode for image sensor |
| JPH0653470A (en) * | 1992-07-27 | 1994-02-25 | Fuji Xerox Co Ltd | Image sensor and fabrication thereof |
| JPH09330930A (en) * | 1996-06-07 | 1997-12-22 | Nippon Steel Corp | Manufacture of semiconductor device |
| KR19990062217A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Field transistor structure of semiconductor device |
-
1999
- 1999-12-24 KR KR10-1999-0061862A patent/KR100520142B1/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62166562A (en) * | 1986-01-20 | 1987-07-23 | Fujitsu Ltd | Manufacture of image sensor |
| JPS6367772A (en) * | 1986-09-09 | 1988-03-26 | Fuji Xerox Co Ltd | Image sensor and manufacture of same |
| JPH0613598A (en) * | 1992-06-24 | 1994-01-21 | Fuji Xerox Co Ltd | Manufacture of transparent electrode for image sensor |
| JPH0653470A (en) * | 1992-07-27 | 1994-02-25 | Fuji Xerox Co Ltd | Image sensor and fabrication thereof |
| JPH09330930A (en) * | 1996-06-07 | 1997-12-22 | Nippon Steel Corp | Manufacture of semiconductor device |
| KR19990062217A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Field transistor structure of semiconductor device |
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