KR100263063B1 - Method of fabricating cmos transistor - Google Patents

Abstract

PURPOSE: A method for fabricating a CMOS transistor is provided to simplify a fabrication process, and to obtain a desired threshold voltage of each PMOS transistor by assuring a junction overlap region sufficiently of the PMOS transistor as adopting an LDD(Lightly Doped Drain) junction structure. CONSTITUTION: According to the method of fabricating a PMOS transistor and an NMOS transistor on a P type silicon substrate(10), a gate(50) of the NMOS transistor is formed on the substrate and a gate(51) of the PMOS transistor is formed in an N-well(20). Then, an N-type impurity is lightly implanted to a drain and source region(30,31,32,33) of the transistors to form an LDD(Lightly Doped Drain). The first and the second insulation film(60,65) are deposited on an upper part of the gates and the ion-implanted regions. And, after forming a compound spacer(64) comprising the first and the second insulation film on a side wall of the gate of the NMOS transistor by covering the PMOS transistor and etching back the region of the NMOS transistor, an N-type impurity is heavily implanted to form an LDD of the NMOS transistor. Then, after forming a spacer(64) comprising the first insulation film on a side wall of the gate of the PMOS transistor by covering the region of the NMOS transistor and etching back the first insulation film in the region of the PMOS transistor, a P-type impurity is heavily implanted to form an LDD of the PMOS transistor. Thus, a transistor is completed where the sizes of junction overlap regions are different according to the width of the spacers, by opening the region of the NMOS transistor and performing a thermal annealing.

Description

Manufacturing Method of SeaMOS Transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a CMOS transistor, each of which can obtain desired threshold voltage values for the transistors.

A peripheral circuit for driving a semiconductor memory device is generally composed of a switching element composed of a transistor, a capacitor, and a resistor. As the switch element located in the peripheral circuit, a CMOS transistor having a N-type transistor and an MOS transistor together on the same substrate is used more than a single N-type transistor or a MOS transistor. This is because the output logic level, power dissipation, transition time, or preage characteristics are relatively good. A CMOS transistor having such an advantage is typically an N-type transistor having an N-type source / drain region of high concentration on a p-type bulk and a gate electrode formed through a gate insulating film on a channel, and an N-type transistor. A bulk MOS transistor having a high concentration source / drain region on the bulk and a gate electrode formed through a gate insulating film on the channel is formed.

CMOS transistors in peripheral circuits of nonvolatile memory devices, such as electrically programmable and erasable NOR flash memories, must have sufficient operating characteristics to withstand high voltages (about 10 volts) during program or erase operations. . Therefore, in the case of manufacturing CMOS transistors using the recent sub micron design rule, a lightly doped drain (LDD) junction structure is employed to improve reliability. In the LDD junction structure, the margin of the operating voltage can be improved by making the N- / P- region of the low concentration wider than the N + / P + region of the high concentration, and for this purpose, the distance from the gate to the N + / P + region is increased. It can be adjusted by a spacer formed on the side wall of the.

Since the spacer formed by the conventional process technology has the same width in both the N-type and the MOS transistors, the characteristics of the N-type transistor are improved, but in the case of the MOS transistor, the high concentration P + region present in the active region is The problem of not overlapping with the gate occurs. Therefore, there is a strong demand for a technique that can sufficiently secure the junction overlap region of the PMOS transistor while adopting the LDD junction structure, so as to obtain desired threshold voltage values for each transistor.

Accordingly, an object of the present invention is to provide a method for manufacturing a CMOS transistor that can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a method for manufacturing a CMOS transistor that can simplify the manufacturing process.

It is still another object of the present invention to provide an improved method for achieving a junction overlap region of a PMOS transistor, while employing an LDD junction structure to obtain desired threshold voltage values for each transistor, respectively, and to improve the structure of the CMOS transistor. In providing.

Still another object of the present invention is to provide a structure of a CMOS transistor that can be suitably used in a peripheral circuit of a nonvolatile memory device such as a noah type flash memory.

In order to achieve the above object, the structure of the CMOS transistor according to the present invention includes: a composite spacer formed on sidewalls of a gate of a second conductive MOS transistor and formed of first and second insulating films; A spacer formed on the sidewall of the gate of the first conductive MOS transistor and formed of the first insulating film; The lower regions of the gates may have drain regions having different sizes of junction overlap regions overlapping the gates as LDD structures.

In addition, a method of manufacturing a first conductive MOS transistor and a second conductive MOS transistor on a first conductive semiconductor substrate includes forming a gate of the second conductive MOS transistor on the substrate and forming a second conductive layer in the substrate. After forming a gate of the first conductive MOS transistor in a type well, implanting a second conductive impurity at low concentration to form an LDD in regions where drain and source regions of the transistors are to be formed; Applying first and second insulating layers on the gates and on the ion implanted regions as a whole; Covering the region of the first conductive MOS transistor and etching back the region of the second conductive MOS transistor to form a composite spacer including the first and second insulating layers on the sidewalls of the gate of the second conductive MOS transistor. Ion-implanting a second conductive impurity at a high concentration to form an LDD formation structure of the second conductive MOS transistor; Covering the region of the second conductive MOS transistor and etching back only the first insulating layer in the region of the first conductive MOS transistor, a spacer including the first insulating layer is formed on the sidewall of the gate of the first conductive MOS transistor. Forming a first conductive impurity at a high concentration to form an LDD formation structure of the first conductive MOS transistor after the formation; And opening the region of the second conductive MOS transistor and performing heat treatment to obtain the transistor having different sizes of junction overlap regions overlapping the lower portions of the gates according to the widths of the spacers. .

1 through 6 are cross-sectional views illustrating a process of manufacturing a CMOS transistor according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same layers as each other are labeled with the same or similar reference numerals or names for convenience of understanding even if they are in different drawings. In the following description, specific details are set forth in detail, for example, in order to provide a more thorough understanding of the present invention. However, for those skilled in the art, the present invention may be practiced only by the above description without these details. In addition, the basic fabrication process and characteristics of MOS transistors so well known in the art are not described in detail in order to not obscure the subject matter of the present invention.

A flowchart of a CMOS manufacturing process according to an embodiment of the present invention is shown in FIGS. 1 to 6. Referring to FIG. 1, an n-well 20 is formed on a p-sub silicon substrate 10 to make a PMOS. NMOS can be formed directly on the p-well or the substrate 10. Making the N well 20 and the P well on the substrate 10 may be performed by the following process. First, an oxide film and a nitride film are formed on the substrate 10 respectively, 300 Å / 1500 Å, the region where the PMOS transistor is to be formed, the region of the nitride film is removed, and the phosphorus, which is an n-type impurity, is about 1.7E13 ions / cm 2. , 100KeV. In this way, an N-type impurity is injected into a part of the surface of the substrate 10 to partially complete the formation of the N-type well 20. Subsequently, an oxide film of 3000 kPa is formed in the portion where the nitride film is removed, and the nitride film of the remaining portion is removed to start the work of forming a pewell in which enmoose is to be made. In other words, boron, which is a p-type impurity, is implanted at 2.0E13 ions / cm 2 and 100 KeV so that an impurity of a type is implanted near the surface of the substrate 10 under the portion where the remaining nitride film is removed. Afterwards, the drive-in process is performed at 1100 ° C. for about 8 hr to form n-well 20 and p-well of about 5 μm in depth.

After the wells or wells are formed, a field insulating film is formed through a general local oxidation process such as LOCOS to separate active and device isolation regions. The field insulating film is not shown in FIG. As a result, active regions are defined on the wells 20 and 10, respectively. On each of the active regions, an oxide film 40.41 as a gate insulating film is formed to a thickness of about 100 GPa. Then, an undoped polysilicon is deposited on the upper portion of the gate electrode to about 4000 mV, and gate patterning is performed to simultaneously obtain the gate 50 of the enMOS transistor and the gate 51 of the PMOS transistor. In this case, when the gates 50 and 51 are formed as polyside gate electrodes, undoped polysilicon of about 1500 kV and metal silicide of about 1500 kPa may be stacked. After completing the gates of FIG. 1, phosphorus or arsenic as n-impurities were implanted into the front of the wafer as 2.0E13 ions / cm 2, 40KeV for LDD formation of the NMOS. As a result, a second conductivity type, for example, an N-type impurity, is ion-implanted at low concentrations in the regions 30, 31, 32, and 33 where the drain and source regions of the transistors are to be formed.

Then, in order to form spacers to be described later, the first and second insulating layers 60 and 65 are entirely formed on the upper portions of the gates 50 and 51 and the ion implanted regions 30 to 33 as shown in FIG. Apply. Here, the first insulating film 60 may be formed of an oxide film, the second insulating film 65 may be formed of a nitride film, a polysilicon film, or a composite film thereof. When the oxide film 60 is employed as the first insulating film, it may be deposited to a thickness of about 1500 kPa by a conventional CVD method.

Referring to FIG. 3, the PMOS region is limited to the photoresist layer 70 and the like, and then the back insulation layers 65 and 60 in the region of the NMOS transistor are etched back to the sidewalls of the gate 50. Formation of a composite spacer 64 made of an insulating film is shown. Thereafter, a second conductive impurity such as n + impurity arsenic is implanted at a high concentration as 5.0E15 ions / cm 2, 50 KeV to form the LDD formation structure of the NMOS transistor.

4 and 5, the region of the NMOS transistor is covered with a mask 71 of a photoresist or the like, and the first insulating layer 60 remaining by wet etching the second insulating layer 65 in the region of the PMOS transistor is removed by wet etching. Bayer was etched back to form a spacer 62 made of the first insulating layer 60 on the sidewall of the gate 51 of the PMOS transistor, and then, BF2, 5.0 p. High concentration ion implantation at 50 KeV has been shown. Therefore, the width of the spacer 62 has a smaller size than the width of the composite spacer 64.

In FIG. 6, the film 71 is removed to even open the region of the NMOS transistor, and heat treatment is performed to obtain the transistor in which the size of the junction overlap region overlapping each of the lower portions of the gates is different depending on the width of the spacers. The results are shown. In FIG. 6, the P + junction overlap region OL1 of the NMOS transistor is relatively large compared to that of the NMOS.

In the above embodiment, in order to reduce two etchbacks in one cycle, the etchback is performed without mask for the entire CMOS region, and then the composite spacer is made into a single spacer before implanting ions into the source and drain of the PMOS transistor. It can have

In addition, it can be seen that an impurity channel implantation process or a PMOS LDD process can be added to control the threshold voltage of the transistor, and a modified process in which the NMOS LDD process can be removed is possible. In addition, the order of n + and p + injection processes is irrelevant. In order to apply LDD to a PMOS, a mask may be added before forming a spacer, and boron may be injected as p-impurity at 4.0E13 ions / cm 2 and 30 KeV. As another modification process, the n-ion implantation process can be eliminated when only the PMOS is made of LDD and the NMOS is formed by a typical junction. In order to increase the injection length of the impurities to be injected, it is better to inject arsenic or BF2 than phosphorus or boron.

Exemplary manufacturing processes according to the present invention have been shown in accordance with the above descriptions and drawings, but this is merely for example and various changes and modifications are possible.

According to the present invention described above, the advantages of providing a CMOS transistor having a low cost and excellent characteristics due to the simple process and excellent characteristics, and sufficiently ensuring the junction overlap region of the PMOS transistor while adopting the LDD junction structure, There is an effect that each of the desired threshold voltage values can be obtained.

Claims (4)

A method for manufacturing a first conductive MOS transistor and a second conductive MOS transistor on a first conductive semiconductor substrate; After forming the gate of the second conductive MOS transistor on the substrate and the gate of the first conductive MOS transistor in the second conductive well in the substrate, the region where the drain and source regions of the transistors are to be formed. Ion implanting a second conductive impurity at low concentration to form LDD in the field; Applying first and second insulating films over the constants of the gates and the ion implanted regions as a whole; Covering the region of the first conductive MOS transistor and etching back the region of the second conductive MOS transistor to form a composite spacer including the first and second insulating layers on the gate sidewall of the second conductive MOS transistor. Thereafter, ion implanting a second conductive impurity at a high concentration to form an LDD formation structure of the second conductive MOS transistor; Covering the region of the second conductive MOS transistor and etching back only the first insulating layer in the region of the first conductive MOS transistor, a spacer made of the first insulating layer is formed on the gate sidewall of the first conductive MOS transistor. Forming a first conductive impurity at a high concentration to form an LDD formation structure of the first conductive MOS transistor after the formation; Opening the region of the second conductive MOS transistor and performing a heat treatment to obtain the transistor having different sizes of junction overlap regions overlapping the lower portions of the gates according to the widths of the spacers. Way. The method of claim 1, wherein the width of the composite spacer is greater than the width of the spacer. The method of claim 2, wherein when the second conductivity type is n-type, the first conductivity type is p-type. A method for manufacturing a first conductive MOS transistor and a second conductive MOS transistor on a first conductive semiconductor substrate; After forming the gate of the second conductive MOS transistor in the first conductive well in the substrate and the gate of the first conductive MOS transistor in the second conductive well in the substrate, drain and source of the transistors Low ion implantation of second conductivity type impurities into the regions where the regions are to be formed; Applying first and second insulating films on the gates and on the ion implanted regions as a whole; The insulating layers are etched back to form a composite spacer including the first and second insulating layers on the gate sidewalls of the first and second conductive MOS transistors, and then cover an area of the first conductive MOS transistor and cover the second conductive layer. Ion implanting a second conductive impurity at a high concentration to form an LDD forming structure of the type MOS transistor; A gate sidewall of the first conductive MOS transistor is formed by covering the region of the second conductive MOS transistor, removing the second insulating layer of the composite spacer in the region of the first conductive MOS transistor, and etching only the first insulating layer. Forming a spacer made of the first insulating film in the substrate, and ion implanting the first conductive impurities at a high concentration to form a structure of the first conductive MOS transistor; Opening the region of the second conductive MOS transistor and performing a heat treatment to obtain the transistor having different sizes of the heavily-concentrated junction overlap regions overlapping the lower portions of the gates according to the widths of the spacers. How to feature. Opening the region of the second conductive MOS transistor and performing a heat treatment to obtain the transistor in which the size of the highly-concentrated junction overlap region overlapping each of the lower portions of the gates is different depending on the width of the spacers. How to.

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