KR20010063772A - A method for forming of a semiconductor device - Google Patents
A method for forming of a semiconductor device Download PDFInfo
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- KR20010063772A KR20010063772A KR1019990061860A KR19990061860A KR20010063772A KR 20010063772 A KR20010063772 A KR 20010063772A KR 1019990061860 A KR1019990061860 A KR 1019990061860A KR 19990061860 A KR19990061860 A KR 19990061860A KR 20010063772 A KR20010063772 A KR 20010063772A
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- junction region
- forming
- low concentration
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- gate electrode
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 18
- 230000015556 catabolic process Effects 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000012535 impurity Substances 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims 1
- 239000002019 doping agent Substances 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 230000008439 repair process Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Description
본 발명은 반도체소자의 형성방법에 관한 것으로, 특히 고전압에서 드레인 접합영역의 브레이크다운 전압 ( breakdown voltage ) 에 안정적으로 동작할 수 있는 트랜지스터를 구현하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, to a technique for implementing a transistor capable of stably operating at a breakdown voltage of a drain junction region at a high voltage.
일반적으로, 전 공정을 다 거친 웨이퍼는 바로 테스트를 하여 리페어 ( repair ) 를 하게 된다.In general, wafers that have been through the entire process are tested and repaired immediately.
그러나, 패키지가 되고 나면 리페어가 불가능해 진다. 이렇게 패키지를 하고 난 후에 페일이 나는 칩이 전체의 5 퍼센트 정도 된다.However, once packaged, repair is impossible. After this package, the failing chip is about 5 percent of the total.
그리하여, 요즘은 패키지를 하고 난 후에도 리페어가 가능하도록 안티 퓨즈 ( anti-fuse ) 를 사용하고 있다.Thus, these days, anti-fuse is used to repair even after package.
그러나, 이것은 기존의 메모리 칩에서 사용하지 않던 고전압을 필요로 하게 된다.However, this requires a high voltage that is not used in conventional memory chips.
그래서, 기존의 주변회로부의 트랜지스터 드레인에 걸리던 전압보다 훨씬 높은 전압이 걸리게 된다.Therefore, a voltage much higher than that of the transistor drain of the existing peripheral circuit part is applied.
기존에 사용하는 트래지스터는, 저농도와 고농도의 엔형 불순물 접합영역을 사용하는 트랜지스터의 접합 브레이크다운 전압이 대략 8 볼트 ( volt ) 이하로서, 현재의 메모리 반도체소자에서는 사용하기 충분하였다.Conventional transistors have a junction breakdown voltage of about 8 volts or less for transistors using low concentrations and high concentrations of en-type impurity junction regions, which are sufficient for use in current memory semiconductor devices.
그러나, 안티 퓨즈 회로를 사용하는 경우 7 내지 8 볼트의 고전압을 사용하게 되어 트랜지스터의 드레인에 이 전압이 그대로 걸리게 되고 드레인 접합 브레이크다운 전압이 생길 가능성이 높아지게 된다.However, in the case of using an anti-fuse circuit, a high voltage of 7 to 8 volts is used, so that the voltage is applied to the drain of the transistor as it is and a possibility of generating a drain junction breakdown voltage is increased.
상기한 바와같이 종래기술에 따른 반도체소자의 형성방법은, 안티 퓨즈 회로를 사용할때 드레인에 걸리는 고전압으로 인하여 트랜지스터의 특성 열화가 유발되어 반도체소자의 특성 및 신뢰성을 저하시키는 문제점이 있다.As described above, the method of forming a semiconductor device according to the related art has a problem in that the characteristics of the transistor are deteriorated due to the high voltage applied to the drain when the anti-fuse circuit is used, thereby degrading the characteristics and reliability of the semiconductor device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 드레인 접합영역의 도핑농도를 감소시켜 전압 인가시 공핍영역을 증가시킴으로써 브레이크다운 전압을 증가시켜 안티 퓨즈 회로의 적용시 유발될 수 있는 소자의 특성 열화를 최소화시킬 수 있는 반도체소자의 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the characteristics of a device that can be induced when applying an anti-fuse circuit by increasing the breakdown voltage by reducing the doping concentration of the drain junction region and increasing the depletion region when voltage is applied It is an object of the present invention to provide a method for forming a semiconductor device capable of minimizing deterioration.
도 1 내지 도 7 은 본 발명의 실시예에 따른 반도체소자의 형성방법을 도시한 단면도.1 to 7 are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.
도 8 은 본 발명의 실시예에 따라 형성된 반도체소자에서 저농도의 엔형 드레인 접합영역을 이용한 트랜지스터의 브레이크다운 전압 변화를 도시한 그래프도.FIG. 8 is a graph illustrating breakdown voltage variation of a transistor using a low concentration of an n-type drain junction region in a semiconductor device formed in accordance with an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11 : 반도체기판 13 : 제1폴리실리콘11: semiconductor substrate 13: first polysilicon
15 : 마스크산화막 17 : 절연막 스페이서15 mask oxide film 17 insulating film spacer
19a : 저농도의 엔형 드레인 접합영역19a: Low concentration en-type drain junction region
19b : 저농도의 엔형 소오스 접합영역19b: low concentration en-type source junction region
21 : 플러그 폴리 23 : 제1감광막패턴21 plug poly 23 first photosensitive film pattern
25 : 콘택패드 27 : 제2감광막패턴25: contact pad 27: second photosensitive film pattern
28 : 고농도의 엔형 소오스 접합영역28: high concentration En-type source junction region
29 : 콘택플러그29: Contact Plug
ⓐ : 저농도의 엔형 드레인 접합영역과, LDD 구조의 엔형 소오스 접합영역이 구비되는 트랜지스터Ⓐ: A transistor having a low concentration of the N-type drain junction region and an LD-type source junction region.
ⓑ : 저농도의 엔형 소오스/드레인 접합영역이 구비되는 트랜지스터Ⓑ is transistor with low concentration source / drain junction region
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 형성방법은,In order to achieve the above object, a method of forming a semiconductor device according to the present invention,
주변회로부에 브레이크다운 전압이 증가된 트랜지스터를 구비하는 반도체소자의 형성방법에 있어서,A method of forming a semiconductor device comprising a transistor having a breakdown voltage increased in a peripheral circuit portion,
반도체기판 상부에 게이트전극을 형성하고 이를 이용하여 상기 반도체기판에 저농도의 엔형 소오스/드레인 접합영역을 형성하는 공정과,Forming a gate electrode on the semiconductor substrate and using the same to form a low concentration N-type source / drain junction region on the semiconductor substrate;
상기 게이트전극 측벽에 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on the sidewalls of the gate electrode;
전체표면상부에 플러그 폴리를 형성하는 공정과,Forming a plug poly on the entire surface;
상기 플러그 폴리를 패터닝하여 상기 저농도의 엔형 드레인 접합영역에 접속되는 콘택패드를 형성하는 공정과,Patterning the plug poly to form a contact pad connected to the low-energy drain region;
상기 저농도의 엔형 소오스 접합영역에만 고농도의 엔형 불순물을 이온주입하여 LDD 구조의 소오스 접합영역을 형성하는 공정을 포함하는 것을 특징으로한다.And ion implanting a high concentration of the en-type impurity into only the low concentration of the en-type source junction region to form a source junction region having an LDD structure.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는, 다음과 같다.On the other hand, the principle of the present invention for achieving the above object is as follows.
일반적으로, 도핑농도가 낮아지면 양단에 전압이 걸렸을때 공핍영역이 넓어지면서 브레이크다운 전압이 증가한다. 이원리를 이용하여 드레인 쪽 접합 브레이크다운 전압을 높이기 위해 드레인 쪽은 저농도의 엔형 불순물 접합영역만을 형성하고 소오스 쪽은 기존대로 저농도와 고농도의 엔형 불순물 접합영역을 형성한다.In general, when the doping concentration decreases, the breakdown voltage increases as the depletion region becomes wider when voltage is applied at both ends. In order to increase the drain-side junction breakdown voltage using this principle, the drain side forms only a low concentration of the Y-type impurity junction region, and the source side forms a low concentration and a high concentration of the Y-type impurity junction region as before.
이는 고전압은 트랜지스터의 드레인에 일반적으로 걸리므로 브레이크다운 전압 특성을 향상시키는 측면에서 유리하다. 위의 방법은 드레인 뿐만아니라 소오스에도 사용할 수 있되, 플러그 폴리를 사용할 수 있는 것이다.This is advantageous in terms of improving the breakdown voltage characteristics since high voltages are generally applied to the drain of the transistor. The above method can be used for sources as well as drains, but with plug poly.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 7 는 본 발명의 실시예에 따른 반도체소자의 형성방법을 도시한 단면도로서, 주변회로부에 형성되는 안티 퓨즈 회로 사용시 고전압에 견질 수 있는 트랜지스터를 형성하는 것이다.1 to 7 are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention, in which a transistor capable of withstanding high voltage when using an anti-fuse circuit formed in a peripheral circuit part is formed.
먼저, 반도체기판(11) 상부에 제1폴리실리콘(13), 마스크산화막(15)의 적층구조로 형성된 게이트전극을 형성한다.First, a gate electrode formed in a stacked structure of the first polysilicon 13 and the mask oxide film 15 is formed on the semiconductor substrate 11.
그 다음, 상기 게이트전극을 마스크로하여 상기 반도체기판(11)에 저농도의 엔형 불순물을 이온주입함으로써 저농도의 엔형 드레인/소오스 접합영역(19a, 19b)을 형성한다. (도 1)Next, a low concentration of the N type drain / source junction regions 19a and 19b is formed by ion implanting a low concentration of the Y type impurity into the semiconductor substrate 11 using the gate electrode as a mask. (Figure 1)
그리고, 전체표면상부에 플러그 폴리(21)를 형성한다. (도 2)Then, the plug poly 21 is formed on the entire surface. (Figure 2)
그리고, 플러그 폴리(21) 상부에 제1감광막패턴(23)을 형성한다.The first photoresist pattern 23 is formed on the plug poly 21.
이때, 상기 제1감광막패턴(23)은 저농도의 엔형 드레인 접합영역(19a) 상측을 도포할 수 있도록 형성한 것이다. (도 3a)In this case, the first photoresist layer pattern 23 is formed so that the upper side of the N-type drain junction region 19a having a low concentration can be coated. (FIG. 3A)
도 3b 는, 상기 제1감광막패턴(23)을 저농도의 엔형 드레인/소오스 접합영역(19a,19b) 상측에 형성한 것을 도시한다. (도 3b)FIG. 3B shows that the first photoresist film pattern 23 is formed above the low concentration of the N-type drain / source junction regions 19a and 19b. (FIG. 3B)
그 다음, 상기 제1감광막패턴(23)을 마스크로하여 상기 플러그 폴리(21)를 식각하고 상기 제1감광막패턴(23)을 제거함으로써 상기 저농도의 엔형 드레인 접합영역(19a)에 접속되도록 콘택패드(25)를 형성한다. (도 4a, 도 5a)Thereafter, the plug poly 21 is etched using the first photoresist pattern 23 as a mask and the first photoresist pattern 23 is removed to contact the low concentration Y-type drain junction region 19a. To form 25. (FIG. 4A, FIG. 5A)
도 4b 및 도 5b 는 상기 도 3b 의 공정후 상기 제1감광막패턴(23)을 마스크로하여 상기 플러그 폴리(21)를 식각하고 상기 제1감광막패턴(23)을 제거함으로써 상기 저농도의 엔형 소오스/드레인 접합영역(19b,19a)에 접속되는 콘택패드(25)를 형성한다.4B and 5B illustrate the low concentration N-type source / etched by etching the plug poly 21 and removing the first photoresist pattern 23 using the first photoresist pattern 23 as a mask after the process of FIG. 3B. Contact pads 25 are formed to be connected to the drain junction regions 19b and 19a.
그 다음, 상기 저농도의 엔형 드레인 접합영역(19a)에 인접한 게이트전극을 도포하여 저농도의 엔형 소오스 접합영역(19b)을 노출시키는 제2감광막패턴(27)을 형성한다.Next, the second photoresist layer pattern 27 exposing the low concentration Y-type source junction region 19b is formed by applying a gate electrode adjacent to the low concentration Y-type drain junction region 19a.
그리고, 상기 제2감광막패턴(27)을 마스크로하여 상기 반도체기판(11)에 고농도의 엔형 불순물을 이온주입하여 고농도의 엔형 소오스 접합영역(28)을 형성함으로써 LDD 의 소오스 접합영역을 형성한다. (도 6)A high concentration of the en-type impurity junction region 28 is formed by ion implanting a high concentration of the en-type impurity into the semiconductor substrate 11 using the second photoresist pattern 27 as a mask to form a source junction region of the LDD. (Figure 6)
그 다음, 상기 드레인 접합영역(19a) 상측의 콘택패드(25) 및 LDD 의 소오스 접합영역(19b,28)에 각각 접속되는 콘택프러그(29)를 형성한다.Next, contact plugs 29 are formed to be connected to the contact pads 25 on the drain junction region 19a and the source junction regions 19b and 28 of the LDD, respectively.
여기서, ⓐ 는 저농도 및 고농도의 엔형 소오스 접합영역(19b,28) 및 저농도의 엔형 드레인 접합영역(19a) 그리고 게이트전극으로 구비되는 트랜지스터를 도시한다. (도 7a)Here,? Represents a transistor provided with the low concentration and high concentration of the N-type source junction regions 19b and 28, the low concentration of the N-type drain junction region 19a, and the gate electrode. (FIG. 7A)
도 7b 는 상기 도 5b 의 공정후 상기 콘택패드(25)에 접속되는 콘택플러그(29)를 형성한 것이다.FIG. 7B shows a contact plug 29 connected to the contact pad 25 after the process of FIG. 5B.
이때, ⓑ 는 저농도의 엔형 소오스/드레인 접합영역(19b,19a) 그리고 게이트전극으로 구비되는 트랜지스터를 도시한 것이다.In this case, ⓑ shows a transistor having low concentration of the N-type source / drain junction regions 19b and 19a and the gate electrode.
도 8 은 본 발명에 따라 저농도의 엔형 드레인 접합영역으로 트랜지스터를 형성하는 경우의 브레이크다운 전압 변화를 도시한 그래프도로서, 브레이크다운 전압이 10 볼트 정도로 기존의 8볼트에 비하여 증가된 것을 도시한다.FIG. 8 is a graph showing breakdown voltage change when a transistor is formed with a low concentration of an N-type drain junction region according to the present invention, and shows that the breakdown voltage is increased by about 10 volts compared with the conventional 8 volts.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 형성방법은, 드레인 접합영역에 저농도의 엔형 드레인 접합영역만이 형성된 트랜지스터를 형성하여 전압 인가시 브레이크다운 전압이 증가되고 그로인하여 고전압을 필요로 하는 안티 퓨즈 회로의 이용을 가능하게 후속 리페어 공정을 용이하게 함으로써 반도체소자의 수율을 향상시킬 수 있는 효과를 제공한다.As described above, in the method of forming the semiconductor device according to the present invention, a transistor in which only a low concentration of the n-type drain junction region is formed in the drain junction region is formed so that the breakdown voltage is increased when voltage is applied, thereby requiring a high voltage. The use of a fuse circuit facilitates the subsequent repair process, thereby providing an effect of improving the yield of the semiconductor device.
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| KR101519457B1 (en) * | 2012-11-23 | 2015-05-21 | 세미컨덕터 매뉴팩춰링 인터내셔널 (상하이) 코포레이션 | A semiconductor device and a method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101519457B1 (en) * | 2012-11-23 | 2015-05-21 | 세미컨덕터 매뉴팩춰링 인터내셔널 (상하이) 코포레이션 | A semiconductor device and a method for manufacturing the same |
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