KR19990057385A - Manufacturing method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a technology for improving refresh characteristics and contact resistance characteristics of a device by using a slow method to form an insulating spacer surrounding a gate electrode.

To this end, the present invention insulates the contact between the gate electrode and the source / drain electrodes, and when forming an insulation spacer surrounding the gate electrode sidewall, by varying the thickness of the insulation spacer of the NMOS region and the PMOS region and forming the insulation spacer by using the slow method. The threshold voltages of the NMOS and PMOS can be adjusted to improve the electrical characteristics of the device, and the defects of the semiconductor substrate can be reduced by not etching the portions where the NMOS and PMOS source / drain electrodes are formed in the cell region. Provided is a method of manufacturing a semiconductor device capable of improving refresh characteristics and contact resistance characteristics.

Description

Manufacturing method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, when forming an insulation spacer surrounding a gate electrode poly1, the thickness of the insulation spacer of the NMOS region and the PMOS region is varied, and the insulation spacer is formed using a slope method. A technique for improving the refresh characteristics and contact resistance characteristics of the device

In general, a poly1 spacer is formed by depositing oxide or nitride with an insulating material and then etching a blanket without a mask after forming a poly1. Since the spacer forming method does not use a mask, the process can be performed in a simple process. This advantage is widely used.

However, the insulating layer etching method using the entire surface etching has a problem in that the gate electrode is also etched to some extent and defects occur in the gate electrode.

In addition, since there is no insulating material on the gate electrode, when the ion is implanted into the NMOS region or the source / drain electrode of the PMOS in the subsequent process, the gate electrode also receives ion defects, as well as the resistance of polysilicon used as the gate electrode There is a disadvantage in that the resistance of the contact drilled on the gate electrode is increased by increasing.

In addition, the formation of the spacer using the front etching method has a disadvantage in that an insulating material cannot be left on the gate electrode in order not to leave an insulating material on the Si surface because the etching rate is the same on the gate electrode and on the Si surface or the field oxide film.

In addition, the etching method using the mask has the advantage that the insulating material on the Si surface can be removed while leaving the insulating material on the gate electrode, but manufacturing a new mask to form the spacer is a big disadvantage in terms of economics.

Accordingly, the present invention is to solve the above problems and to insulate between the contact of the gate electrode poly1 and the source / drain electrode, and to vary the thickness of the insulation spacer of the NMOS region and the PMOS region when forming an insulating spacer surrounding the gate electrode sidewalls By using the slope method, insulation characteristics between poly1 and poly2 contacts and poly1 and poly3 contacts, which are vulnerable in the cell region, can be improved, and the spacer width of the NMOS and PMOS can be adjusted to improve the electrical properties of the device. The semiconductor device can improve the characteristics and improve the refresh and contact resistance characteristics of the device by reducing defects in the semiconductor substrate without etching the portions where the NMOS and PMOS source / drain electrodes are formed in the cell region. Its purpose is to provide a method of manufacturing.

1A to 1F are manufacturing process diagrams of a semiconductor device according to the present invention.

<Explanation of symbols for main parts of the drawings>

10 semiconductor substrate 12 device isolation insulating film

14 gate insulating film 16 conductive layer pattern

18 low concentration diffusion region 20 insulating film

22: first photosensitive film pattern 24: second photosensitive film pattern

26, 32: insulation spacer 28, 34: high concentration diffusion region

30: third photosensitive film pattern 36: first interlayer insulating film

38: second interlayer insulating film

According to the present invention to achieve the above object,

Forming a gate insulating film and a gate electrode on the semiconductor substrate;

Forming an insulating film on the entire surface of the structure;

Forming a first photoresist film pattern for a gate mask on the insulating film on the gate electrode;

Forming an insulating film pattern having an inclined sidewall on the gate electrode by a slow etching process using the first photoresist pattern as a mask;

Forming a second photoresist film pattern over the cell region exposing the first conductive MOS region and the second conductive MOS region insulating film pattern;

Forming an insulating spacer surrounding the gate electrode in the first conductive MOS region by etching the entire surface of the second photoresist pattern with a mask;

Forming a first MOSFET in the first conductive MOS region;

Forming a third photoresist pattern on the cell region exposing the second conductive MOS region and the first conductive MOS region insulation pattern;

Forming an insulating spacer surrounding the gate electrode in a second conductive MOS region by etching the third photoresist pattern with a mask;

And forming a second MOSFET in the second conductive MOS region.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

1A to 1F are manufacturing process diagrams of a semiconductor device according to the present invention.

First, a device isolation insulating film 12 for device isolation, a gate insulating film 14 made of an oxide film, and a conductive layer pattern 16 for a gate electrode made of a polysilicon film pattern are sequentially formed on the semiconductor substrate 10.

At this time, the semiconductor substrate 10 is divided into a cell region (A), an NMOS region (B), and a PMOS region (C).

Next, a low concentration ion implantation process is performed on the entire surface of the structure to form the low concentration diffusion region 18 on the semiconductor substrate 10 on both sides of the conductive layer pattern 16.

After that, the insulating film 20 is formed on the entire surface of the cell region A, the NMOS region B, and the PMOS region C having the above structure.

At this time, the insulating film 20 is formed of one film arbitrarily selected from the group consisting of an oxide film, a nitride film, and an insulating material (see FIG. 1A).

Next, a first photoresist film pattern 22 for a gate mask is formed on the insulating film 20 including the conductive layer pattern 16 (see FIG. 1B).

Next, an insulating layer 20 pattern having an inclined sidewall is formed on the conductive layer pattern 16 by a slope etching process using the first photoresist layer pattern 22 as a mask.

The reason why the insulating layer 20 is not etched completely in the active region is to reduce the attack of the active region during the NMOS and PMOS mask processes in the subsequent process (see FIG. 1C).

Next, the second photoresist layer pattern 24 is formed on the cell region A and the PMOS region C while exposing the NMOS region B. FIG.

Thereafter, the second photoresist pattern 24 is etched with a mask to form an insulating spacer 26 covering the entire conductive layer pattern 16 in the NMOS region B.

In addition, a high concentration ion implantation process is performed in the NMOS region B to form a high concentration diffusion region 28 in the semiconductor substrate 10 on both sides of the insulating spacer 26 (see FIG. 1D).

Next, the PMOS region C is exposed, and a third photoresist pattern 30 is formed on the cell region A and the NMOS region B.

Thereafter, the third photoresist pattern 30 is etched with a mask to form an insulating spacer 32 covering the entire conductive layer pattern 16 in the PMOS region C.

At this time, the thickness of the insulating spacer 26 formed in the NMOS region B and the thickness of the insulating spacer 32 formed in the PMOS region C are different from each other so that the NMOS region B and the PMOS region C are formed. The threshold voltage can be adjusted to improve the electrical characteristics of the device.

In the PMOS region C, a high concentration diffusion region 34 is formed in the semiconductor substrate 10 on both sides of the insulating spacer 32 (see FIG. 1E).

Next, the first interlayer insulating film 36 and the second interlayer insulating film 38 are sequentially formed on the entire surface of the structure.

In this case, the first interlayer insulating layer 36 is an M.T. film, and the second interlayer insulating layer 38 is a B.P.S. paper (BPSG). ) Is formed into a film (see FIG. 1F).

In addition, as a preferred embodiment of the present invention by depositing a nitride film with an insulating film on the conductive layer pattern (Poly 1) and etching to expose the active region of the semiconductor substrate in a slow manner to form an insulating spacer surrounding the conductive layer pattern At the time of contact etching, self-aligned contacts may be formed.

As described above, according to the present invention, when forming the insulating spacer of the sidewall of the gate electrode poly1, the thickness of the insulating spacer of the NMOS region and the PMOS region is different, and the insulating spacer is formed by using a slope method, which is vulnerable in the cell region. The insulation properties between the poly1 and poly2 contacts and the poly1 and poly3 contacts can be improved, and the spacer width (ie, the threshold voltage) of the NMOS and PMOS can be adjusted to improve the electrical characteristics of the device.

In addition, since the defects of the semiconductor substrate can be reduced by not etching the portions where the source / drain electrodes of the NMOS and the PMOS are formed in the cell region, the refresh characteristics and the contact resistance characteristics of the device can be improved.

In addition, since the insulating spacers of the sidewalls of the gate electrodes are formed of a nitride film, there is an advantage that a self-aligned contact method may be formed in the poly 2 contact and the poly 3 contact etching process on the poly 1 side or the top surface.

Claims (5)

Forming a gate insulating film and a gate electrode on the semiconductor substrate; Forming an insulating film on the entire surface of the structure; Forming a first photoresist film pattern for a gate mask on the insulating film on the gate electrode; Forming an insulating film pattern having an inclined sidewall on the gate electrode by a slow etching process using the first photoresist pattern as a mask; Forming a second photoresist film pattern over the cell region exposing the first conductive MOS region and the second conductive MOS region insulating film pattern; Forming an insulating spacer covering the entire gate electrode in the first conductive MOS region by etching the entire surface of the second photoresist pattern with a mask; Forming a first MOSFET in the first conductive MOS region; Forming a third photoresist pattern on the cell region exposing the second conductive MOS region and the first conductive MOS region insulation pattern; Forming an insulating spacer covering the entire gate electrode in the second conductive MOS region by etching the third photoresist pattern with a mask; And forming a second MOSFET in the second conductive MOS region. The method of claim 1, wherein the insulating film is formed of one film arbitrarily selected from the group consisting of an oxide film, a nitride film, and an insulating material. The method of claim 1, wherein the first conductive MOS region is formed of NMOS and formed of the second conductive PMOS. The method of claim 1, wherein the thickness of the insulating spacer formed in the first conductive MOS region is different from that of the insulating spacer formed in the second conductive MOS region. The method of claim 1, wherein when the insulating layer pattern having the sidewalls inclined to the gate electrode is formed as a nitride layer, the semiconductor device is etched until the semiconductor substrate is exposed in a slowing manner.