KR20000065714A - Fabricating method of semiconductor device - Google Patents
Fabricating method of semiconductor device Download PDFInfo
- Publication number
- KR20000065714A KR20000065714A KR1019990012328A KR19990012328A KR20000065714A KR 20000065714 A KR20000065714 A KR 20000065714A KR 1019990012328 A KR1019990012328 A KR 1019990012328A KR 19990012328 A KR19990012328 A KR 19990012328A KR 20000065714 A KR20000065714 A KR 20000065714A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor substrate
- etched
- gate
- region
- film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 150000004767 nitrides Chemical class 0.000 claims abstract description 37
- 239000012535 impurity Substances 0.000 claims abstract description 23
- 150000002500 ions Chemical class 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 230000003647 oxidation Effects 0.000 claims abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 claims description 90
- 238000005530 etching Methods 0.000 claims description 13
- 238000005498 polishing Methods 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 28
- 239000011229 interlayer Substances 0.000 abstract description 9
- 230000002093 peripheral effect Effects 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 반도체기판 내에 소자를 제조하여 공정을 단순화함과 아울러 특성을 향상시키기에 적당하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which the device is manufactured in a semiconductor substrate so as to simplify the process and improve the characteristics thereof.
종래 반도체소자의 제조방법을 도1a 내지 도1g에 도시한 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A method of manufacturing a conventional semiconductor device will be described in detail with reference to the procedure cross-sectional view shown in FIGS. 1A to 1G as follows.
먼저, 도1a에 도시한 바와같이 셀영역과 주변영역의 반도체기판(1) 상부전면에 순차적으로 버퍼산화막(2)과 질화막(3)을 형성한 후, 사진식각공정을 통해 상기 질화막(3)과 버퍼산화막(2)의 일부를 식각하고, 계속해서 반도체기판(1)을 소정깊이로 식각하여 셀영역에 소정거리 이격되는 트렌치(4A,4B)를 형성함과 아울러 주변영역에 트렌치(4C)를 형성하여 셀영역과 주변영역 상에 액티브영역을 정의한다.First, as shown in FIG. 1A, the buffer oxide film 2 and the nitride film 3 are sequentially formed on the upper surface of the semiconductor substrate 1 in the cell region and the peripheral region, and then the nitride film 3 is formed through a photolithography process. And a portion of the buffer oxide film 2 are etched, and then the semiconductor substrate 1 is etched to a predetermined depth to form trenches 4A and 4B spaced a predetermined distance from the cell region and trenches 4C in the peripheral region. To define an active region on the cell region and the peripheral region.
그리고, 도1b에 도시한 바와같이 산화공정을 통해 상기 트렌치(4A∼4C)의 내벽에 얇은 산화막(5)을 성장시키고, 그 구조물의 상부전면에 고온저압 산화막(6)을 형성하여 열처리한 후, 상기 액티브영역의 버퍼산화막(2)이 노출될때까지 화학기계적 연마(chemical mechanical polishing : CMP)하여 평탄화한다.1B, a thin oxide film 5 is grown on the inner walls of the trenches 4A to 4C through an oxidation process, and a high temperature low pressure oxide film 6 is formed on the upper surface of the structure and then heat treated. The substrate is planarized by chemical mechanical polishing (CMP) until the buffer oxide film 2 in the active region is exposed.
그리고, 도1c에 도시한 바와같이 상기 노출된 버퍼산화막(2)을 통해 반도체기판(1)의 액티브영역 내에 불순물이온을 주입하여 웰(7)을 형성하고, 문턱전압 조절을 위한 불순물영역(8)을 형성한다.As shown in FIG. 1C, the well 7 is formed by implanting impurity ions into the active region of the semiconductor substrate 1 through the exposed buffer oxide film 2, and the impurity region 8 for controlling the threshold voltage is formed. ).
그리고, 도1d에 도시한 바와같이 상기 노출된 버퍼산화막(2)을 제거하고, 그 구조물의 상부전면에 게이트산화막(9), 도핑된 폴리실리콘(10), WSix막(11), 캡산화막(12) 및 캡질화막(13)을 순차적으로 형성한 후, 제1게이트(first gate : FG) 마스크(미도시)를 통해 패터닝하여 셀영역과 주변영역 상에 제1게이트를 형성하고, 주변영역의 제1게이트를 마스크로 적용하여 불순물이온을 할로(halo) 주입함으로써, 주변영역의 액티브영역 내에 저농도 영역(14)을 형성한다.As shown in FIG. 1D, the exposed buffer oxide film 2 is removed, and the gate oxide film 9, the doped polysilicon 10, the WSix film 11, and the cap oxide film ( 12) and the cap nitride layer 13 are sequentially formed, and then patterned through a first gate (FG) mask (not shown) to form a first gate on the cell region and the peripheral region. By implanting impurity ions halo by applying the first gate as a mask, the low concentration region 14 is formed in the active region of the peripheral region.
그리고, 상기 셀영역과 주변영역의 상부전면에 절연막(15)을 형성하고, 주변영역에 형성된 절연막(15)을 선택적으로 식각하여 주변영역 제1게이트의 측면에 게이트측벽(16)을 형성한 후, 셀영역과 주변영역의 제1게이트를 마스크로 적용하여 고농도 불순물이온을 주입함으로써, 액티브영역 내에 소스/드레인(17)을 형성한다.After forming the insulating film 15 on the upper surface of the cell region and the peripheral region, and selectively etching the insulating film 15 formed in the peripheral region to form the gate side wall 16 on the side of the first gate of the peripheral region. The source / drain 17 is formed in the active region by implanting high concentration impurity ions using the first gate of the cell region and the peripheral region as a mask.
그리고, 상기 구조물의 상부전면에 층간절연막(18)을 형성하고, 사진식각공정을 통해 일부를 식각하여 셀영역에 소스/드레인(17)과 각기 접속되는 노드콘택(19) 및 비트라인콘택(20)을 형성함과 아울러 주변영역에 배선을 위한 콘택(21)을 형성한다.The interlayer insulating layer 18 is formed on the upper surface of the structure, and a portion of the interlayer insulating layer 18 is etched through a photolithography process so that the node contact 19 and the bit line contact 20 are respectively connected to the source / drain 17 in the cell region. ) And a contact 21 for wiring in the peripheral area.
그러나, 상기한 바와같은 종래 반도체소자의 제조방법은 전체적인 공정이 복잡한 문제점과; 적층 구조물의 높은 단차로 인해 층간절연막의 식각된 영역에 각각 콘택을 형성하기 위하여 도전물질을 채우기 어려운 문제점과; 층간절연막의 형성시에 수반되는 열공정으로 인해 도핑된 불순물이 확산되어 소자특성에 영향을 미치는 문제점과; 노드콘택과 비트라인콘택의 저항값이 커지는 문제점이 있었다.However, the conventional method of manufacturing a semiconductor device as described above has a problem that the whole process is complicated; Difficulty in filling a conductive material to form contacts in the etched regions of the interlayer insulating film due to the high level of the laminated structure; A problem in which the doped impurities are diffused due to the thermal process involved in the formation of the interlayer dielectric film and thus affect the device characteristics; There is a problem that the resistance value of the node contact and the bit line contact increases.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 제1게이트를 반도체기판 내에 형성하여 측벽 및 층간절연막 형성공정을 생략함으로써, 공정 단순화 및 단차를 최소화함과 아울러 층간절연막의 형성으로 인한 상기 문제점들을 해결하고, 노드콘택과 비트라인콘택의 저항값을 감소시킬 수 있는 반도체소자의 제조방법을 제공하는데 있다.The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to form a first gate in a semiconductor substrate and to omit the sidewall and interlayer insulating film forming process, thereby simplifying the process and minimizing the step. In addition, to solve the above problems due to the formation of the interlayer insulating film, and to provide a method of manufacturing a semiconductor device that can reduce the resistance value of the node contact and the bit line contact.
도1a 내지 도1d는 종래 반도체소자의 제조방법을 보인 수순단면도.1A to 1D are cross-sectional views showing a conventional method for manufacturing a semiconductor device.
도2a 내지 도2g는 본 발명의 일 실시예에 따른 평면도, A-A선 단면도 및 B-B선 단면도로 이루어진 공정수순도.Figures 2a to 2g is a process flow chart consisting of a plan view, a cross-sectional view line A-A and a line B-B according to an embodiment of the present invention.
31:반도체기판 32:버퍼산화막31: semiconductor substrate 32: buffer oxide film
33:질화막 34:절연막33: nitride film 34: insulating film
35:웰 36:문턱전압 조절을 위한 불순물영역35: well 36: impurity region for threshold voltage control
37:엔형 불순물영역 38:게이트산화막37: n-type impurity region 38: gate oxide film
39:도핑된 폴리실리콘 40:WSix막39: doped polysilicon 40: WSix film
41:소스/드레인 42:캡산화막41: source / drain 42: cap oxide film
43:캡질화막 44:도전성 물질43: capsulating film 44: conductive material
FGMASK1,BLMASK1:제1게이트 및 비트라인콘택 마스크FGMASK1, BLMASK1: First Gate and Bitline Contact Mask
FGMASK2,BLMASK2:축소된 제1게이트 및 비트라인콘택 마스크FGMASK2, BLMASK2: Reduced first gate and bitline contact mask
PGIMASK1:피지아이 마스크PGIMASK1: Fiji eye mask
NCMASK1,BCMASK1:축소된 노드콘택 및 비트라인콘택 마스크NCMASK1, BCMASK1: Reduced node contact and bitline contact mask
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 제조방법은 반도체기판의 상부에 버퍼산화막과 질화막을 순차적으로 형성한 후, 질화막 상에 제1게이트 및 비트라인콘택 마스크를 겹치도록 하여 상기 질화막, 버퍼산화막 및 반도체기판을 식각하는 공정과; 상기 식각된 구조물 상에 피지아이(profiled grooving isolation : PGI) 마스크를 형성하여 노출된 영역의 질화막, 산화막 및 반도체기판을 식각하는 공정과; 상기 식각된 구조물 상에 절연막을 형성한 후, 화학기계적 연마하여 반도체기판의 식각된 영역에 절연막을 채우는 공정과; 상기 질화막을 제거한 후, 버퍼산화막 및 절연막을 통해 반도체기판 내에 불순물이온을 주입하여 웰을 형성하는 공정과; 상기 겹쳐진 제1게이트 및 비트라인콘택 마스크의 공간을 축소한 마스크를 이용하여 반도체기판의 식각된 영역에 채워진 절연막을 선택적으로 식각하는 공정과; 상기 구조물에서 셀의 비트라인 콘택지역에 해당하는 반도체기판 내에 엔형 불순물이온을 주입하는 공정과; 상기 절연막이 선택적으로 식각된 영역에 게이트산화막, 도핑된 폴리실리콘 및 WSix막을 순차적으로 형성하고, 화학기계적 연마하여 제1게이트를 형성하는 공정과; 상기 제1게이트가 형성된 반도체기판 상에 고농도 및 저농도 불순물이온을 주입하여 소스/드레인을 형성하는 공정과; 상기 소스/드레인이 형성된 반도체기판 상에 캡산화막과 캡질화막을 순차적으로 형성하는 공정과; 상기 캡질화막 상에 노드콘택 및 비트라인콘택 마스크를 겹치도록 함과 아울러 공간을 축소한 마스크를 형성하여 캡질화막 및 캡산화막을 선택적으로 식각하고, 그 식각된 영역에 도전성 물질을 채우는 공정을 구비하여 이루어지는 것을 특징으로 한다.In the method of manufacturing a semiconductor device as described above, the buffer oxide film and the nitride film are sequentially formed on the semiconductor substrate, and the first gate and the bit line contact mask are overlapped on the nitride film. Etching the nitride film, the buffer oxide film, and the semiconductor substrate; Forming a profiled grooving isolation (PGI) mask on the etched structure to etch the nitride film, oxide film and semiconductor substrate in the exposed region; Forming an insulating film on the etched structure and then chemically mechanically polishing the insulating film on the etched region of the semiconductor substrate; Removing the nitride film and implanting impurity ions into the semiconductor substrate through a buffer oxide film and an insulating film to form a well; Selectively etching the insulating film filled in the etched region of the semiconductor substrate by using a mask in which the spaces of the overlapped first gate and bit line contact masks are reduced; Implanting N-type impurity ions into the semiconductor substrate corresponding to the bit line contact region of the cell in the structure; Sequentially forming a gate oxide film, a doped polysilicon, and a WSix film in a region where the insulating film is selectively etched, and forming a first gate by chemical mechanical polishing; Forming a source / drain by implanting high and low concentration impurity ions onto the semiconductor substrate on which the first gate is formed; Sequentially forming a cap oxide film and a cap nitride film on the semiconductor substrate on which the source / drain is formed; Forming a mask having a reduced space and overlapping the node contact and the bit line contact mask on the cap nitride layer, selectively etching the cap nitride layer and the cap oxide layer, and filling a conductive material in the etched region. Characterized in that made.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법을 첨부한 도2a 내지 도2g의 평면도, A-A선 단면도 및 B-B선 단면도로 이루어진 공정수순도를 일 실시예로 하여 상세히 설명하면 다음과 같다.The process flow chart consisting of the plan view of Figs. 2A to 2G, the A-A cross-sectional view and the B-B cross-sectional view of the semiconductor device manufacturing method according to the present invention as described above will be described in detail as follows.
먼저, 도2a에 도시한 바와같이 반도체기판(31)의 상부에 버퍼산화막(32)과 질화막(33)을 순차적으로 형성한 후, 질화막(33)의 상부에 제1게이트 및 비트라인콘택 마스크(FGMASK1,BLMASK1)를 겹치도록 하여 상기 질화막(33), 버퍼산화막(32) 및 반도체기판(31)을 식각한다. 이때, 식각은 겹쳐진 제1게이트 및 비트라인콘택 마스크(FGMASK1,BLMASK1)를 다크-톤(dark-tone:마스크가 형성되는 영역이 식각됨)으로 사용하여 반도체기판(31)이 1000Å 정도 식각되도록 실시한다.First, as shown in FIG. 2A, the buffer oxide film 32 and the nitride film 33 are sequentially formed on the semiconductor substrate 31, and then the first gate and bit line contact masks are formed on the nitride film 33. The nitride film 33, the buffer oxide film 32, and the semiconductor substrate 31 are etched by overlapping the FGMASK1 and BLMASK1. In this case, the etching is performed by using the overlapping first gate and bit line contact masks FGMASK1 and BLMASK1 as dark-tones (etched regions where the mask is formed) to etch the semiconductor substrate 31 at about 1000Å. do.
그리고, 도2b에 도시한 바와같이 상기 식각된 구조물 상에 피지아이 마스크(PGIMASK1)를 형성하여 노출된 영역의 질화막(33), 산화막(32) 및 반도체기판(31)을 식각한다. 이때, 식각은 다크-톤이 적용된 상기 제1게이트 및 비트라인콘택 마스크(FGMASK1,BLMASK1)와는 반대로 피지아이 마스크(PGIMASK1)가 형성되지 않는 영역이 식각되도록 하여 반도체기판(31)이 3000Å 정도 식각되도록 실시하며, 이에 따라 상기 제1게이트 및 비트라인콘택 마스크(FGMASK1,BLMASK1)와 피지아이 마스크(PGIMASK1)에 의해 반복하여 식각된 영역의 반도체기판(31)은 총 4000Å 정도가 식각된다.As illustrated in FIG. 2B, the nitride film 33, the oxide film 32, and the semiconductor substrate 31 in the exposed region are etched by forming a PIGMASK1 on the etched structure. At this time, the etching is performed to etch the region where the PGIMASK1 is not formed, as opposed to the first gate and the bit line contact masks FGMASK1 and BLMASK1 to which the dark-tone is applied, so that the semiconductor substrate 31 is etched at about 3000Å. As a result, the semiconductor substrate 31 in the region repeatedly etched by the first gate and the bit line contact masks FGMASK1 and BLMASK1 and the PGIMASK1 is etched at a total of about 4000 ns.
그리고, 도2c에 도시한 바와같이 상기 식각된 구조물 상에 절연막(34)을 형성한 후, 화학기계적 연마하여 반도체기판(31)의 식각된 영역에 절연막(34)을 채우고, 상기 질화막(33)을 제거한 다음 버퍼산화막(32) 및 절연막(34)을 통해 반도체기판(31) 내에 불순물이온을 순차적으로 주입하여 웰(35) 및 문턱전압 조절을 위한 불순물영역(36)을 형성한다. 이때, 반도체기판(31)의 식각된 영역에 절연막(34)을 채우는 공정은 먼저, 약한 산화공정을 실시하여 반도체기판(31)의 식각된 영역에 산화박막을 형성한 후, 비로소 절연막(34)으로 산화막을 증착하고, 열처리를 수행한 다음 화학기계적 연마를 실시하는 것이 바람직하다.As shown in FIG. 2C, an insulating film 34 is formed on the etched structure, followed by chemical mechanical polishing to fill the insulating film 34 in the etched region of the semiconductor substrate 31, and the nitride film 33. After removing the impurities, impurity ions are sequentially injected into the semiconductor substrate 31 through the buffer oxide layer 32 and the insulating layer 34 to form the well 35 and the impurity region 36 for controlling the threshold voltage. At this time, the process of filling the insulating film 34 in the etched region of the semiconductor substrate 31 is first performed a weak oxidation process to form an oxide thin film in the etched region of the semiconductor substrate 31, and then the insulating film 34 It is preferable to deposit an oxide film, perform heat treatment, and then perform chemical mechanical polishing.
그리고, 도2d에 도시한 바와같이 상기 겹쳐진 제1게이트 및 비트라인콘택 마스크(FGMASK1,BLMASK1)의 공간을 축소한 마스크(FGMASK2,BLMASK2)를 이용하여 반도체기판(31)의 식각된 영역에 채워진 절연막(34)을 선택적으로 식각한다. 이때, 상기와 마찬가지로 겹쳐진 제1게이트 및 비트라인콘택 마스크(FGMASK1,BLMASK1)의 공간을 축소한 마스크(FGMASK2,BLMASK2)도 다크-톤으로 사용하여 식각을 실시한다.As shown in FIG. 2D, an insulating layer filled in the etched region of the semiconductor substrate 31 using the masks FGMASK2 and BLMASK2 which have reduced the space of the overlapped first gate and bit line contact masks FGMASK1 and BLMASK1. (34) is selectively etched. At this time, the masks FGMASK2 and BLMASK2 which have reduced the space of the overlapped first gate and bit line contact masks FGMASK1 and BLMASK1 are also used as dark tones to perform etching.
그리고, 도2e에 도시한 바와같이 상기 구조물에서 셀의 비트라인 콘택지역에 해당하는 반도체기판(31) 내에 엔형 불순물이온을 주입하여 엔형 불순물영역(37)을 형성하고, 상기 절연막(34)이 선택적으로 식각된 영역에 게이트산화막(38), 도핑된 폴리실리콘(39) 및 WSix막(40)을 순차적으로 형성하고, 화학기계적 연마하여 제1게이트를 형성한다.As shown in FIG. 2E, the N-type impurity ions are implanted into the semiconductor substrate 31 corresponding to the bit line contact region of the cell to form the N-type impurity region 37, and the insulating film 34 is selectively selected. The gate oxide film 38, the doped polysilicon 39, and the WSix film 40 are sequentially formed in the etched region, and the first gate is formed by chemical mechanical polishing.
그리고, 도2f에 도시한 바와같이 상기 제1게이트가 형성된 반도체기판(31) 상에 고농도 및 저농도 불순물이온을 순차적으로 주입하여 소스/드레인(41)을 형성한 후, 반도체기판(31) 상에 캡산화막(42)과 캡질화막(43)을 순차적으로 형성한다. 이때, 상기 저농도 불순물이온은 경사이온주입(halo)을 적용하여 소스/드레인(41)을 엘디디(lightly doped drain : LDD)구조로 형성한 후, 열처리를 실시하는 것이 바람직하다.As shown in FIG. 2F, a high concentration and a low concentration of impurity ions are sequentially injected onto the semiconductor substrate 31 on which the first gate is formed to form a source / drain 41, and then on the semiconductor substrate 31. The cap oxide film 42 and the cap nitride film 43 are sequentially formed. In this case, the low concentration impurity ions are formed by applying a gradient ion implantation (halo) to form a source / drain 41 in the lightly doped drain (LDD) structure, it is preferable to perform a heat treatment.
그리고, 도2g에 도시한 바와같이 상기 캡질화막(43) 상에 노드콘택 및 비트라인콘택 마스크를 겹치도록 함과 아울러 공간을 축소한 마스크(NCMASK1,BCMASK1)를 형성하여 캡질화막(43) 및 캡산화막(42)을 선택적으로 식각하고, 그 식각된 영역에 도전성 물질(44)을 채운다. 이때, 도전성 물질(44)로는 도핑된 폴리실리콘을 적용할 수 있다.As shown in FIG. 2G, the cap contact film 43 and the cap are formed by overlapping the node contact and the bit line contact mask on the cap nitride film 43 and reducing the spaces of the mask NCMASK1 and BCMASK1. The oxide film 42 is selectively etched, and the conductive material 44 is filled in the etched region. In this case, the doped polysilicon may be applied to the conductive material 44.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 제1게이트를 반도체기판 내에 형성하여 측벽 및 층간절연막 형성공정을 생략함으로써, 종래에 비해 공정 단순화 및 단차를 최소화함과 아울러 층간절연막의 형성으로 인한 소자특성이 나빠지는 종래의 문제를 해결할 수 있으며, 이에 따라 노드콘택과 비트라인콘택의 저항값을 감소시킬 수 있는 효과가 있다.The method of manufacturing a semiconductor device according to the present invention as described above eliminates the sidewall and interlayer insulating film forming process by forming the first gate in the semiconductor substrate, thereby simplifying the process and minimizing the step difference and forming the interlayer insulating film. The conventional problem of deteriorating device characteristics due to this can be solved, thereby reducing the resistance of the node contact and the bit line contact.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990012328A KR20000065714A (en) | 1999-04-08 | 1999-04-08 | Fabricating method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990012328A KR20000065714A (en) | 1999-04-08 | 1999-04-08 | Fabricating method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000065714A true KR20000065714A (en) | 2000-11-15 |
Family
ID=19579124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990012328A KR20000065714A (en) | 1999-04-08 | 1999-04-08 | Fabricating method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000065714A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116110920A (en) * | 2023-02-20 | 2023-05-12 | 湖北江城芯片中试服务有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
-
1999
- 1999-04-08 KR KR1019990012328A patent/KR20000065714A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116110920A (en) * | 2023-02-20 | 2023-05-12 | 湖北江城芯片中试服务有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100370129B1 (en) | Semiconductor Device and Method for the Same | |
| KR20000075409A (en) | Method of Forming T-Shape Isolation Layer, Method of Elevated Salicide Source/Drain Region Using thereof and Semiconductor Device Having T-Shape Isolation Layer | |
| US5940710A (en) | Method for fabricating metal oxide semiconductor field effect transistor | |
| KR0119961B1 (en) | Fabrication method for capacitor of semiconductor device | |
| US5903013A (en) | Thin film transistor and method of manufacturing the same | |
| KR100244271B1 (en) | semiconductor device and method for manufacturing the same | |
| KR100341182B1 (en) | Method of forming mos transistor in semiconductor device | |
| KR100273296B1 (en) | Method for fabricating mos transistor | |
| KR0123781B1 (en) | Eprom semiconductor device and the fabricating method thereof | |
| KR20000065714A (en) | Fabricating method of semiconductor device | |
| KR100320436B1 (en) | Method for manufacturing mosfet | |
| KR100273319B1 (en) | Method for fabricating mos transistor | |
| KR20010029029A (en) | Fabricating method of semiconductor device | |
| KR20020011549A (en) | Method of forming a contact plug in a high voltage semiconductor device | |
| KR970053925A (en) | Manufacturing Method of Flash Memory Cell | |
| KR20030053959A (en) | Method for fabricating semiconductor device | |
| KR100261991B1 (en) | Manufacturing method for transistor of semiconductor memory cell and its structure | |
| KR100316526B1 (en) | Method for forming gate of semiconductor memory | |
| KR100305205B1 (en) | Method for manufacturing semiconductor device | |
| KR0136920B1 (en) | Manufacturing method of semiconductor device | |
| KR100235943B1 (en) | Method of manufacturing tansistor of semiconductor device | |
| KR100752191B1 (en) | Method of fabricating a mosfet | |
| KR940010923B1 (en) | Mosfet and manufacturing method thereof | |
| KR20000031758A (en) | Method for producing semiconductor device | |
| KR20000003980A (en) | Transistor of semiconductor devices and method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| N231 | Notification of change of applicant | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |