KR19990033109A - Method of manufacturing dual gate of semiconductor device - Google Patents
Method of manufacturing dual gate of semiconductor device Download PDFInfo
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- KR19990033109A KR19990033109A KR1019970054366A KR19970054366A KR19990033109A KR 19990033109 A KR19990033109 A KR 19990033109A KR 1019970054366 A KR1019970054366 A KR 1019970054366A KR 19970054366 A KR19970054366 A KR 19970054366A KR 19990033109 A KR19990033109 A KR 19990033109A
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- South Korea
- Prior art keywords
- oxide film
- polysilicon
- gate
- nitride film
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 230000009977 dual effect Effects 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 41
- 229920005591 polysilicon Polymers 0.000 claims abstract description 41
- 150000004767 nitrides Chemical class 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 24
- -1 nitrogen ions Chemical class 0.000 claims abstract description 22
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 21
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 20
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910001930 tungsten oxide Inorganic materials 0.000 claims abstract description 15
- 238000000206 photolithography Methods 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
Abstract
본 발명은 반도체소자의 듀얼게이트 제조방법에 관한 것으로, 종래에는 듀얼게이트의 게이트산화막 두께가 일정하기 때문에 각 반도체소자의 동작전압을 서로 다르게 인가하기가 어려운 문제점이 있었다. 이와같은 문제점을 감안한 본 발명은 반도체기판의 상부에 제1산화막과 도핑되지 않은 폴리실리콘을 차례로 증착한 후, 그 도핑되지 않은 폴리실리콘에 질소이온을 주입하는 단계와; 사진식각공정을 이용하여 상기 질소이온이 주입된 폴리실리콘의 일부를 식각한 후, 열처리를 통해 상기 질소이온을 확산시켜 폴리실리콘 하부의 반도체기판에 제1질화막을 형성하는 단계와; 상기 질소이온이 주입된 폴리실리콘과 제1산화막을 제거한 후, 산화공정을 통해 반도체기판 및 제1질화막의 상부에 제2산화막을 형성하는 단계와; 상기 제2산화막의 상부에 도핑된 폴리실리콘, 텅스텐산화막, 제2질화막을 차례로 증착한 후, 사진식각공정을 통해 제2질화막, 텅스텐산화막, 도핑된 폴리실리콘, 제2산화막의 일부를 순차적으로 식각하여 게이트를 형성하는 단계로 이루어지는 반도체소자의 듀얼게이트 제조방법을 통해 듀얼게이트의 게이트산화막을 서로다른 두께로 형성시킴으로써, 서로다른 동작전압을 필요로 하는 반도체소자의 제조가 편리한 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a dual gate of a semiconductor device. In the related art, since the gate oxide film thickness of the dual gate is constant, it is difficult to apply different operating voltages of the semiconductor devices. In view of the above problems, the present invention includes the steps of depositing a first oxide film and undoped polysilicon on top of a semiconductor substrate, and then injecting nitrogen ions into the undoped polysilicon; Etching a portion of the polysilicon into which the nitrogen ions have been implanted using a photolithography process, and then diffusing the nitrogen ions through heat treatment to form a first nitride film on the semiconductor substrate under the polysilicon; Removing the polysilicon and the first oxide film into which the nitrogen ion is injected, and then forming a second oxide film on the semiconductor substrate and the first nitride film through an oxidation process; After depositing the doped polysilicon, tungsten oxide film, and the second nitride film on top of the second oxide film in sequence, a portion of the second nitride film, tungsten oxide film, doped polysilicon, second oxide film is sequentially etched through a photolithography process By forming the gate oxide film of the dual gate to have a different thickness through the method of manufacturing a dual gate of the semiconductor device comprising the step of forming a gate, it is convenient to manufacture a semiconductor device requiring a different operating voltage.
Description
본 발명은 반도체소자의 듀얼(dual)게이트 제조방법에 관한 것으로, 특히 게이트에 인가되는 서로다른 동작전압에 따른 게이트산화막의 신뢰성을 향상시키기에 적당하도록 한 반도체소자의 듀얼게이트 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a dual gate of a semiconductor device, and more particularly, to a method of manufacturing a dual gate of a semiconductor device suitable for improving the reliability of a gate oxide film according to different operating voltages applied to a gate.
종래 반도체소자의 듀얼게이트 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.A method of manufacturing a dual gate of a conventional semiconductor device will be described in detail with reference to the accompanying drawings.
도1a 내지 도1b는 종래 반도체소자의 듀얼게이트 제조방법을 보인 수순단면도로서, 이에 도시한 바와같이 반도체기판(1)의 상부에 순차적으로 산화막(2), 도핑된 폴리실리콘(3), 텅스텐산화막(4)과 질화막(5)을 증착하는 단계(도1a)와; 사진식각공정을 통해 질화막(5), 텅스텐산화막(4), 도핑된 폴리실리콘(3), 산화막(2)의 일부를 기판(1)의 일부가 노출되도록 식각하여 게이트를 형성하는 단계(도1b)로 이루어지며, 이후 노출된 기판(1)에 저농도의 불순물이온을 주입하여 저농도의 소스/드레인영역을 형성하고, 게이트의 측면에 측벽을 형성한 후, 기판(1)에 고농도의 불순물이온을 주입하여 고농도의 소스/드레인영역을 형성하는 순서로 진행된다. 이하, 상기한 바와같은 종래 반도체소자의 듀얼게이트 제조방법을 좀더 상세히 설명한다.1A to 1B are cross-sectional views showing a method of manufacturing a dual gate of a conventional semiconductor device. As shown in FIG. 1, the oxide film 2, the doped polysilicon 3, and the tungsten oxide film are sequentially formed on the semiconductor substrate 1. (4) and depositing a nitride film 5 (FIG. 1A); Etching a portion of the substrate 1 by exposing the nitride film 5, the tungsten oxide film 4, the doped polysilicon 3, and the oxide film 2 through a photolithography process (FIG. 1B). Then, low concentration of impurity ions are implanted into the exposed substrate 1 to form a low concentration source / drain region, and sidewalls are formed on the side of the gate, and then high concentration of impurity ions are applied to the substrate 1. Injection is performed in order to form a high concentration source / drain region. Hereinafter, a method of manufacturing a dual gate of a conventional semiconductor device as described above will be described in more detail.
먼저, 도1a에 도시한 바와같이 반도체기판(1)의 상부에 순차적으로 산화막(2), 도핑된 폴리실리콘(3), 텅스텐산화막(4)과 질화막(5)을 증착한다. 이때, 질화막(5)을 증착하는 이유는 이후의 공정에서 게이트를 셀프얼라인(self align)하여 이온주입공정을 통해 소스/드레인영역을 형성할 때, 게이트에 불순물이온이 주입되는 것을 방지하기 위해서이다.First, as shown in FIG. 1A, an oxide film 2, a doped polysilicon 3, a tungsten oxide film 4, and a nitride film 5 are sequentially deposited on the semiconductor substrate 1. In this case, the reason for depositing the nitride film 5 is to prevent impurity ions from being injected into the gate when the source / drain region is formed through the ion implantation process by self-aligning the gate in a subsequent process. to be.
그리고, 도1b에 도시한 바와같이 사진식각공정을 통해 질화막(5), 텅스텐산화막(4), 도핑된 폴리실리콘(3), 산화막(2)의 일부를 기판(1)의 일부가 노출되도록 식각하여 게이트를 형성한다.As shown in FIG. 1B, a portion of the substrate 1 is etched by exposing a portion of the nitride film 5, the tungsten oxide film 4, the doped polysilicon 3, and the oxide film 2 through a photolithography process. To form a gate.
상기한 바와같이 제조되는 반도체소자는 게이트에 인가되는 전압이 증가함에 따라 축적(accumulation), 공핍(depletion), 약/강 반전(weak/strong inversion)을 거쳐 채널이 형성되고, 게이트에 인가되는 전압이 더욱 증가하면 드레인영역 근처에서 채널이 핀치오프(pinch-off)되고, 공핍층이 확대되어 핀치오프점과 드레인영역사이의 공핍층에는 수평방향의 전계가 형성되며, 이 전계에 의해 캐리어(carrier)는 채널로부터 드레인쪽으로 끌려간다. 따라서, 소스와 드레인사이에 존재하는 동작영역이 소자의 선형, 포화영역으로 구분되어 반도체소자는 스위칭특성을 지니게 된다.In the semiconductor device fabricated as described above, as the voltage applied to the gate increases, a channel is formed through accumulation, depletion, weak / strong inversion, and the voltage applied to the gate. Further increasing, the channel is pinched off near the drain region, the depletion layer is enlarged, and a horizontal electric field is formed at the depletion layer between the pinch off point and the drain region. ) Is pulled from the channel towards the drain. Therefore, the operation region existing between the source and the drain is divided into linear and saturation regions of the device, so that the semiconductor device has switching characteristics.
그러나, 상기한 바와같이 제조되는 종래 반도체소자의 듀얼게이트 제조방법은 듀얼게이트의 게이트산화막 두께가 일정하기 때문에 각 반도체소자의 동작전압을 서로 다르게 인가하기가 어려운 문제점이 있었다.However, the conventional method of manufacturing a dual gate of a semiconductor device manufactured as described above has a problem that it is difficult to apply different operating voltages of the semiconductor devices because the thickness of the gate oxide film of the dual gate is constant.
본 발명은 상기한 바와같은 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 듀얼게이트의 게이트산화막을 서로다른 두께로 증착시킬 수 있는 반도체소자의 듀얼게이트 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a dual gate of a semiconductor device capable of depositing a gate oxide film of the dual gate at different thicknesses.
도1은 종래 반도체소자의 듀얼게이트 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a method of manufacturing a dual gate of a conventional semiconductor device.
도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
11:반도체기판 12:산화막11: semiconductor substrate 12: oxide film
13,16:폴리실리콘 14,18:질화막13,16 polysilicon 14,18 nitride film
15:산화막 17:텅스텐산화막15: oxide film 17: tungsten oxide film
N-:질소이온N -: nitrogen ions
상기한 바와같은 본 발명의 목적은 반도체기판의 상부에 제1산화막과 도핑되지 않은 폴리실리콘을 차례로 증착한 후, 그 도핑되지 않은 폴리실리콘에 질소이온을 주입하는 단계와; 사진식각공정을 이용하여 상기 질소이온이 주입된 폴리실리콘의 일부를 식각한 후, 열처리를 통해 상기 질소이온을 확산시켜 폴리실리콘 하부의 반도체기판에 제1질화막을 형성하는 단계와; 상기 질소이온이 주입된 폴리실리콘과 제1산화막을 제거한 후, 산화공정을 통해 반도체기판 및 제1질화막의 상부에 제2산화막을 형성하는 단계와; 상기 제2산화막의 상부에 도핑된 폴리실리콘, 텅스텐산화막, 제2질화막을 순차적으로 증착한 후, 사진식각공정을 통해 제2질화막, 텅스텐산화막, 도핑된 폴리실리콘, 제2산화막의 일부를 순차적으로 식각하여 게이트를 형성하는 단계로 이루어짐으로써 달성되는 것으로, 본 발명에 의한 반도체소자의 듀얼게이트 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.An object of the present invention as described above comprises the steps of depositing a first oxide film and undoped polysilicon on top of a semiconductor substrate, and then injecting nitrogen ions into the undoped polysilicon; Etching a portion of the polysilicon into which the nitrogen ions have been implanted using a photolithography process, and then diffusing the nitrogen ions through heat treatment to form a first nitride film on the semiconductor substrate under the polysilicon; Removing the polysilicon and the first oxide film into which the nitrogen ion is injected, and then forming a second oxide film on the semiconductor substrate and the first nitride film through an oxidation process; After sequentially depositing the doped polysilicon, tungsten oxide film, and the second nitride film on the second oxide film, a portion of the second nitride film, tungsten oxide film, doped polysilicon, second oxide film sequentially through a photolithography process It is achieved by the step of forming a gate by etching, described in detail with reference to the accompanying drawings, a method for manufacturing a dual gate of a semiconductor device according to the present invention.
도2a 내지 도2d는 본 발명의 일 실시예를 보인 수순단면도로서, 이에 도시한 바와같이 반도체기판(11)의 상부에 산화막(12)과 도핑되지 않은 폴리실리콘(13)을 차례로 증착한 후, 그 도핑되지 않은 폴리실리콘(13)에 질소이온(N-)을 주입하는 단계(도2a)와; 사진식각공정을 이용하여 질소이온(N-)이 주입된 폴리실리콘(13)의 일부를 식각한 후, 열처리를 통해 질소이온(N-)을 확산시켜 폴리실리콘(13) 하부의 반도체기판(11)에 질화막(14)을 형성하는 단계(도2b)와; 그 질소이온(N-)이 주입된 폴리실리콘(13)과 산화막(12)을 제거한 후, 산화공정을 통해 반도체기판(11) 및 질화막(14)의 상부에 산화막(15)을 형성하는 단계(도2c)와; 그 산화막(15)의 상부에 도핑된 폴리실리콘(16), 텅스텐산화막(17), 질화막(18)을 순차적으로 증착한 후, 사진식각공정을 통해 질화막(18), 텅스텐산화막(17), 도핑된 폴리실리콘(16), 산화막(15)의 일부를 순차적으로 식각하여 게이트를 형성하는 단계(도2d)로 이루어진다. 이하, 상기한 바와같은 본 발명의 일 실시예를 좀더 상세히 설명한다.2A to 2D are cross-sectional views showing an embodiment of the present invention. As shown therein, an oxide film 12 and an undoped polysilicon 13 are sequentially deposited on an upper portion of the semiconductor substrate 11. nitrogen ions (N -) for the non-doped polysilicon (13) step (Fig. 2a) for injecting and; After etching a part of the polysilicon 13 into which the nitrogen ions (N − ) are injected using a photolithography process, the semiconductor substrate 11 under the polysilicon 13 is diffused by diffusing nitrogen ions (N − ) through heat treatment. Forming a nitride film 14 (Fig. 2B); Removing the polysilicon 13 and the oxide film 12 into which the nitrogen ions (N − ) are injected, and then forming an oxide film 15 on the semiconductor substrate 11 and the nitride film 14 through an oxidation process ( 2c); The doped polysilicon 16, tungsten oxide film 17, and nitride film 18 are sequentially deposited on the oxide film 15, and then the nitride film 18, tungsten oxide film 17, and doping are performed through a photolithography process. A portion of the polysilicon 16 and the oxide film 15 are sequentially etched to form a gate (FIG. 2D). Hereinafter, an embodiment of the present invention as described above will be described in more detail.
먼저, 도2a에 도시한 바와같이 반도체기판(11)의 상부에 산화막(12)과 도핑되지 않은 폴리실리콘(13)을 차례로 증착한 후, 그 도핑되지 않은 폴리실리콘(13)에 질소이온(N-)을 주입한다. 이때, 산화막(12)은 도핑되지 않은 폴리실리콘(13)에 질소이온(N-)을 주입할 때, 반도체기판(11)의 손상을 방지하기 위한 버퍼의 기능을 한다.First, as shown in FIG. 2A, an oxide film 12 and an undoped polysilicon 13 are sequentially deposited on the semiconductor substrate 11, and then nitrogen ions (N) are deposited on the undoped polysilicon 13. - ) At this time, the oxide film 12 functions as a buffer to prevent damage to the semiconductor substrate 11 when nitrogen ions N − are injected into the undoped polysilicon 13.
그리고, 도2b에 도시한 바와같이 사진식각공정을 이용하여 질소이온(N-)이 주입된 폴리실리콘(13)의 일부를 식각한 후, 열처리를 통해 질소이온(N-)을 확산시켜 폴리실리콘(13) 하부의 반도체기판(11)상에 질화막(14)을 형성한다.As shown in FIG. 2B, after etching a part of the polysilicon 13 into which the nitrogen ions (N − ) are injected using a photolithography process, the silicon ions are diffused through heat treatment to diffuse the polysilicon (N − ). (13) A nitride film 14 is formed on the lower semiconductor substrate 11.
그리고, 도2c에 도시한 바와같이 질소이온(N-)이 주입된 폴리실리콘(13)과 산화막(12)을 제거한 후, 산화공정을 통해 반도체기판(11) 및 질화막(14)의 상부에 산화막(15)을 형성한다. 이때, 반도체기판(11) 및 질화막(14)의 상부에 형성되는 산화막(15)은 그 질화막(14)의 영향으로 인해 서로다른 두께를 지닌다.As shown in FIG. 2C, after removing the polysilicon 13 and the oxide film 12 into which the nitrogen ions N − are injected, the oxide film is formed on the semiconductor substrate 11 and the nitride film 14 through an oxidation process. (15) is formed. At this time, the oxide film 15 formed on the semiconductor substrate 11 and the nitride film 14 has different thicknesses due to the influence of the nitride film 14.
그리고, 도2d에 도시한 바와같이 산화막(15)의 상부에 도핑된 폴리실리콘(16), 텅스텐산화막(17), 질화막(18)을 순차적으로 증착한 후, 사진식각공정을 통해 질화막(18), 텅스텐산화막(17), 도핑된 폴리실리콘(16), 산화막(15)의 일부를 순차적으로 식각하여 게이트를 형성한다. 이때, 질화막(18)을 증착하는 이유는 종래와 동일하게 게이트에 불순물이온이 주입되는 것을 방지하기 위해서이다.As shown in FIG. 2D, the doped polysilicon 16, the tungsten oxide film 17, and the nitride film 18 are sequentially deposited on the oxide film 15, and then the nitride film 18 is subjected to a photolithography process. A portion of the tungsten oxide film 17, the doped polysilicon 16, and the oxide film 15 are sequentially etched to form a gate. At this time, the reason for depositing the nitride film 18 is to prevent impurity ions from being injected into the gate as in the prior art.
상기한 바와같이 제조되는 본 발명에 의한 반도체소자의 듀얼게이트 제조방법은 듀얼게이트의 게이트산화막을 서로다른 두께로 형성시킴으로써, 서로다른 동작전압을 필요로 하는 반도체소자의 제조가 편리한 효과가 있다.The method of manufacturing a dual gate of a semiconductor device according to the present invention manufactured as described above is advantageous in that it is convenient to manufacture semiconductor devices requiring different operating voltages by forming gate oxide films having different thicknesses.
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| KR100911103B1 (en) * | 2002-12-26 | 2009-08-06 | 매그나칩 반도체 유한회사 | Method of manufacturing a semiconductor device |
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| KR100911103B1 (en) * | 2002-12-26 | 2009-08-06 | 매그나칩 반도체 유한회사 | Method of manufacturing a semiconductor device |
| KR100671161B1 (en) * | 2004-12-29 | 2007-01-17 | 동부일렉트로닉스 주식회사 | Method for Cleaning a Wafer |
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