KR100249194B1 - Fabricating method of a self aligned mesfet - Google Patents
Fabricating method of a self aligned mesfet Download PDFInfo
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- KR100249194B1 KR100249194B1 KR1019960054394A KR19960054394A KR100249194B1 KR 100249194 B1 KR100249194 B1 KR 100249194B1 KR 1019960054394 A KR1019960054394 A KR 1019960054394A KR 19960054394 A KR19960054394 A KR 19960054394A KR 100249194 B1 KR100249194 B1 KR 100249194B1
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 26
- 150000002500 ions Chemical class 0.000 claims abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000009792 diffusion process Methods 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 3
- 150000001875 compounds Chemical class 0.000 claims abstract 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- -1 silicon ion Chemical class 0.000 description 3
- 239000007769 metal material Substances 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32105—Oxidation of silicon-containing layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3211—Nitridation of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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Abstract
MESFET 제조방법에 관한 것으로, 화합물 반도체 기판에 활성층을 형성하고 기판 상의 일정영역에 게이트 전극을 형성한 후, 게이트 전극을 포함한 기판 전면에 제 1실리콘산화막을 형성하고, 제 1실리콘산화막의 일정영역을 제거하여 게이트 전극의 양측면에 제 1실리콘산화막을 남긴 다음, 기판 상에 제 2실리콘산화막 및 실리콘질화막을 차레로 형성하여 이온확산공정으로 기판 표면내에 소오스 영역 및 드레인 영역을 형성한 후, 제 1, 제 2실리콘산화막 및 실리콘질화막을 제거하고 소오스 영역과 드레인 영역상에 소오스 전극 및 드레인 전극을 형성함으로써 게이트-드레인 항복전압을 높이고 게이트-소오스 저항을 줄일 수 있고, 공정을 단순화하고 공정가를 줄일 수 있다.A method of manufacturing a MESFET includes forming an active layer on a compound semiconductor substrate, forming a gate electrode on a predetermined region of the substrate, forming a first silicon oxide film on the entire surface of the substrate including the gate electrode, Removing the first silicon oxide film on both sides of the gate electrode, forming a second silicon oxide film and a silicon nitride film on the substrate in a molten state, forming a source region and a drain region in the surface of the substrate by an ion diffusion process, The second silicon oxide film and the silicon nitride film are removed and the source electrode and the drain electrode are formed on the source region and the drain region, the gate-drain breakdown voltage can be increased and the gate-source resistance can be reduced, and the process can be simplified and the process cost can be reduced .
Description
본 발명은 MESFET(Metal Semiconductor Field Ettect Transistor)에 관한 것으로, 특히 이온확산공정을 이용한 LDD(Lightly Doped Drain) 구조를 갖는 자기정렬형 MESFET 제조방법에 관한 것이다.The present invention relates to a MESFET (Metal Semiconductor Field Ettect Transistor), and more particularly, to a self-aligned MESFET having an LDD (Lightly Doped Drain) structure using an ion diffusion process.
일반적으로 MESFET 은 결정성장(epitaxy)층을 이용한 MESFET과 이온주입 공정을 이용한 MESFET 등이 있다.Generally, MESFETs include MESFETs using a crystal growth (epitaxy) layer and MESFETs using an ion implantation process.
그리고, MESFET은 보다 높은 게이트-드레인 항복전압(breakdown voltage)과 보다 낮은 게이트-소오스 저항을 얻기 위하여 LDD(Lightly Doped Drain)구조를 이용하고 있다.And MESFETs use LDD (Lightly Doped Drain) structure to obtain higher gate-drain breakdown voltage and lower gate-source resistance.
이하, 첨부된 도면을 참조하여 종래 기술에 다른 MESFET 제조방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a MESFET according to the related art will be described with reference to the accompanying drawings.
도 1a 내지 1d는 종래 기술에 따른 MESFET의 제조공정을 보여주는 공정단면도이다.1A to 1D are process sectional views showing a manufacturing process of a conventional MESFET.
도 1a에 도시된 바와 같이, 반절연성 GaAS 기판(10)상에 활성영역을 정의하고 1차 이온주입공정으로 활성영역에 이온(Si)을 주입하여 기판(10) 표면내에 활성층(11)을 형성한다.1A, an active region is defined on a semi-insulating GaAs substrate 10, and ions (Si) are injected into an active region by a primary ion implantation process to form an active layer 11 in the surface of the substrate 10 do.
그리고, 기판(10) 상에 게이트 금속물질을 형성하고 패터닝하여 기판(10) 상의 일정영역에 게이트 전극(12)을 형성한다.Then, a gate metal material is formed on the substrate 10 and patterned to form the gate electrode 12 in a certain region on the substrate 10. [
이어, 도 1b에 도시된 바와 같이 게이트 전극(12)을 마스크로 하여 2차 이온 주입공정으로 기판(10)에 이온(Si)을 주입하여 저농도 소오스 영역(13) 및 저농도 드레인 영역(14)을 형성한다.1B, ions (Si) are injected into the substrate 10 by a secondary ion implantation process using the gate electrode 12 as a mask to form a low concentration source region 13 and a low concentration drain region 14 .
이때, 저농도 소오스 영역(13) 및 저농도 드레인 영역(14)은 활성층(11) 형성시의 이온주입량보다 더 많은 이온이 주입된다.At this time, the lightly doped source region 13 and the lightly doped drain region 14 are implanted with ions larger than the amount of ions implanted when the active layer 11 is formed.
그리고, 도 1c에 도시된 바와 같이 게이트 전극(12)을 포함한 기판(10) 전면에 실리콘 옥시 나이트라이드(SiON)(15)를 형성하고 제 3차 이온주입공정으로 기판(10)에 이온(Si)을 주입하여 고농도 소오스 영역(16) 및 고농도 드레인 영역(17)을 형성한다.Silicon oxynitride (SiON) 15 is formed on the entire surface of the substrate 10 including the gate electrode 12 as shown in FIG. 1C, and ions (Si Concentration source region 16 and the heavily doped drain region 17 are formed.
이어, 도 1d에 도시된 바와 같이 실리콘 옥시 나이트라이드(15)의 일정영역을 제거하여 고농도 소오스 영역(16) 및 고농도 드레인 영역(17)을 노출시킨 다음 노출된 영역에 소오스 전극(18) 및 드레인 전극(19)을 형성하여 LDD(Lightly Doped Drain)구조를 갖는 자기정렬형 MESFET을 완성한다.1D, a certain region of the silicon oxynitride 15 is removed to expose the high concentration source region 16 and the high concentration drain region 17, and then the source electrode 18 and drain Electrode 19 is formed to complete a self-aligned MESFET having an LDD (Lightly Doped Drain) structure.
이와 같이 LDD 구조를 갖도록 자기정렬형 MESFET을 제조하는 이유는 게이트-드레인 항볼전압을 높일 수 있고 게이트-소오스 저항을 크게 낮출 수 있기 때문이다.The reason for manufacturing the self-aligned MESFET having the LDD structure is that the gate-drain voltage can be increased and the gate-source resistance can be greatly reduced.
종래 기술에 따른 자기정렬형 MESFET 제조방법은 3번의 이온주입공정이 필요하므로 공정이 복잡한 문제점이 있다.The self-aligned MESFET fabrication method according to the related art has a problem in that the process is complicated because three ion implantation processes are required.
또한, 이온주입을 위해 고가의 이온주입장비를 이용하여야 하므로 공정가가 비싼 문제점이 있다.In addition, expensive ion implantation equipment must be used for ion implantation, which is expensive.
본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로서, 본 발명의 목적은 이온확산공정을 이용하여 게이트-드레인 항복전압을 높이고, 게이트-소오스 저항을 줄일 수 있는 자기저항형 MESFET 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION It is an object of the present invention to provide a magnetoresistance MESFET fabrication method capable of increasing a gate-drain breakdown voltage and reducing a gate-source resistance by using an ion diffusion process have.
도 1a 내지 1d는 종래 기술에 따른 자기정렬형 MESFET의 제조공정을 보여주는 공정단면도,FIGS. 1A to 1D are process cross-sectional views illustrating a manufacturing process of a self-aligned MESFET according to the prior art,
도 2a 내지 2d는 본 발명에 따른 자기정렬형 MESFET의 제조공정을 보여주는 공정단면도이다.FIGS. 2A to 2D are process cross-sectional views illustrating a manufacturing process of a self-aligned MESFET according to the present invention.
*도면의 주요부분에 대한 부호의 설명*Description of the Related Art [0002]
20:기판21:활성층20: substrate 21: active layer
22:게이트 전극23:제 1실리콘산화막22: gate electrode 23: first silicon oxide film
24:제 2실리콘산화막25:실리콘질화막24: second silicon oxide film 25: silicon nitride film
26:저농도 소오스 영역27:고농도 소오스영역26: low concentration source region 27: high concentration source region
28:저농도 드레인29:고농도 드레인 영역28: lightly doped drain 29: heavily doped drain region
30:소오스 전극31:드레인 전극30: source electrode 31: drain electrode
이와 같은 목적을 달성하기 위한 본 발명에 따른 자기정렬형 MESFET 제조방법 기판 상에 실리콘산화막 및 실리콘질화막을 형성한 후 단 한번의 이온확산공정을 이용하여 게이트-소오스, 게이트-드레인 간격을 일정하게 형성하는 자기정렬형 MESFET를 제조함을 특징으로 한다.In order to achieve the above object, a self-aligned MESFET fabrication method according to the present invention includes forming a silicon oxide film and a silicon nitride film on a substrate, forming a gate-source and a gate- And a self-aligned MESFET.
이하, 본 발명에 따른 자기정렬형 MESFET 제조방법의 바람직한 실시예를 첨부한 도면을 참조하여 설명하면 다음과 같다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of a self-aligned MESFET fabrication method according to the present invention will be described with reference to the accompanying drawings.
도 2a 내지 2d는 본 발명에 따른 자기정렬형 MESFET의 제조공정을 보여주는 공정단면도이다.FIGS. 2A to 2D are process cross-sectional views illustrating a manufacturing process of a self-aligned MESFET according to the present invention.
도 2a에 도시된 바와 같이, 반절연성 GaAs 기판(20) 상에 활성영역을 정의하고 이온주입공정으로 활성영역에 이온(Si)을 주입하여 기판(20) 표면내에 활성층(21)을 형성한다.2A, an active region is defined on a semi-insulating GaAs substrate 20 and ions (Si) are implanted into an active region through an ion implantation process to form an active layer 21 in the surface of the substrate 20. [
그리고, 기판(21)상에 게이트 금속물질을 형성하고 패터닝하여 기판(21)상의 일정영역에 게이트 전극(22)을 형성한다.Then, a gate metal material is formed on the substrate 21 and patterned to form the gate electrode 22 in a predetermined region on the substrate 21. [
이어, 게이트 전극(22)을 포함한 반절연성 GaAs 기판(20)상에 제 1실리콘산화막(SiOx) (23)을 형성한다.Next, a first silicon oxide film (SiOx) 23 is formed on the semi-insulating GaAs substrate 20 including the gate electrode 22.
이어, 도 2b에 도시돤 바와 같이, 제 1실리콘산화막(SiOx) (23)을 건식식각으로 활성층(21) 및 게이트 전극(22)의 상면이 노출되도록 제거하여 게이트 전극(22)의 양측면에 제 1실리콘산화막(23)을 남긴다.2B, the first silicon oxide film (SiOx) 23 is removed by dry etching to expose the upper surface of the active layer 21 and the gate electrode 22, thereby forming a gate electrode 22 on both sides of the gate electrode 22. Next, as shown in FIG. 1 silicon oxide film 23 is left.
이어, 도 2c에 도시된 바와 같이, 게이트 전극(22)을 포함한 기판(20) 전면에 제 2실리콘산화막(SiOx) (24)을 형성한다.2C, a second silicon oxide film (SiOx) 24 is formed on the entire surface of the substrate 20 including the gate electrode 22. Next, as shown in FIG.
그리고, 제 2실리콘산화막(24) 상에 실리콘질화막(SiNx) (25)을 형성한다.Then, a silicon nitride film (SiNx) 25 is formed on the second silicon oxide film 24.
이때, 실리콘질화막(25)을 형성하는 이유는 제 2실리콘산화막(24)의 실리콘 이온이 기판(20)으로 확산이 잘되도록 촉매적인 역할을 하기 때문이다.The reason for forming the silicon nitride film 25 at this time is that the silicon ion of the second silicon oxide film 24 serves as a catalyst so that diffusion of the silicon ions into the substrate 20 is facilitated.
그리고, 도 2d에 도시한 바와 같이, 단한번의 이온확산공정으로 제 2실리콘 산화막(24) 및 실리콘질화막(25)의 실리콘(Si)이온을 기판(20)에 확산시켜 기판(20) 표면내에 저농도 및 고농도의 소오스 영역(26) (27)과 드레인 영역(28) (29)을 형성한다.2 (d), the silicon (Si) ions of the second silicon oxide film 24 and the silicon nitride film 25 are diffused into the substrate 20 by a single ion diffusion process, Source regions 26 and 27 and drain regions 28 and 29 of a low concentration and a high concentration are formed.
이때, 이와 같은 저농도 및 고농도의 소오스 영역(26) (27)과 드레인 영역(28) (29)이 형성되는 이유는 제 2실리콘산화막(24) 형성시 사용되는 SiH/N2O 가스비를 다르게 조절함으로써 농도가 다른 소오스 영역과 드레인 영역을 형성할 수 있다.The reason why the source and drain regions 26 and 27 are formed at a low concentration and a high concentration is that the SiH / N 2 O gas ratio used in the formation of the second silicon oxide film 24 is controlled differently The source and drain regions having different concentrations can be formed.
즉, 기판(20)으로 확산되는 실리콘이온의 농도는 제 2실리콘산화막(24) 형성시 사용되는 SiH4/N2O 가스의 비에 의해 결정된다.That is, the concentration of silicon ions diffused into the substrate 20 is determined by the ratio of SiH 4 / N 2 O gas used in forming the second silicon oxide film 24.
그리고, 제 2실리콘산화막(24) 및 실리콘질화막(25)을 제거하고 소오스 영역과 드레인 영역상에 소오스 전극(30) 및 드레인 전극(31)을 형성하여 LDD 구조를 갖는 MESFET을 완성한다.Then, the second silicon oxide film 24 and the silicon nitride film 25 are removed, and the source electrode 30 and the drain electrode 31 are formed on the source region and the drain region, thereby completing the MESFET having the LDD structure.
본 발명에 따른 MESFET 제조방법에 있어서는 다음과 같은 효과가 있다. 1번의 이온확산공정으로 LDD 구조를 갖는 MESFET을 제작함으로써 공정이 간단하고 이온주입기와 같은 고가의 장비를 사용하지 않으므로 공정가를 줄일 수 있다. 또한, 이온확산공정을 이용하여 게이트-드레인 항복전압을 높이고, 게이트-소오스 저항을 줄일 수 있다.The MESFET fabrication method according to the present invention has the following effects. Since the MESFET having the LDD structure is fabricated by one ion diffusion process, the process is simple and the expensive equipments such as the ion implanter are not used, so the process cost can be reduced. In addition, an ion diffusion process can be used to increase the gate-drain breakdown voltage and reduce the gate-source resistance.
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