KR19990026422A - Output data rearrangement device according to scan type of frame memory - Google Patents

Abstract

The present invention relates to an output data rearrangement apparatus according to a scan type of a frame memory.

The apparatus of the present invention is a scan type that reads two blocks in a horizontal box unit and reads one block in a vertical box unit, and a scan type that reads one block in a vertical box unit and reads two blocks in a horizontal box unit. In this case, the first latch L1 latches 8 pixel data, the second latch L2 latches 16 pixel data, the first FIFO 50 for storing pixel data over one block, and two blocks. A second FIFO 60 for storing pixel data over a predetermined number of pixels according to the pixel address PA of the reference point RP of the predicted macroblock by a predetermined number of times, thereby corresponding to the predicted macroblock. First and second data sorting units 60 and 70 for extracting effective pixel data up to half pixels, and the first data sorting unit 70 and the second data sorting unit 80 according to the scan type (scan_type). Select) to print A multiplexer 90 configured to select a scan type to read in box units over up to three blocks according to the pixel address of the reference point of the predicted macroblock, and then shift left by up to seven times to predict the macroblock. It may be rearranged to the pixel data corresponding to.

Description

Apparatus for rearranging data output from a frame memory according to scanning type of a frame memory

The present invention relates to a motion compensation device, and more particularly, to an apparatus for rearranging output data of a frame memory according to a scan type.

The motion compensation technique used in the Moving Picture Experts Group (MPEG) -2 standard is to reduce temporal redundancy by estimating and compensating for motion between two adjacent temporal pictures in macroblock units. That is, in the motion estimation and compensation process, a neighboring image is compared with the current image to detect a motion vector, which is information about an object's motion, and the current image is predicted using the motion vector.

In an MPEG-2 video encoder using such a motion compensation technique, the P picture performs forward motion compensation on the basis of the I picture or P picture of the previous picture with respect to the current picture, and the B picture performs the current picture. The best one is selected from among motion compensation blocks obtained by performing forward motion compensation, reverse motion compensation, and interpolated motion compensation based on the I picture or P picture of the previous picture and the I picture or P picture of the next picture.

The frame memory is used to store the I picture or P picture of the previous picture and the I picture or P picture of the next picture as the reference picture for motion compensation. In addition, the frame memory is used to temporarily store a decoded picture and fetch it according to the display order since the decoding order and the display order are different in the MPEG-2 video decoder.

However, the frame memory as described above has a capacity to store at least three frames of image data according to the I picture and the P picture or the distance M between the P picture and the P picture, and therefore, the price is expensive, and thus, the entire picture. In addition to raising the price of the decoder, there is a problem that the delay time from the completion of decoding to the display increases.

Accordingly, the present invention has been made to solve the above problems, and includes a region for storing reference image data, a region for storing decoded image data for display, and an encoded bitstream input to an image decoder. In a frame memory in which an area to be stored is implemented on one memory module, pixel data corresponding to a macroblock predicted by a start address and a motion vector of a current macroblock is stored in a box unit over a maximum of three blocks according to a scan type. It is an object of the present invention to provide an apparatus for rearranging pixel data corresponding to a predicted macroblock after reading.

According to an aspect of the present invention, there is provided a frame memory of a field structure that stores pixel data for reference in macroblock units in motion compensation. 8 pixel data is latched over a block from the box where) is located, and then 8 pixel data is latched over a block from the box where the jump address JA2 is positioned, and in the case of the second scan type, the frame memory Is a first latch for latching 8 pixel data from the box where the jump address JA1 is located, and in the case of the first scanning type, a block from the box where the jump address JA0 output from the first latch is located. 8 blocks per block from 8 boxes of pixel data and a frame in which jump address JA1 is located from the frame memory. Each pixel data is latched, and in the case of the second scan type, the jump address JA3 is input from the pixel memory and frame memory each of eight blocks from the box where the jump address JA1 output from the first latch is located. A second latch for latching eight pixel data over a block from a box to be positioned, and a first FIFO for storing pixel data for one block from a box in which a jump address JA0 is located in the case of the second scan type. In the case of the first scan type, a second FIFO for storing pixel data over two blocks in which a jump address JA0 and a jump address JA1 output from the second latch are located, and a first scan in the predicted macroblock. By shifting the pixel data according to the type a predetermined number of times according to the pixel address of the reference point, the effective pixel data corresponding to the predicted macroblock is determined. A first data sorting unit for extracting the data from half a pixel, and shifting the pixel data according to the second scan type a predetermined number of times according to the pixel address of the reference point in the predicted macroblock, thereby corresponding to the predicted macroblock. And a second data sorting unit for extracting effective pixel data by considering half pixels, and a multiplexer for selecting outputs of the first data sorting unit and the second data sorting unit according to a scan type (scan_type).

1 is a diagram showing the structure of a frame memory adopted in the present invention;

FIG. 2 is a diagram illustrating an example of a method for setting a RAS box for one frame in the frame memory shown in FIG. 1;

3 is a view showing an example of a macroblock structure in the RAS box shown in FIG.

4A is a diagram illustrating an example of a position of a predicted macroblock;

4B and 4C illustrate an example of a scan type of a frame memory according to the present invention;

5 is output data according to a scan type of a frame memory according to the present invention.

It is a block diagram which shows the structure of a rearrangement apparatus.

* Explanation of symbols for main parts of the drawings

50: first FIFO 60: second FIFO

70: first data sorting unit 80: second data sorting unit

90: multiplexer L1, L2: latch

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a structure of a frame memory adopted in the present invention, in which the frame memory 100 includes a restored image data write operation, a data read operation for motion compensation, and a data read operation for display to a memory controller (not shown). Is controlled by The frame memory 100 has two memory banks, bank 1 and bank 2, bank 1 has first and second frame storage areas 100-1 and 100-2, and bank 2 stores third and fourth frames. There are regions 100-3 and 100-4. Here, the first to fourth frame storage areas 100-1, 100-2, 100-3, and 100-4 have a capacity for storing pixel data of one frame, respectively, and the first to fourth frame storage areas 100-1, 100-. 2,100-3 and 100-4 each have 1,024 row addresses, and have a column address of 256 words (where 1 word is 8 bits). One address stores eight Y pixels, two Cr pixels, two Cb pixels, and a total of 12 pixel data. Here, 1,024 row addresses mean the number of RAS boxes. The 256-word column address is derived by eight macroblocks per one RAS box * 32 boxes per macroblock (= 256 boxes).

The actual physical row address of the frame memory 100 is 000 _H to 3FF _H , 400 _H to 7FF _H for the first to fourth frame storage areas 100-1 to 100-4, respectively. , 800 _H to BFF _H and C00 _H to FFF _H. However, the first to fourth frame storage regions 100-1 to 100-4 exist independently, and the second and fourth frames corresponding to the macroblocks located at predetermined row addresses of the first frame storage region 100-1 are respectively provided. The macroblocks of the third frame storage areas 100-2 and 100-3 have the same row address. As such, the row address in the first to third frame storage areas 100-1 to 100-3 is referred to as a virtual row address. Then, based on the scheduling order of the frame memory 100 as shown in FIG. 2 during motion compensation, an address used to convert a virtual row address in a corresponding storage area in which a reference image is located into a physical row address is framed. It is called the frame offset address and is called RA [11:10]. That is, if RA [11:10] is '00', the first frame storage area 100-1, if '01', the second frame storage area 100-2, and if the '10', the third frame storage area 100 -3) and '11' indicate the fourth frame storage areas 100-4, respectively.

Here, the first and second frame storage areas 100-1 and 100-2 are used to store reconstructed I-picture or motion-compensated P-picture image data for use as a reference image for motion compensation and simultaneously for display. The three-frame storage area 100-3 is used to store the motion compensated B-picture image data, and the fourth frame storage area 100-4 stores the encoded bitstream input to the image decoder in units of predetermined bits. Used to save.

FIG. 2 illustrates an example of a RAS box setting method for one frame in the frame memory 100 shown in FIG. 1. For example, when one frame includes 1,920 pixels * 1,088 pixels, 15 RAS boxes * 68 It is divided into RAS boxes, a total of 1,020 Row Address Strobe (RAS) boxes. That is, the number of the RAS box is the row address (RA) of the frame memory 100. Here, one RAS box is composed of 8 macroblocks * 1 macroblocks and a total of 8 macroblocks MB0 to MB7. Each macroblock is divided into four blocks b0 to b3 when the luminance Y block is taken as an example.

FIG. 3 shows an example of a macroblock structure in the RAS box shown in FIG. 2, with four luminance (Y) blocks b0 to b3, one color difference (Cr) block, and one color difference (Cb) block. Four luminance (Y) blocks are composed of eight boxes (b0-0 to b0-7, b1-0 to b1-7, b2-0 to b2-7, and b3-0 to b3-7), respectively. Each of the two color difference (Cr, Cb) blocks has eight sub boxes (sb0-0 to sb0-7, sb1-0 to sb1-7, sb2-0 to sb2-7, and sb3-0 to sb3-7). It consists of. 8 pixel data in 8 * 1 format is included in each box constituting the Y block, 2 pixel data in 2 * 1 format is formed in each sub box constituting the Cr block, and 2 * is in each sub box constituting the Cb block. There are two pixel data in one format.

4A illustrates an example of a position of a predicted macroblock, wherein the macroblock MBp predicted by the start address and the motion vector of the current macroblock to be motion compensated is divided into four macroblocks, that is, the macroblock MB7. ), The macroblock MB8, the macroblock MB127 and the macroblock MB128 are shown. In other words, the predicted macroblock (MBp) is located across four RAS boxes, RAS box 0, RAS box 1, RAS box 15 and RAS box 16.

FIG. 5 is a block diagram illustrating an output data rearrangement apparatus according to a method of reading a frame memory according to the present invention, wherein a first latch L1, a second latch L2, a first FIFO 50, and a second FIFO are shown. 60, a first data sorting unit 70, a second data sorting unit 80, and a multiplexer 90.

Then, the operation and effects of the present invention will be described in detail with reference to FIGS. 1 to 5. Here, for convenience of description, when a picture to be referred to as a frame picture and a motion type is frame estimation and compensation, a luminance signal is taken as an example.

In order to consider the worst case that may occur, the starting address of the current macroblock to be motion compensated, that is, the slice position and the macroblock position (mb-position), and the vertical and horizontal motion vectors The case in which the macroblock MBp predicted from S is located as shown in FIG. 4A will be described. In FIG. 4A, pixel data corresponding to the predicted macroblock MBp is read in box units, that is, in units of 8 pixels.

First, when the scan type is in the order as shown in FIG. 4B and the macroblock MBp predicted in the upper field is read in units of two blocks, the macroblock MB7 in which the reference point RP is located is located. The two boxes of the box b3-2 of the block b3 and the box b2-2 of the block b2 of the next macroblock MB8 are read, and the box of the block b3 of the macroblock MB127 is read. (b3-0) and two boxes are read sequentially up to the box (b2-0) of the block (b2) of the next macroblock (MB128), so that 16 boxes across two blocks are placed on a common bus (not shown). Raised Subsequently, eight boxes are read from the box b3-2 of the block b3 of the macroblock MB8 and placed on a common bus (not shown).

When pixel data is read in a box unit as described above, eight boxes must be read over a total of three blocks except that the reference point R.P is placed at the start position of each macroblock. The present invention is to extract the pixel data corresponding to the predicted macroblock MBp from the pixel data read out in a box unit over a maximum of three blocks in the corresponding storage area of the frame memory (100 in FIG. 1). .

According to the scanning type shown in FIG. 4B, if data in units of pixels is loaded on a common bus (not shown), the first latch L1 may move from the box b3-2 to the block b3 of the macroblock MB7. Latch the two boxes. The second latch L2 is the box b2-2 of the block b2 of the macroblock MB8 supplied from the frame memory 300 and the eight pixel data corresponding to one box supplied from the first latch L1. 8 pixel data) are latched. The second FIFO 60 is a common bus (not shown) sequentially from the block in which the reference point is located from the corresponding storage area of the frame memory (100 in FIG. 1) that stores pixel data over up to three blocks. For storing the pixel data in the unit of a box mounted on the box, and including the box b3-2 of the block b3 of the macroblock MB7 and the block of the next macroblock MB8 from the second latch L2. 16 pixel data corresponding to box b2-2 of b2) are input and sequentially stored over eight boxes. At this time, the second FIFO 60 is capable of storing pixel data over nine boxes in consideration of the upper half or the lower half half. As such, when the first latch L1 and the second latch L2 latch all 16 pixel data across eight boxes and store data from two blocks from the block where the reference point is located in the second FIFO 60, The first latch L1 latches eight pixel data from the box b3-2 of the block b3 of the macroblock MB8 to eight boxes.

The first data sorting unit 70 outputs a box b3-2 of the block b3 of the macroblock MB7 output from the second FIFO 60 and a box of the block b2 of the next macroblock MB8. 16 pixel data corresponding to (b2-2) and 8 pixel data corresponding to the box b3-2 of the block b3 of the macroblock MB8 output from the first latch L1 are received. , To extract pixel data (ie, 16 pixel data) for two blocks of the predicted macroblock MBp. To this end, the pixel address P.A for the reference point R.P of the predicted macroblock MBp is used.

The first data sorting unit 70 performs a maximum of seven shifting operations to the left according to the pixel address PA. For example, when the pixel address of the reference point RP is 011 ₂ in FIG. 4A, three shifting operations are performed. Is done. That is, the first data sorting unit 70 shifts 24 pixel data left by one pixel a predetermined number of times according to the pixel address PA, thereby extracting 17 effective pixel data in consideration of half a pixel.

Next, the scanning type will be described in the order as shown in FIG. 4C, and the case in which the predicted macroblock MBp in the upper field is read in units of two blocks will be described. First, eight boxes are read from the box b3-2 of the block b3 of the macroblock MB7 in which the reference point R.P is located and loaded on a common bus (not shown). Subsequently, two boxes of the box b2-2 of the block b2 of the next macroblock MB8 and the box b3-2 of the block b3 of the macroblock MB8 are read, and the macroblock MB128 Two boxes are read sequentially from the box b2-0 of the block b2 of the block to the box b3-0 of the block b3 of the macroblock MB128. It is put on (not shown).

According to the scanning type shown in FIG. 4C, if data in pixel units is loaded on a common bus (not shown), the first FIFO 50 stores a frame memory (100 in FIG. 1) storing up to three blocks of pixel data. A box of block b3 of the macroblock MB7 for storing pixel data in a box unit sequentially loaded on a common bus (not shown) over one block in which a reference point is located from the corresponding storage area of the block. From (b3-2), eight pixel data are sequentially stored over eight boxes. When data for one block in which the reference point is located is stored in the first FIFO 50 as described above, the first latch L1 is a box of the block b2 of the macroblock MB8 supplied from a common bus (not shown). 8 pixel data are latched from (b2-2), and the second latch L2 is supplied from the frame memory (100 in FIG. 1) and the 8 pixel data corresponding to one box supplied from the first latch L1. The eight pixel data of the box b3-2 of the block b3 of the macroblock MB8 is latched. The first FIFO 50 is capable of storing pixel data over nine boxes in consideration of upper or lower half pixels.

The second data sorting unit 80 includes eight pixel data for the box b3-2 of the block b3 of the macroblock MB7 output from the first FIFO 50 and the second latch L2. 16 pixel data corresponding to the box b3-2 of the block b3 of the next macroblock MB8 and the box b2-2 of the block b2 of the macroblock MB8 are input and predicted. It is for extracting pixel data (ie, 16 pixel data) for two blocks of the macroblock MBp. To this end, the pixel address P.A for the reference point R.P of the predicted macroblock MBp is used.

The second data sorting unit 80 performs a maximum of seven shifting operations to the left according to the pixel address PA. For example, when the pixel address of the reference point RP is 011 ₂ in FIG. 4A, three shifting operations are performed. This is done. That is, the second data sorting unit 80 shifts the 24 pixel data left by one pixel a predetermined number of times according to the pixel address PA, thereby extracting 17 effective pixel data in consideration of half a pixel.

The multiplexer 90 of FIG. 5 selectively outputs the outputs of the first data sorting unit 70 and the second data sorting unit 80 using the scan type scan_type as a control signal. That is, when the scan type is as shown in FIG. 4B, the output of the first data sorting unit 80 is selected. When the scan type is as shown in FIG. 4C, the output of the second data sorting unit 90 is selected and output.

On the other hand, the above detailed description is intended to describe particular embodiments presented herein and is not intended to limit the present invention. Those skilled in the art may make various changes and modifications according to the structure of the RAS box, the structure of the macroblock block, the picture type, and the motion compensation form within the spirit of the present invention with reference to the above description and drawings.

As described above, the apparatus of the present invention selects a scan type when the macroblock predicted by the start address and the motion vector of the current macroblock to be motion compensated from the corresponding storage area of the frame memory is selected. According to the pixel address of the block, the read-by-box unit over a maximum of three blocks, and then left shifted by up to seven times, can be rearranged into pixel data corresponding to the predicted macroblock.

Claims (3)

A frame memory for storing pixel data for reference in macroblock units in motion compensation, In the case of the first scanning type, eight pixel data are latched from the box where the jump address JA0 is located from one frame to one block, and eight pixels from the box where the jump address JA2 is located. A first latch L1 for latching data and latching 8 pixel data from a box in which a jump address JA1 is located from the frame memory in the case of the second scan type; In the case of the first scan type, one box is located from the box in which the jump address JA0 output from the first latch L1 is located, from the box in which the jump address JA1 is located from the pixel memory and frame memory of eight blocks. 8 pixel data and frame memories are latched from the box in which 8 pixel data are latched over the block and the jump address JA1 output from the first latch L1 is located in the case of the second scan type. A second latch L2 for latching eight pixel data each block from a box in which a jump address JA3 is located; A first FIFO 50 for storing pixel data over a block from a box in which a jump address JA0 is located in the case of the second scan type; A second FIFO 60 for storing pixel data over two blocks in which a jump address JA0 and a jump address JA1 are output from the second latch L2 in the case of the first scan type; By shifting pixel data according to the first scan type a predetermined number of times in the predicted macroblock according to the pixel address of the reference point, the first data sorting extracting effective pixel data corresponding to the predicted macroblock by considering half pixels. Part 70; Second data sorting for extracting effective pixel data corresponding to the predicted macroblock by taking half pixels by shifting pixel data according to the second scan type a predetermined number of times in the predicted macroblock according to the pixel address of the reference point. Part 80; And Output data according to the scan type of the frame memory, characterized in that it comprises a multiplexer 90 for selecting the output of the first data sorting unit 70 and the second data sorting unit 80 according to the scan type (scan_type) Rearrangement device. The method of claim 1, wherein one frame picture stored in the frame memory includes a plurality of RAS boxes, the RAS box includes eight macroblocks, and the macroblocks include four blocks for luminance blocks. And the block has a 1 box * 8 box format, and the box has an 8 pixel * 1 pixel format. 2. The apparatus of claim 1, wherein the first to second data sorting units (80,90) perform a maximum of seven shifts according to the pixel address.