KR19990032812A - Address generator in frame memory - Google Patents

Abstract

The present invention relates to an address generator in a frame memory for a motion compensation device.

The apparatus of the present invention, in the frame memory mapped to the macroblock of the field structure, when the predicted macroblock (MBp) is read in units of two blocks, the horizontal motion vector according to the block to be read of the predicted macroblock Horizontal motion vector counter 61 which selects and outputs one of the added horizontal motion vector and the two added horizontal motion vectors, and the vertical motion vector and 1 to 7 for shifting in units of boxes in the block to be read of the predicted macroblock. The vertical motion vector counter 62 which selects and outputs one of the added vertical motion vectors, and the motion vector mv_h and mv_v output from the horizontal and vertical motion vectors 61 and 62 and the slice position value of the current macroblock ( slice_pos) and macroblock position value (mb_pos) are input to generate an address for generating a plurality of addresses for reading the predicted macroblock It consists of a core 63, and obtains 24 motion vectors in box units for the predicted macroblock without the hassle of finding the macroblock position in the RAS box and the block position in the macroblock based on the reference point. The address for the macroblock predicted by the start address and the motion vector of the block can be easily generated.

Description

Apparatus for generating address in a frame memory

The present invention relates to a frame memory for a motion compensation device. In particular, in order to read a macroblock predicted by motion compensation from a frame memory, 24 motion vectors are calculated in box units for the predicted macroblock, and the motion vector is obtained. And an address generator for generating an address for a series of motion vectors using the slice position of the current macroblock and the macroblock position.

The motion compensation technique used in the Moving Picture Experts Group (MPEG) -2 standard is to reduce temporal redundancy by estimating and compensating for motion between two adjacent temporal pictures in macroblock units. That is, in the motion estimation and compensation process, a neighboring image is compared with the current image to detect a motion vector, which is information about an object's motion, and the current image is predicted using the motion vector.

In an MPEG-2 video encoder using such a motion compensation technique, the P picture performs forward motion compensation on the basis of the I picture or P picture of the previous picture with respect to the current picture, and the B picture performs the current picture. The best one is selected from among motion compensation blocks obtained by performing forward motion compensation, reverse motion compensation, and interpolated motion compensation based on the I picture or P picture of the previous picture and the I picture or P picture of the next picture.

The frame memory is used to store the I picture or P picture of the previous picture and the I picture or P picture of the next picture as the reference picture for motion compensation. In addition, the frame memory is used to temporarily store the decoded picture and read out the display order in a MPEG-2 video decoder because the decoding order and the display order are different from each other.

However, the frame memory as described above has a capacity to store at least three frames of image data according to the I picture and the P picture or the distance M between the P picture and the P picture, and therefore, the price is expensive, and thus, the entire picture. In addition to raising the price of the decoder, there is a problem that the delay time from the completion of decoding to the display increases.

Accordingly, the present invention has been made to solve the above problems, and includes a region for storing reference image data, a region for storing decoded image data for display, and an encoded bitstream input to an image decoder. In a frame memory in which an area to be stored is implemented on one memory module, 24 motion vectors are obtained by box unit to read a macroblock predicted by motion compensation from the frame memory, and then an address for a series of motion vectors is obtained. It is an object of the present invention to provide an address generator for generating a.

The address generator according to the present invention for providing the above object, in the frame memory mapped to the macroblock of the field structure, the slice position value, the macroblock position value and the motion vector of the current macroblock to be motion compensated When generating the row address and column address of the predicted macroblock by using, the adder A11 for adding 1 to the horizontal motion vector mv_h [11: 4], the adder A12 for adding 2, and the horizontal motion It consists of a multiplexer M11 which sequentially selects and outputs a vector mv_h [11: 4], an output of the adder A11, and an output of the adder A12, and is horizontal in block units with respect to the macroblock. Horizontal motion vector counter for counting motion vectors, adder A21 for adding 4 to vertical motion vector mv_v [7: 1], adder A22 for adding 1, adder for adding 2 (A23) ), A multiplexer M21 that sequentially selects and outputs one of an adder A24, a vertical motion vector mv_v [7: 1], and an output of the adder A21, and the multiplexer M21. A multiplexer (M22) for sequentially selecting and outputting one of an output and one of the outputs of the adders (A22, A23, and A24), a vertical motion vector counter for counting vertical motion vectors in units of boxes for the macroblock, and A plurality of motion vectors (mv_h, mv_v) output from the horizontal and vertical motion vector counters, a slice position value (slice_pos), and a macro block position value (mb_pos) of the current macroblock, respectively; And an address generation core for generating an address.

1 is a diagram showing the structure of a frame memory adopted in the present invention;

2 is a diagram illustrating a scheduling order of the frame memory shown in FIG. 1;

3 is a diagram illustrating an example of a method for setting a RAS box for one frame in the frame memory shown in FIG. 1;

4 is a view showing an example of a macroblock structure in the RAS box shown in FIG.

5 is a diagram illustrating an example of a position of a predicted macroblock;

6 is a block diagram showing an address generator in a frame memory according to the present invention.

＊ Explanation of symbols for main parts of drawing

100: frame memory 100-1 to 100-4: first to fourth frame storage areas

61: Horizontal Motion Vector Counter 62: Vertical Motion Vector Counter

63: address generation core A11, A12, A21, A22, A23, A24: adder

M11, M21, M22: Multiplexer C11, C21, C22: Counter

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a structure of a frame memory adopted in the present invention, in which the frame memory 100 includes a restored image data write operation, a data read operation for motion compensation, and a data read operation for display to a memory controller (not shown). Is controlled by The frame memory 100 has two memory banks, bank 1 and bank 2, bank 1 has first and second frame storage areas 100-1 and 100-2, and bank 2 stores third and fourth frames. There are regions 100-3 and 100-4. Here, the first to fourth frame storage areas 100-1, 100-2, 100-3, and 100-4 have a capacity for storing pixel data of one frame, respectively, and the first to fourth frame storage areas 100-1, 100-. 2,100-3 and 100-4 each have 1,024 row addresses, and have a column address of 256 words (where 1 word is 8 bits). One address stores eight Y pixels, two Cr pixels, two Cb pixels, and a total of 12 pixel data. Here, 1,024 row addresses mean the number of RAS boxes. The 256-word column address is derived by eight macroblocks per one RAS box * 32 boxes per macroblock (= 256 boxes).

The actual physical row address of the frame memory 100 is 000 _H to 3FF _H , 400 _H to 7FF _H for the first to fourth frame storage areas 100-1 to 100-4, respectively. , 800 _H to BFF _H and C00 _H to FFF _H. However, the first to fourth frame storage regions 100-1 to 100-4 exist independently, and the second and fourth frames corresponding to the macroblocks located at predetermined row addresses of the first frame storage region 100-1 are respectively provided. The macroblocks of the third frame storage areas 100-2 and 100-3 have the same row address. As such, the row address in the first to third frame storage areas 100-1 to 100-3 is referred to as a virtual row address. Then, based on the scheduling order of the frame memory 100 as shown in FIG. 2 during motion compensation, an address used to convert a virtual row address in a corresponding storage area in which a reference image is located into a physical row address is framed. It is called the frame offset address and is called RA [11:10]. That is, if RA [11:10] is '00', the first frame storage area 100-1, if '01', the second frame storage area 100-2, and if the '10', the third frame storage area 100 -3) and '11' indicate the fourth frame storage areas 100-4, respectively.

Here, the first and second frame storage areas 100-1 and 100-2 are used to store reconstructed I-picture or motion-compensated P-picture image data for use as a reference image for motion compensation and simultaneously for display. The three-frame storage area 100-3 is used to store the motion compensated B-picture image data, and the fourth frame storage area 100-4 stores the encoded bitstream input to the image decoder in units of predetermined bits. Used to save.

FIG. 2 shows a scheduling order of the frame memory 100 shown in FIG. 1, and the decoding order is I, P, B, B, P, B, B, P, B, B, P, B, B, I. , P, B, B, ... and the display order is I, B, B, P, B, B, P, B, B, P, B, B, P, I, B, B, ... For example, the display latency is 2 pictures. Here, the underlined portion indicates the picture currently being decoded, the arrow indicates the picture to be referred for motion compensation, and the storage area to which 'D' is added indicates that image data is being read out for display.

FIG. 3 shows an example of a method for setting a RAS box for one frame in the frame memory 100 shown in FIG. 1. For example, when one frame includes 1,920 pixels * 1,088 pixels, 15 RAS boxes * 68 It is divided into RAS boxes, a total of 1,020 Row Address Strobe (RAS) boxes. That is, the number of the RAS box is the row address (RA) of the frame memory 100. Here, one RAS box is composed of 8 macroblocks * 1 macroblocks and a total of 8 macroblocks MB0 to MB7. Each macroblock is divided into four blocks b0 to b3 when the luminance Y block is taken as an example.

FIG. 4 shows an example of a macroblock structure in the RAS box shown in FIG. 3, with four luminance (Y) blocks b0 to b3, one color difference (Cr) block, and one color difference (Cb) block. Four luminance (Y) blocks are composed of eight boxes (b0-0 to b0-7, b1-0 to b1-7, b2-0 to b2-7, and b3-0 to b3-7), respectively. Each of the two color difference (Cr, Cb) blocks has eight sub boxes (sb0-0 to sb0-7, sb1-0 to sb1-7, sb2-0 to sb2-7, and sb3-0 to sb3-7). It consists of. Then, 8 pixel data in 8 * 1 format for each box constituting the Y block, 2 pixel data in 2 * 1 format for each box constituting the Cr block, and 2 * 1 format for each box constituting the Cb block. There are two pixel data of.

On the other hand, in order to consider the worst case that may occur, the starting address of the current macroblock to be motion compensated, that is, the slice position and the macroblock position (mb-position), and vertical and horizontal A case in which the macroblock MBp predicted from the motion vector is located as shown in FIG. 5 will be described.

In FIG. 5, pixel data corresponding to the predicted macroblock MBp is read in box units, that is, in units of 8 pixels. Therefore, when the predicted macroblock MBp is read in units of two blocks, eight boxes are first selected from the box b3-1 of the block b3 of the macroblock MB7 where the reference point RP is located. 8 boxes are read from box b2-1 of block b2 of the next macroblock MB8, and finally from box b3-1 of block b3 of the macroblock MB8. From the eight boxes are read and sequentially placed on a common bus (not shown). When pixel data is read in a box as described above, eight boxes must be read over a total of three blocks except that the reference point RP is placed at the start of each macroblock. A total of 24 pixel data are read. On the other hand, 24 addresses are required to read the MBp at the position shown in FIG. 5 according to the motion type, the picture structure, and the like. The present invention is to calculate an address required for reading pixel data in units of boxes as described above.

Fig. 6 is a block diagram showing an address generator according to the present invention in a frame memory, which is comprised of a horizontal motion vector counter 61, a vertical motion vector counter 62, and an address generation core 63. Figs. The horizontal motion vector counter 61 is composed of adders A11 and A12, a multiplexer M11, and a counter C11, and the vertical motion vector counter 62 is connected to adders A21, A22, A23 and A24. And multiplexers M21 and M22, and counters C21 and C22.

First, referring to the structure of the motion vector, the horizontal motion vector mv_h [12: 0] and the vertical motion vector mv_v [8: 0] each use the most significant 1 bit as the sign bit and the least significant 1 bit as the half pixel flag. The remaining bits are used as pixel data. On the other hand, in the predicted macroblock MBp of Fig. 5, since the box has a structure of 8 pixels * 1 pixel, the motion vector between jump addresses has a shift scale of 8 pixels horizontally and 1 pixel vertically.

The motion vectors mv_h and mv_v have the half-pixel flag and the horizontal motion vector mv_h [11: 4] and the half-pixel flag erased three bits again in order to adjust the horizontal shift scale. The motion vectors mv_v [7: 1] are divided into the horizontal motion vector counter 61 and the vertical motion vector counter 62, respectively.

Referring to the horizontal motion vector counter 61 of FIG. 6, the adder A11 adds 1 to the horizontal motion vector mv_h [11: 4] and the adder A12 adds 2. The multiplexer M11 selects and outputs the horizontal motion vector mv_h [11: 4] as it is by the counter C11 according to the block to be read, or the horizontal motion vector in which 1 or 2 are added through the adders A11 and A12, respectively. Select (mv_h [11: 4]) to print. Subsequently, looking at the vertical motion vector counter 62, the adder A21 adds 4 to the vertical motion vector mv_v [7: 1], the adder A22 adds 1, the adder A23 adds 2, and the adder ( A24) adds three. The multiplexer M21 selects and outputs one of the vertical motion vector mv_v [7: 4] and the output of the adder A21 according to the box position to be read, and the multiplexer M22 reads. According to the box position, the counter C22 selects and outputs one of the output of the multiplexer M21 and the outputs of the adders A22, A23, and A24. Meanwhile, in the detailed description of the present invention, the multiplexers M11, M21, and M22 select the input signals by the counters C11, C21, and C22, but the input signals may be sequentially selected by a predetermined control signal.

First, a case where an address required for reading pixel data of eight boxes is obtained from the box b3-1 of the block b3 of the macroblock MB7 where the reference point is located.

In this case, the multiplexer M11 of the horizontal motion vector counter 61 selects and outputs the horizontal motion vector mv_h [11: 4] pointing to the reference point as it is, according to the count value of the counter C11, and outputs the vertical motion vector. The multiplexers M21 and M22 of the counter 62 each add so that a series of numbers from 0 to 7 are added in order to the vertical motion vector mv_v [7: 1] according to the counter values of the counters C21 and C22, respectively. Select and output the outputs of the fields A21, A22, A23, and A24. At this time, the cycle of the counter C11 is twice the cycle of the counter C21, and the cycle of the counter C21 is four times the cycle of the counter C22. That is, the period of the counter C11 is equal to the period of reading one block, the counter C21 is equal to the period of reading four boxes of one block, and the counter C22 is equal to the period of reading one box of one block. Therefore, while the multiplexer M21 outputs the vertical motion vector as it is by the counter C21, the multiplexer M22 sequentially turns the output of the multiplexer M21 and the outputs of the adders A22, A23, and A24 by the counter C22. The multiplexer M22 is output by the counter C22 while the multiplexer M21 selects and outputs the output of the adder A21 by the counter C21 by the counter C21. By sequentially selecting the output of the multiplexer M21 and the outputs of the adders A22, A23, and A24, vertical motion vectors added from 4 to 7 are output.

Next, the multiplexer of the horizontal motion vector counter 61 is obtained to obtain an address necessary to read eight boxes from the box b2-1 of the block b2 of the macroblock MB8 in which the jump address JA1 is located. M11 selects and outputs the horizontal motion vector mv_h [11: 4] added by one by the adder A11 according to the count value of the counter C11. The multiplexers M21 and M22 of the vertical motion vector counter 62 each have a sequence of numbers from 0 to 7 in the vertical motion vector mv_v [7: 1] according to the counter values of the counters C21 and C22. The outputs of the adders A21, A22, A23, and A24 are selected to be added as they are.

Then, in order to obtain an address necessary for reading eight boxes from the box b3-1 of the block b3 of the macroblock MB8 where the jump address JA2 is located, the horizontal motion vector counter 61 The multiplexer M11 selects and outputs the horizontal motion vector mv_h [11: 4] added by the adder A12 according to the count value of the counter C11, and multiplexer M21 of the vertical motion vector counter 62. M22 adds the numbers A21, A22, A23, so that a series of numbers from 0 to 7 are added to the vertical motion vector mv_v [7: 1] in order according to the counter values of the counters C21, C22, respectively. Select the output of A24) and output it.

The address generation core 63 of FIG. 6 includes 24 series of motion vectors mv_h, obtained by the horizontal and vertical motion vector counters 61 and 62 as described above, in order to generate an address necessary for reading the predicted macroblock. mv_v), the slice position (slice_pos [6: 0]) and the macroblock position (mb_pos [6: 0]) as inputs, and the linear address (LA [13 :) of the macroblock predicted by the following equation: 0]).

LA = (slice_pos + mv_v) * slice_width + (mb_pos + mv_h)

Here, slice_width is 120, indicating that there are 120 macroblocks in the horizontal direction in one frame (1920 pixels * 1088 pixels).

On the other hand, the above detailed description is intended to describe particular embodiments presented herein and is not intended to limit the present invention. Those skilled in the art may make various changes and modifications according to the structure of the RAS box and the structure of the macroblock block within the technical spirit of the present invention with reference to the above detailed description and drawings.

As described above, in the apparatus of the present invention, in order to read a macroblock predicted by motion compensation from a frame memory in a frame memory in which the first to fourth frame storage areas are implemented on one memory module, 24 motion vectors are calculated per box for the predicted macroblock without the hassle of finding the macroblock position in the RAS box and the block position in the macroblock based on the point. It is possible to easily generate an address for the predicted macroblock.

Claims (3)

In a frame memory mapped to a macroblock of a field structure, when generating a row address and a column address of a macroblock predicted by using a slice position value, a macroblock position value, and a motion vector of a current macroblock to be motion compensated, An adder A11 that adds 1 to the horizontal motion vector mv_h [11: 4], an adder A12 that adds 2, and an output of the horizontal motion vector mv_h [11: 4] and the adder A11 And a multiplexer (M11) for sequentially selecting and outputting one of the outputs of the adder (A12), the horizontal motion vector counter (61) for counting horizontal motion vectors in units of blocks for the macroblock; An adder A21 that adds 4 to the vertical motion vector mv_v [7: 1], an adder A22 that adds 1, an adder A23 that adds 2, an adder A24 that adds 3, and a vertical motion A multiplexer M21 for sequentially selecting and outputting one of a vector mv_v [7: 1] and the output of the adder A21, an output of the multiplexer M21 and an output of the adders A22, A23, and A24. A multiplexer (M22) for sequentially selecting and outputting one of them, the vertical motion vector counter 62 for counting vertical motion vectors in units of boxes for the macroblocks; And The macroblock predicted by receiving the motion vectors mv_h and mv_v output from the horizontal and vertical motion vector counters 61 and 62, the slice position value slice_pos and the macro block position value mb_pos of the current macroblock, respectively. And an address generating core (63) for generating a plurality of addresses for reading the data. The method of claim 1, wherein the period in which the multiplexer M11 selects one of three input signals is twice the period in which the multiplexer M21 selects one of two input signals, and the multiplexer M21 inputs two input signals. The period for selecting one of the signals is four times the period for the multiplexer (M22) to select one of the four input signals. 2. The address generator of claim 1, wherein the address generator generates a series of addresses for 24 boxes when the predicted macroblock is read in units of two blocks.