KR19990026428A - Address generator in frame memory - Google Patents

Abstract

The present invention relates to an address generator in a frame memory used in a motion compensation device.

The apparatus of the present invention is a frame memory mapped to a plurality of RAS boxes having a predetermined macroblock structure, and is linearly separated with respect to each of a start address (slice_pos, mb_pos) and a motion vector (mv_h, mv_v) of a current macroblock. A first address generation core 51 and a motion vector mv_h and mv_v which generate a linear address for the start address slice_pos and mb_pos so as to obtain an address and add the values to obtain a final linear address. And a second address generating core 52 for generating a linear address for the P, and an adder 53 for adding the outputs of the first to second address generating cores, by the start address and the motion vector of the current macroblock. An address related to the reference point RP of the predicted macroblock may be generated.

Description

Apparatus of generating address in a frame memory

The present invention relates to a frame memory for a motion compensation device, and more particularly to an address generator for generating an address related to a reference point for reading a predicted macroblock into the frame memory.

The motion compensation technique used in the Moving Picture Experts Group (MPEG) -2 standard is to reduce temporal redundancy by estimating and compensating for motion between two adjacent temporal pictures in macroblock units. That is, in the motion estimation and compensation process, a neighboring image is compared with the current image to detect a motion vector, which is information about an object's motion, and the current image is predicted using the motion vector.

In an MPEG-2 video encoder using such a motion compensation technique, the P picture performs forward motion compensation on the basis of the I picture or P picture of the previous picture with respect to the current picture, and the B picture performs the current picture. The best one is selected from among motion compensation blocks obtained by performing forward motion compensation, reverse motion compensation, and interpolated motion compensation based on the I picture or P picture of the previous picture and the I picture or P picture of the next picture.

Methods for motion estimation and compensation include frame motion estimation and compensation mode, field motion estimation and compensation mode, dual prime motion estimation and compensation mode, and basically all motion estimation and compensation are half pixel. It is specified to have a half-pel unit.

Among these, frame motion estimation and compensation mode has been used since MPEG-1, and motion estimation and compensation are performed in a frame structure without distinguishing a top field or even field and a bottom field or odd field. do. To this end, a full search is performed on the macroblock MB to be encoded of the current frame to the half-pixel precision in the search region of the reference frame, thereby obtaining the smallest mean absolute error (MAE). The position to generate is determined as a motion vector for the macroblock. In fact, since data is given in units of pixels, a pixel-by-pixel motion vector is obtained through the first-order full search in pixel units, and then a half-pixel motion vector is obtained through interpolation and a second full search in half-pixel units. In the case of frame motion estimation, one motion vector is transmitted per one macroblock for a P picture, and one or two motion vectors are transmitted per one macroblock for a B picture. The number of bits required for transmission is small.

Next, the field motion estimation and compensation mode performs motion estimation and compensation for each field in the picture of the frame structure. For this purpose, the upper and lower, upper and upper, lower and upper, lower and lower positions in the unit of 16 * 8 (pixels) sub macroblocks between upper and lower fields of the current frame and upper and lower fields of the reference frame, respectively. After four motion vectors are obtained, one motion vector is generated to generate a minimum motion compensation error for each of the upper and lower fields of the current frame. Therefore, two motion vectors per macroblock for a P picture and two or four motion vectors per macroblock for a B picture are transmitted. The MPEG-2 image encoder applies all the frame / field prediction modes to all macroblocks, and then uses the prediction mode having the smaller prediction error. Meanwhile, since the prediction mode used by the encoder is transmitted in the MPEG-2 image decoder, motion compensation is performed to restore the image.

On the other hand, there is a 16 * 8 (pixels) motion estimation and compensation mode as a deformation mode of the field motion estimation and compensation mode, in which two motion vectors are used for each macroblock, and the first motion vector is the top 16. For the * 8 region, the second motion vector is used for the lower 16 * 8 region. In the case of the bi-predicted macroblock, four motion vectors are used, two for forward prediction and two for backward prediction.

Next, the dual prime motion estimation and compensation mode transmits only one motion vector and differential motion vector (dmv) per macroblock, and is known to be effective for sequences with relatively slow motion. This mode is specified to be used only when the B picture is not used. That is, when the B picture is allowed, a better picture quality can be obtained using the B picture. However, when the B picture is not allowed, the dual prime prediction mode can be used to improve the picture quality with as little bit generation as possible. . In the dual prime prediction mode, first, the motion vectors of the upper, upper, and lower part of the four motion vectors obtained from the field prediction mode from upper to lower, upper to upper, lower to upper, lower to lower are used as the basic motion vectors. The upper and lower motion vectors and upper and lower motion vectors are scaled (* 2, * 2/3) and truncated, respectively, to form a basic motion vector. Next, each of the four basic motion vectors thus created is fine-tuned by -1, 0, and 1 in the horizontal and vertical directions to minimize the motion compensation error for the two 16 * 8 (pixels) sub macroblocks. A motion vector and a differential motion vector are transmitted. Since the dual prime prediction mode has a large amount of computation in the image encoder, it is necessary to calculate nine prediction candidate values per one basic motion vector. Therefore, the basic motion vector and the differential motion vector of one of 36 candidates must be calculated. Meanwhile, the image decoder can be implemented relatively simply because only two field motion vectors need to be calculated from the transmitted basic motion vector and the differential motion vector.

The frame memory is used to store the I picture or P picture of the previous picture and the I picture or P picture of the next picture as the reference picture for motion compensation. In addition, the frame memory is used to temporarily store the decoded picture and read out the display order in a MPEG-2 video decoder because the decoding order and the display order are different from each other.

However, the frame memory as described above has a capacity to store at least three frames of image data according to the I picture and the P picture or the distance M between the P picture and the P picture, and therefore, the price is expensive, and thus, the entire picture. In addition to raising the price of the decoder, there is a problem that the delay time from the completion of decoding to the display increases.

Accordingly, the present invention has been made to solve the above problems, and includes a region for storing reference image data, a region for storing decoded image data for display, and an encoded bitstream input to an image decoder. It is an object of the present invention to provide an apparatus for generating an address related to a reference point of a current macroblock MB to be motion compensated in a frame memory in which a storage area is implemented on one memory module.

An apparatus of the present invention for providing the above object, in the frame memory mapped to a plurality of RAS boxes having a predetermined macroblock structure, the start address (slice_pos, mb_pos) of the current macroblock as input, A first address generation core for generating a linear address for a start address, and a second address for generating a linear address for the horizontal and vertical motion vectors as input as the horizontal and vertical motion vectors mv_h and mv_v of the current macroblock. And an adder that adds a generation core and outputs of the first to second address generation cores to output a linear address with respect to a reference point of the predicted macroblock.

1 is a diagram showing the structure of a frame memory adopted in the present invention;

2 is a diagram illustrating a scheduling order of the frame memory shown in FIG. 1;

3 is a diagram illustrating a first example of a method for setting a RAS box for one frame in the frame memory shown in FIG. 1;

4 is a view showing an example of a macroblock structure in the RAS box shown in FIG.

5 is a block diagram showing an address generator according to the present invention.

* Explanation of symbols for main parts of the drawings

51,52: address generation core 53: adder

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a structure of a frame memory adopted in the present invention, in which the frame memory 100 includes a restored image data write operation, a data read operation for motion compensation, and a data read operation for display to a memory controller (not shown). Synchronous-DRAM (SDRAM) controlled by a burst length of 8 will be taken as an example. The frame memory 100 has two memory banks, bank 1 and bank 2, bank 1 has first and second frame storage areas 100-1 and 100-2, and bank 2 stores third and fourth frames. There are regions 100-3 and 100-4. Here, the first to fourth frame storage areas 100-1, 100-2, 100-3, and 100-4 have a capacity for storing pixel data of one frame, respectively, and the first to fourth frame storage areas 100-1, 100-. 2,100-3 and 100-4 each have 1,024 row addresses, and have a column address of 256 words (where 1 word is 8 bits). One address stores eight Y pixels, two Cr pixels, two Cb pixels, and a total of 12 pixel data. Here, 1,024 row addresses mean the number of RAS boxes. The 256-word column address is derived by eight macroblocks per one RAS box * 32 boxes per macroblock (= 256 boxes).

The actual physical row address of the frame memory 100 is 000 _H to 3FF _H , 400 _H to 7FF _H for the first to fourth frame storage areas 100-1 to 100-4, respectively. , 800 _H to BFF _H and C00 _H to FFF _H. However, the first to fourth frame storage regions 100-1 to 100-4 exist independently, and the second and fourth frames corresponding to the macroblocks located at predetermined row addresses of the first frame storage region 100-1 are respectively provided. The macroblocks of the third frame storage areas 100-2 and 100-3 have the same row address. As such, the row address in the first to third frame storage areas 100-1 to 100-3 is referred to as a virtual row address. Then, based on the scheduling order of the frame memory 100 as shown in FIG. 2 during motion compensation, an address used to convert a virtual row address in a corresponding storage area in which a reference image is located into a physical row address is framed. It is called the frame offset address and is called RA [11:10]. That is, if RA [11:10] is '00', the first frame storage area 100-1, if '01', the second frame storage area 100-2, and if the '10', the third frame storage area 100 -3) and '11' indicate the fourth frame storage areas 100-4, respectively.

Here, the first and second frame storage areas 100-1 and 100-2 are used to store reconstructed I-picture or motion-compensated P-picture image data for use as a reference image for motion compensation and simultaneously for display. The three-frame storage area 100-3 is used to store the motion compensated B-picture image data, and the fourth frame storage area 100-4 stores the encoded bitstream input to the image decoder in units of predetermined bits. Used to save.

FIG. 2 shows a scheduling order of the frame memory 100 shown in FIG. 1, and the decoding order is I, P, B, B, P, B, B, P, B, B, P, B, B, I. , P, B, B, ... and the display order is I, B, B, P, B, B, P, B, B, P, B, B, P, I, B, B, ... For example, the display latency is 2 pictures. Here, the underlined portion indicates the picture currently being decoded, the arrow indicates the picture to be referred for motion compensation, and the storage area to which 'D' is added indicates that image data is being read out for display.

FIG. 3 illustrates a first example of a method for setting a RAS box for one frame in the frame memory 100 shown in FIG. 1. For example, when one frame includes 1,920 pixels * 1,088 pixels, 15 RAS boxes are illustrated. * 68 RAS boxes, divided into 1,020 RAS (Row Address Strobe) boxes. That is, the number of the RAS box is the row address (RA) of the frame memory 100. Here, one RAS box is composed of eight macroblocks * 1 macroblocks and a total of eight macroblocks MB0 to MB7. Each macroblock is divided into four blocks b0 to b3 when the luminance Y block is taken as an example.

FIG. 4 shows an example of a macroblock structure in the RAS box shown in FIG. 3, and includes four luminance (Y) blocks, one color difference (Cr) block, and one color difference (Cb) block. The luminance (Y) block consists of eight boxes (b0-0 to b0-7, b1-0 to b1-7, b2-0 to b2-7, and b3-0 to b3-7), respectively, and two color differences. The (Cr, Cb) block is composed of eight sub boxes (sb0-0 to sb0-7, sb1-0 to sb1-7, sb2-0 to sb2-7, sb3-0 to sb3-7), respectively. Then, 8 pixel data in 8 * 1 format for each box constituting the Y block, 2 pixel data in 2 * 1 format for each box constituting the Cr block, and 2 * 1 format for each box constituting the Cb block. There are two pixel data of.

On the other hand, the start address of the current macroblock MB to be compensated for motion, that is, the slice position (slice_pos) and the macroblock position (mb_pos), and the motion vectors (mv_v, mv_h) are respectively located in the rectangular coordinates of x and y. However, in the actual frame memory, elements present in two dimensions are represented by linear addresses instead of x and y. To this end, an address generation core is used. The reference point is obtained by using the start address of the current macroblock MB to be motion compensated, that is, the slice position (slice_pos) and the macroblock position (mb_pos), and the motion vectors (mv_v and mv_h). Make To do this, the address generation core calculates the following general formula.

Here, slice_width is 120, indicating that there are 120 macroblocks in the horizontal direction in one frame (1920 pixels * 1088 pixels).

Fig. 5 is a block diagram showing a first embodiment of the address generating apparatus according to the present invention, which is composed of first to second address generating cores 51 and 52 and an adder 53. Figs.

The apparatus of the present invention is used by modifying Equation 1 as follows.

That is, in FIG. 5, the first address generation core 51 receives the start address of the current macroblock MB to be motion compensated, that is, the slice position slice_pos and the macroblock position mb_pos. Perform left operation. The second address generation core 52 receives the motion vectors mv_v and mv_h and performs the right operation of Equation 2 above. The adder 53 receives the output of the first to second address generation cores 51 and 52 and finally outputs an 18-bit reference point (RP) related address.

On the other hand, the above detailed description is intended to describe particular embodiments presented herein and is not intended to limit the present invention. Those skilled in the art may make various changes and modifications according to the structure of the RAS box and the structure of the macroblock block within the technical spirit of the present invention with reference to the above detailed description and drawings.

As described above, the apparatus of the present invention includes one region for storing reference image data, one region for storing decoded image data for display, and one region for storing an encoded bitstream input to the image decoder. In the frame memory implemented on the memory module of, it is possible to generate an address related to the start address of the current macroblock and the reference point of the macroblock predicted by the motion vector.

Claims (1)

In a frame memory mapped to a plurality of RAS boxes having a predetermined macroblock structure, A first address generation core 51 for inputting start addresses (slice_pos, mb_pos) of the current macroblock and generating a linear address for the start address; A second address generation core 52 for inputting horizontal and vertical motion vectors mv_h and mv_v of the current macroblock, and generating linear addresses for the horizontal and vertical motion vectors; And And an adder (53) for adding the outputs of the first to second address generation cores to output linear addresses with respect to the reference points of the predicted macroblocks.