KR100248653B1 - Method for transitioning a state of blocks during address generation in a frame memory - Google Patents

Abstract

Disclosed is a block state transition method when an address is generated in a frame memory used in a motion compensation device. The block state transition method includes the steps of checking the motion estimation and the compensation mode of the predicted macroblock; Examining the macroblock pattern of the predicted macroblock; If the motion estimation and compensation mode is a field or 16 * 8 and the macroblock pattern is forward prediction, fetching while transitioning to block b0, b1, b2, b3 state order; If the motion estimation and compensation mode is frame or dual prime and the macroblock pattern is forward prediction, fetching while transitioning to block b0, b2, b1, b3 state order; If the motion estimation and compensation mode is a field or 16 * 8 and the macroblock pattern is bidirectional prediction, fetching while transitioning to blocks b0, b1, b0, b1, b2, b3, b2, b3 states; And when the motion estimation and compensation mode is frame or dual prime and the macroblock pattern is bidirectional prediction, transitioning and fetching in the order of blocks b0, b2, b0, b2, b1, b3, b1, b3 states.

Description

Block state transition method when address occurs in frame memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory for a motion compensation device, and more particularly, when generating a row address (RA) and a column address (CA) for reading a predicted macroblock from the frame memory. A block state transition method for transitioning a block state to be fetched according to a motion estimation and compensation mode of a block and a macroblock pattern.

The motion compensation technique used in the Moving Picture Experts Group (MPEG) -2 standard is to reduce temporal redundancy by estimating and compensating for motion between two adjacent temporal pictures in macroblock units. That is, in the motion estimation and compensation process, a neighboring image is compared with the current image to detect a motion vector, which is information about an object's motion, and the current image is predicted using the motion vector.

In an MPEG-2 video encoder using such a motion compensation technique, the P picture performs forward motion compensation on the basis of the I picture or P picture of the previous picture with respect to the current picture, and the B picture performs the current picture. The best one is selected from among motion compensation blocks obtained by performing forward motion compensation, reverse motion compensation, and interpolated motion compensation based on the I picture or P picture of the previous picture and the I picture or P picture of the next picture.

Methods for motion estimation and compensation include frame motion estimation and compensation mode, field motion estimation and compensation mode, dual prime motion estimation and compensation mode, and basically all motion estimation and compensation are half pixel. It is specified to have a half-pel unit.

Among these, frame motion estimation and compensation mode has been used since MPEG-1, and motion estimation and compensation are performed in a frame structure without distinguishing a top field or even field and a bottom field or odd field. do. To this end, a full search is performed on the macroblock MB to be encoded of the current frame up to half-pixel precision in the search region of the reference frame, thereby obtaining the smallest mean absolute error (MAE). The position to generate is determined as a motion vector for the macroblock. In fact, since data is given in units of pixels, a pixel-by-pixel motion vector is obtained through the first-order full search in pixel units, and then a half-pixel motion vector is obtained through interpolation and a second full search in half-pixel units. In the case of frame motion estimation, one motion vector is transmitted per one macroblock for a P picture, and one or two motion vectors are transmitted per one macroblock for a B picture. The number of bits required for transmission is small.

Next, the field motion estimation and compensation mode performs motion estimation and compensation for each field in the picture of the frame structure. For this purpose, the upper and lower, upper and upper, lower and upper, lower and lower positions in the unit of 16 * 8 (pixels) sub macroblocks between upper and lower fields of the current frame and upper and lower fields of the reference frame, respectively. After four motion vectors are obtained, one motion vector is generated to generate a minimum motion compensation error for each of the upper and lower fields of the current frame. Therefore, two motion vectors per macroblock for a P picture and two or four motion vectors per macroblock for a B picture are transmitted. The MPEG-2 image encoder applies all the frame / field prediction modes to all macroblocks, and then uses the prediction mode having the smaller prediction error. Meanwhile, since the prediction mode used by the encoder is transmitted in the MPEG-2 image decoder, motion compensation is performed to restore the image.

On the other hand, as a variation of the field motion estimation and compensation mode, there are 16 * 8 (pixels) motion estimation and compensation modes. In this mode, two motion vectors are used for each macroblock, and the first motion vector is the top 16. For the * 8 region, the second motion vector is used for the lower 16 * 8 region. In the case of a bidirectional predicted macroblock, four motion vectors are used, two for forward prediction and two for backward prediction.

Next, the dual prime motion estimation and compensation mode transmits only one motion vector and differential motion vector (dmv) per macroblock, and is known to be effective for sequences with relatively slow motion. This mode is specified to be used only when the B picture is not used. That is, when the B picture is allowed, a better picture quality can be obtained using the B picture. However, when the B picture is not allowed, the dual prime prediction mode can be used to improve the picture quality with as little bit generation as possible. . In the dual prime prediction mode, first, the motion vectors of the upper, upper, and lower part of the four motion vectors obtained from the field prediction mode from upper to lower, upper to upper, lower to upper, lower to lower are used as the basic motion vectors. The upper and lower motion vectors and upper and lower motion vectors are scaled (* 2, * 2/3) and truncated, respectively, to form a basic motion vector. Next, each of the four basic motion vectors thus created is fine-tuned by -1, 0, and 1 in the horizontal and vertical directions to minimize the motion compensation error for the two 16 * 8 (pixels) sub macroblocks. A motion vector and a differential motion vector are transmitted. Since the dual prime prediction mode has a large amount of computation in the image encoder, it is necessary to calculate nine prediction candidate values per one basic motion vector. Therefore, the basic motion vector and the differential motion vector of one of 36 candidates must be calculated. Meanwhile, the image decoder can be implemented relatively simply because only two field motion vectors need to be calculated from the transmitted basic motion vector and the differential motion vector.

The frame memory is used to store the I picture or P picture of the previous picture and the I picture or P picture of the next picture as the reference picture for motion compensation. In addition, the frame memory is used to temporarily store a decoded picture and fetch it according to the display order since the decoding order and the display order are different in the MPEG-2 video decoder.

However, the frame memory as described above must have a capacity to store at least three frames of image data according to the I picture and the P picture or the distance M between the P picture and the P picture, and thus the price thereof is expensive, and therefore, the entire picture. In addition to raising the price of the decoder, there is a problem that the delay time from the completion of decoding to the display increases.

Accordingly, the present invention has been made to solve the above-described problem, and includes an area for storing reference image data when compensating for motion, an area for storing decoded image data for display, and an encoded bitstream input to an image decoder. In the frame memory implemented on one memory module, when generating a row address and a column address to read the predicted macroblock from the frame memory, the motion estimation and compensation mode and the macroblock of the corresponding macroblock are generated. It is an object of the present invention to provide a block state transition method for transitioning a block state to be fetched according to a pattern.

In order to achieve the above object, a block state transition method according to the present invention when an address is generated in a frame memory includes first to fourth frames each having a predetermined RAS box structure and a predetermined macroblock structure and storing one frame of an image signal. In a frame memory composed of a storage area, when fetching luminance blocks b0 to b3 of a macroblock predicted by motion compensation, each frame has a predetermined RAS box structure and a predetermined macroblock structure, and outputs one frame of video signal. A frame memory comprising first to fourth frame storage areas for storing, when fetching luminance blocks b0 to b3 of a macroblock predicted by motion compensation, a motion estimation and a compensation mode of the predicted macroblock are examined. The first inspection step to; A second inspection step of inspecting the macroblock pattern of the predicted macroblock; As a result of the inspection in the first and second inspection steps, when the motion estimation and compensation mode is a field or 16 * 8 and the macroblock pattern is forward prediction, in the block b0 state, block b1, block b2, and block b3 states Fetching while transitioning; As a result of the inspection in the first and second inspection steps, when the motion estimation and compensation mode is frame or dual prime and the macroblock pattern is forward prediction, transition from block b0 state to block b2, block b1, block b3 state Fetching while; As a result of the inspection in the first and second inspection steps, when the motion estimation and compensation mode is a field or 16 * 8 and the macroblock pattern is bidirectional prediction, in the block b0 state, block b1, block b0 state, block b1, block b2 Fetching while transitioning to block b3, block b2, and block b3 states; And when the motion estimation and compensation mode is frame or dual prime and the macroblock pattern is bidirectional prediction in the first and second inspection steps, in the block b0 state, block b2, block b0 state, block b2, block b1. Fetching and transitioning in the order of block b3, block b1, and block b3 states.

1 is a diagram showing the structure of a frame memory adopted in the present invention;

2 is a diagram illustrating a scheduling order of the frame memory shown in FIG. 1;

3 is a diagram illustrating an example of a method for setting a RAS box for one frame in the frame memory shown in FIG. 1;

4 is a view showing an example of a macroblock structure in the RAS box shown in FIG.

5 is a state diagram showing a block state transition method when an address is generated according to the present invention;

FIG. 6 is a block diagram illustrating an apparatus in which the block state transition method illustrated in FIG. 5 is executed.

* Explanation of symbols for main parts of the drawings

100: frame memory 200: memory control unit

100-1 to 100-4: First to fourth frame storage areas

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 illustrates a structure of a frame memory adopted in the present invention, in which the frame memory 100 includes a restored image data write operation, a data read operation for motion compensation, and a data read operation for display to a memory controller (not shown). Synchronous-DRAM (SDRAM) controlled by a burst length of 8 will be taken as an example. The frame memory 100 has two memory banks, bank 1 and bank 2, bank 1 has first and second frame storage areas 100-1 and 100-2, and bank 2 stores third and fourth frames. There are regions 100-3 and 100-4. Here, the first to fourth frame storage areas 100-1, 100-2, 100-3, and 100-4 have a capacity for storing pixel data of one frame, respectively, and the first to fourth frame storage areas 100-1, 100-. 2,100-3 and 100-4 each have 1,024 row addresses, and have a column address of 256 words (where 1 word is 8 bits). One address stores eight Y pixels, two Cr pixels, two Cb pixels, and a total of 12 pixel data. Here, 1,024 row addresses mean the number of RAS boxes. The column address of 256 words is derived by 8 macroblocks per one RAS box * 32 pixels per macroblock (= 256 pixels).

The actual physical row address of the frame memory 100 is 000 _H to 3FF _H , 400 _H to 7FF _H for the first to fourth frame storage areas 100-1 to 100-4, respectively. , 800 _H to BFF _H and C00 _H to FFF _H. However, the first to fourth frame storage regions 100-1 to 100-4 exist independently, and the second and fourth frames corresponding to the macroblocks located at predetermined row addresses of the first frame storage region 100-1 are respectively provided. The macroblocks of the third frame storage areas 100-2 and 100-3 have the same row address. As such, the row address in the first to third frame storage areas 100-1 to 100-3 is referred to as a virtual row address. Then, based on the scheduling order of the frame memory 100 as shown in FIG. 2 during motion compensation, an address used to convert a virtual row address in a corresponding storage area in which a reference image is located into a physical row address is framed. It is called the frame offset address and is called RA [11:10]. That is, if RA [11:10] is '00', the first frame storage area 100-1, if '01', the second frame storage area 100-2, and if the '10', the third frame storage area 100 -3) and '11' indicate the fourth frame storage areas 100-4, respectively.

Here, the first and second frame storage areas 100-1 and 100-2 are used to store reconstructed I-picture or motion-compensated P-picture image data for use as a reference image for motion compensation and simultaneously for display. The three-frame storage area 100-3 is used to store the motion compensated B-picture image data, and the fourth frame storage area 100-4 stores the encoded bitstream input to the image decoder in units of predetermined bits. Used to save.

FIG. 2 shows a scheduling order of the frame memory 100 shown in FIG. 1, and the decoding order is I, P, B, B, P, B, B, P, B, B, P, B, B, I. , P, B, B, ... and the display order is I, B, B, P, B, B, P, B, B, P, B, B, P, I, B, B, ... For example, the display latency is 2 pictures. Here, the underlined portion indicates the picture currently being decoded, the arrow indicates the picture to be referred for motion compensation, and the storage area to which 'D' is added indicates that image data is fetched for display.

FIG. 3 shows an example of a method for setting a RAS box for one frame in the frame memory 100 shown in FIG. 1. For example, when one frame includes 1,920 pixels * 1,088 pixels, 30 RAS boxes * 34 It is divided into RAS boxes, a total of 1,020 Row Address Strobe (RAS) boxes. That is, the number of the RAS box is the row address (RA) of the frame memory 100. Here, one RAS box is composed of four macroblocks * 2 macroblocks and a total of eight macroblocks MB0 to MB7. Each macroblock is divided into four blocks b0 to b3 when the luminance Y block is taken as an example.

FIG. 4 shows an example of a macroblock structure in the RAS box shown in FIG. 3, with four luminance (Y) blocks b0 to b3, one color difference (Cr) block, and one color difference (Cb) block. Four luminance (Y) blocks are composed of eight boxes (b0-0 to b0-7, b1-0 to b1-7, b2-0 to b2-7, and b3-0 to b3-7), respectively. Each of the two color difference (Cr, Cb) blocks has eight sub boxes (sb0-0 to sb0-7, sb1-0 to sb1-7, sb2-0 to sb2-7, and sb3-0 to sb3-7). It consists of. Then, 8 pixel data in 8 * 1 format for each box constituting the Y block, 2 pixel data in 2 * 1 format for each box constituting the Cr block, and 2 * 1 format for each box constituting the Cb block. There are two pixel data of.

3 and 4, when the open dress CA [7: 0] is examined, the position of the macro block in one RAS box is CA [7: 5] and the position of the block in the macro block. CA [4: 3], the position of the box in the block is called CA [2: 0]. In addition, a line in which the row address is changed in one frame is called a RAS line, and a line in which the open address is changed is called a CAS (Column Address Strobe) line.

5 is a state diagram illustrating a method for transitioning a block state when an address is generated according to the present invention. Herein, when one macroblock is to be read from the frame memory 100, it is assumed that two blocks are fetched in one fetch. In general, blocks b0 and b1 are fetched, and then a predetermined time elapses, then blocks b2 and b3 are fetched. However, there are some exceptions to this. That is, in the case of bidirectional prediction, otherwise, the block fetch pattern should be changed, and in the case of frame prediction or field prediction, the block fetch pattern should be changed, whereas one frame is composed of macroblocks of the field structure. Some examples are as follows.

First, when mb_forward = '1', mb_backward (weak mb_b in FIG. 5) = '1', that is, bidirectional prediction, and motion type (motion_type (weak in mt in FIG. 5) is field prediction), b0, b1, Fetch blocks in the order b0, b1, b2, b3, b2, b3.

Second, when mb_forward = '0', mb_backward = '1', that is, backward prediction, and the motion type is field prediction, the blocks are fetched in the order of b0, b1, b2, and b3.

Third, when mb_forward = '1', mb_backward = '0', that is, forward prediction, and the motion type is frame prediction, the blocks are fetched in the order of b0, b2, b1, and b3.

Next, a situation other than the above three cases will be described with reference to FIG. 5.

In Fig. 5, it is initially in the "IDLE" state, and then transitions to the "block b0" state when the "pds" signal indicating the start of the macroblock is "1." In the "block b0" state, the motion estimation and compensation mode is performed. When the motion estimation and compensation mode is a field or 16 * 8, the state transitions to the "block b1" state, and in the "block b1" state, the macroblock pattern is examined and bidirectional prediction (i.e., mb_b = '1') is performed. ), The transition to the "block b0" state and the "block b1" state is cleared while mb_b is cleared, while the "block b2" and "block b2" and " Block b3 "state. In the" block b3 "state, the macroblock pattern is examined, and in the case of bidirectional prediction (i.e., mb_b = '1'), mb_b is cleared while the" block b2 "state and" block b3 "state. Transitions sequentially to "block b3", unless mb_b = '1'. Transition to the "IDLE" state.

Next, when the "pds" signal indicating the start of the macroblock in the "IDLE" state is "1", the state transitions to the "block b0" state. In the "block b0" state, the motion estimation and compensation mode is checked to determine the motion estimation and compensation. When the mode is frame or dual prime, the state transitions to the "block b2" state. In the "block b2" state, the macroblock pattern is examined, and in the bidirectional prediction (ie, mb_b = '1'), mb_b is cleared and "block b0" is checked. Transition to "block b2" state sequentially while transitioning to "block b1" and "block b3" states while updating the macroblock pattern if mb_b = '1' is not in the "block b2" state In the " block b3 " state, the macroblock pattern is examined, and in the case of bidirectional prediction (i.e., mb_b = '1'), mb_b is cleared and the block is sequentially shifted to the " block b1 " state and " block b3 " state. Block b3 "state, if mb_b = '1', then" IDLE "state Transition

Summarizing the above state transitions, the motion estimation and compensation mode is a field or 16 * 8, and in the case of forward prediction, state transitions from "block b0" to "block b1" to "block b2" to "block b3", If the motion estimation and compensation mode is field or 16 * 8, and bidirectional prediction, "block b0"-> "block b1"-> "block b0"-> "block b1"-> "block b2"-" block b3 " b2 "→ State transition from" block b3 ". On the other hand, when the motion estimation and compensation mode is frame or dual prime, and in the forward prediction, the state transitions from "block b0" to "block b2" → "block b1" to "block b3", and the motion estimation and compensation mode is framed. Or in the case of dual prime and bidirectional prediction, "block b0"-> "block b2"-> "block b0"-> "block b2"-" block b1 " → " block b3 " → " block b1 " → " block b3 " State transition.

FIG. 6 is a block diagram illustrating an apparatus in which the block state transition method of FIG. 5 is executed, and is typically performed by the memory controller 200. That is, the memory controller 200 inputs a start address, a motion vector, and various parameters of a current macroblock in a picture to be motion compensated, and fetches a corresponding macroblock of a picture to be referred to in units of blocks or boxes. Is applied to the frame memory 100 via the address bus. In addition, various control signals for controlling write and read operations of the frame memory 100 are applied to the frame memory 100.

On the other hand, the above detailed description is intended to describe particular embodiments presented herein and is not intended to limit the present invention. Those skilled in the art may make various changes and modifications according to the structure of the RAS box and the structure of the macroblock block within the technical spirit of the present invention with reference to the above detailed description and drawings.

As described above, in the frame memory in which the first to fourth frame storage areas are implemented on one memory module, a row address and a column address are generated to read the predicted macroblock from the frame memory. In this case, the block state to be fetched can be shifted according to the motion estimation and compensation mode and the macroblock pattern of the macroblock.

Claims (2)

A frame memory comprising first to fourth frame storage areas each having a predetermined RAS box structure and a predetermined macroblock structure and storing one frame of an image signal, the luminance block b0 of the macroblock predicted by motion compensation. To fetch block b3, A first inspection step of examining a motion estimation and a compensation mode of the predicted macroblock; A second inspection step of inspecting the macroblock pattern of the predicted macroblock; As a result of the inspection in the first and second inspection steps, when the motion estimation and compensation mode is a field or 16 * 8 and the macroblock pattern is forward prediction, in the block b0 state, block b1, block b2, and block b3 states Fetching while transitioning; As a result of the inspection in the first and second inspection steps, when the motion estimation and compensation mode is frame or dual prime and the macroblock pattern is forward prediction, transition from block b0 state to block b2, block b1, block b3 state Fetching while; As a result of the inspection in the first and second inspection steps, when the motion estimation and compensation mode is a field or 16 * 8 and the macroblock pattern is bidirectional prediction, in the block b0 state, block b1, block b0 state, block b1, block b2 Fetching while transitioning to block b3, block b2, and block b3 states; And As a result of the inspection in the first and second inspection steps, when the motion estimation and compensation mode is frame or dual prime and the macroblock pattern is bidirectional prediction, in block b0 state, block b2, block b0 state, block b2, block b1, And a step of fetching and transitioning in the order of block b3, block b1, and block b3 states. A frame memory comprising first to fourth frame storage areas each having a predetermined RAS box structure and a predetermined macroblock structure and storing one frame of an image signal, the luminance block b0 of the macroblock predicted by motion compensation. To fetch block b3, Transitioning to a block b0 state when a signal indicating the start of the macroblock is applied; A first checking step of checking a motion estimation and a compensation mode of the predicted macroblock in the block b0 state; A first transition step of transitioning from the block b0 state to the block b1 state if the motion estimation and compensation mode is a field or 16 * 8 in the first inspection step; A second transition step of transitioning from the block b0 state to the block b2 state when the motion estimation and compensation mode is a frame or dual prime in the first inspection step; A second inspection step of examining the macroblock patterns of the predicted macroblocks in the block b1 state and the block b2 state respectively transitioned in the first and second transition steps; In the second inspection step, when the macroblock pattern is the forward prediction, a third transition is made from the block b1 state to the block b2 and the block b3 states, and from the block b2 state to the block b1 and block b3 states. step; And If the macroblock pattern is bidirectional predicted as a result of the inspection in the second inspection step, the block b1 state is changed to block b0, block b1, block b2, block b3, block b2, block b3, and in the block b2 state. And a fourth transition step of transitioning to the block b0, block b2, block b1, block b3, block b1, and block b3 states.

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