KR100226704B1 - Method for calculating address distances in a frame memory - Google Patents

Abstract

Disclosed is a method for calculating an address distance in a frame memory used in a motion compensation device. In the address distance calculation method, if the reference point of the predicted macroblock is located in one of the blocks b0 and b2 in one macroblock of the macroblocks MB0 to MB2 and MB4 to MB6, CA [4: 3]. ] Increases by 1, and located in one of the blocks b1, b3 increases CA [7: 5] by 1, decreases CA [4: 3] by 1, and the reference point is the macroblocks MB3, MB7. If one is in one of the blocks (b0, b2) in one macroblock, CA [4: 3] is increased by one, and in one of the blocks (b1, b3), RA [9: 0] is increased by one. Decrease the CA [7: 5] by 3, decrease the CA [4: 3] by 1, and calculate the horizontal address distance, and the reference point of the predicted macroblock is the macro of one of the macroblocks MB0 to MB3. If located in one of the blocks (b0, b1) in the block, increase CA [4: 3] by 2; in one of blocks (b2, b3), increase CA [7: 5] by 4, CA [4 Decreases: 3] by 2, and the reference point If one is located in one of the blocks b0 and b1 in one of the macroblocks MB4 to MB7, CA [4: 3] is increased by two, and if it is located in one of the blocks b2 and b3, RA [9]. Vertical address distance is calculated by increasing: 0] by 30, decreasing CA [7: 5] by 4, and decreasing CA [4: 3] by 2.

Description

Address distance calculation method in frame memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory for a motion compensation device. In particular, when generating an address for reading a macroblock predicted by motion compensation in units of blocks, the present invention relates to a horizontal or vertical direction according to the position of a reference point of the predicted macroblock. An address distance calculation method for calculating an address of an adjacent block is provided.

The motion compensation technique used in the Moving Picture Experts Group (MPEG) -2 standard is to reduce temporal redundancy by estimating and compensating for motion between two adjacent temporal pictures in macroblock units. That is, in the motion estimation and compensation process, a neighboring image is compared with the current image to detect a motion vector, which is information about an object's motion, and the current image is predicted using the motion vector.

In an MPEG-2 video encoder using such a motion compensation technique, the P picture performs forward motion compensation on the basis of the I picture or P picture of the previous picture with respect to the current picture, and the B picture performs the current picture. The best one is selected from among motion compensation blocks obtained by performing forward motion compensation, reverse motion compensation, and interpolated motion compensation based on the I picture or P picture of the previous picture and the I picture or P picture of the next picture.

The frame memory is used to store the I picture or P picture of the previous picture and the I picture or P picture of the next picture as the reference picture for motion compensation. In addition, the frame memory is used to temporarily store the decoded picture and read out the display order in a MPEG-2 video decoder because the decoding order and the display order are different from each other.

However, the frame memory as described above must have a capacity to store at least three frames of image data according to the I picture and the P picture or the distance M between the P picture and the P picture, and thus the price thereof is expensive, and therefore, the entire picture. In addition to raising the price of the decoder, there is a problem that the delay time from the completion of decoding to the display increases.

Accordingly, the present invention has been made to solve the above-described problem, and includes a region for storing reference image data, a region for storing decoded image data for display, and an encoded bitstream input to an image decoder. In the frame memory implemented on one memory module, when generating an address for reading a macroblock predicted by motion compensation in units of blocks, the area is horizontal or vertical according to the position of a reference point of the predicted macroblock. It is an object of the present invention to provide a method for calculating an address distance for calculating addresses of blocks adjacent in a direction.

In order to achieve the above object, in the address distance calculation method according to the present invention, one frame includes a plurality of RAS boxes, and the RAS box includes eight macroblocks (MB0 to MB7) of 4 macroblocks * 2 macroblock formats. In the frame memory, when the row address RA [9: 0] and the column address CA [7: 0] are generated to read the macroblock predicted by the motion compensation in block units, the block memory is placed in a block horizontally adjacent to the arbitrary block. When the reference point of the predicted macroblock is located in one of the blocks b0 and b2 in one macroblock of the macroblocks MB0 to MB2 and MB4 to MB6 to calculate a horizontal address distance with respect to Increasing CA [4: 3] by 1 to calculate the horizontal address distance; When the reference point is located in one of the blocks b1 and b3 in one of the macroblocks MB0 to MB2 and MB4 to MB6, increase CA [7: 5] by 1 and increase CA [4]. Decrement: 3] by 1 to calculate the horizontal address distance; Calculating the horizontal address distance by increasing CA [4: 3] by 1 when the reference point is located in one of the blocks b0 and b2 in one of the macroblocks MB3 and MB7 ; And when the reference point is located in one of the blocks b1 and b3 in one of the macroblocks MB3 and MB7, increase RA [9: 0] by 1 and increase CA [7: 5]. Decrement 3 by 3 and decrement CA [4: 3] by 1 to calculate the horizontal address distance, and to calculate a vertical address distance for a block vertically adjacent to any block. Calculating a vertical address distance by increasing CA [4: 3] by 2 when the reference point of is located in one of the blocks b0 and b1 in one of the macroblocks MB0 to MB3 ; When the reference point is located in one of the blocks b2 and b3 in one of the macroblocks MB0 to MB3, increase CA [7: 5] by 4 and increase CA [4: 3]. Reducing the two to calculate the vertical address distance; Calculating the vertical address distance by increasing CA [4: 3] by 2 when the reference point is located in one of the blocks b0 and b1 in one of the macroblocks MB4 to MB7 ; And when the reference point is located in one of the blocks b2 and b3 in one of the macroblocks MB4 to MB7, increase RA [9: 0] by 30 and increase CA [7: 5]. Reducing 4 by and reducing CA [4: 3] by 2 to calculate the vertical address distance.

1 is a diagram showing the structure of a frame memory adopted in the present invention;

2 is a diagram illustrating a scheduling order of the frame memory shown in FIG. 1;

3 is a view showing an example of a method for setting a RAS box for one frame used in the present invention in the frame memory shown in FIG. 1;

4 is an enlarged view of one RAS box and an adjacent RAS box in FIG. 3;

5 is a flowchart for explaining a horizontal address distance calculation method according to the present invention;

6 is a flowchart illustrating a method of calculating a vertical address distance according to the present invention.

* Explanation of symbols for main parts of the drawings

100: frame memory 200: memory control unit

100-1 to 100-4: First to fourth frame storage areas

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 illustrates a structure of a frame memory adopted in the present invention, in which the frame memory 100 includes a restored image data write operation, a data read operation for motion compensation, and a data read operation for display to a memory controller (not shown). Synchronous-DRAM (SDRAM) controlled by a burst length of 8 will be taken as an example. The frame memory 100 has two memory banks, bank 1 and bank 2, bank 1 has first and second frame storage areas 100-1 and 100-2, and bank 2 stores third and fourth frames. There are regions 100-3 and 100-4. Here, the first to fourth frame storage areas 100-1, 100-2, 100-3, and 100-4 have a capacity for storing pixel data of one frame, respectively, and the first to fourth frame storage areas 100-1, 100-. 2,100-3 and 100-4 each have 1,024 row addresses, and have a column address of 256 words (where 1 word is 8 bits). One address stores eight Y pixels, two Cr pixels, two Cb pixels, and a total of 12 pixel data. Here, 1,024 row addresses mean the number of RAS boxes. The column address of 256 words is derived by 8 macroblocks per one RAS box * 32 pixels per macroblock (= 256 pixels).

The actual physical row address of the frame memory 100 is 000 _H to 3FF _H , 400 _H to 7FF _H for the first to fourth frame storage areas 100-1 to 100-4, respectively. , 800 _H to BFF _H and C00 _H to FFF _H. However, the first to fourth frame storage regions 100-1 to 100-4 exist independently, and the second and fourth frames corresponding to the macroblocks located at predetermined row addresses of the first frame storage region 100-1 are respectively provided. The macroblocks of the third frame storage areas 100-2 and 100-3 have the same row address. As such, the row address in the first to third frame storage areas 100-1 to 100-3 is referred to as a virtual row address. Then, based on the scheduling order of the frame memory 100 as shown in FIG. 2 during motion compensation, an address used to convert a virtual row address in a corresponding storage area in which a reference image is located into a physical row address is framed. It is called the frame offset address and is called RA [11:10]. That is, if RA [11:10] is '00', the first frame storage area 100-1, if '01', the second frame storage area 100-2, and if the '10', the third frame storage area 100 -3) and '11' indicate the fourth frame storage areas 100-4, respectively.

Here, the first and second frame storage areas 100-1 and 100-2 are used to store reconstructed I-picture or motion-compensated P-picture image data for use as a reference image for motion compensation and simultaneously for display. The three-frame storage area 100-3 is used to store the motion compensated B-picture image data, and the fourth frame storage area 100-4 stores the encoded bitstream input to the image decoder in units of predetermined bits. Used to save.

FIG. 2 shows a scheduling order of the frame memory 100 shown in FIG. 1, and the decoding order is I, P, B, B, P, B, B, P, B, B, P, B, B, I. , P, B, B, ... and the display order is I, B, B, P, B, B, P, B, B, P, B, B, P, I, B, B, ... For example, the display latency is 2 pictures. Here, the underlined portion indicates the picture currently being decoded, the arrow indicates the picture to be referred for motion compensation, and the storage area to which 'D' is added indicates that image data is being read out for display.

FIG. 3 shows an example of a method of setting a RAS box for one frame used in the present invention in the frame memory 100 shown in FIG. 1. For example, when one frame includes 1,920 pixels * 1,088 pixels, 30 pieces are used. RAS Box * 34 RAS boxes, divided into a total of 1,020 Row Address Strobe (RAS) boxes. In other words, the number of the RAS box becomes the row address RA [9: 0] of the frame memory 100. Here, one RAS box is composed of four macroblocks * 2 macroblocks and a total of eight macroblocks MB0 to MB7. For example, each macroblock is divided into four blocks b0 to b3 when the luminance (Y) block is taken as an example, and each block b0 to b3 is usually divided into eight boxes having a 2 * 4 or 1 * 8 structure. In the box of 2 * 4 structure, each box is composed of 8 pixels of 4 * 2 structure, and each box is composed of 8 pixels of 8 * 1 structure in a box of 1 * 8 structure. In this case, the column address CA [7: 0] of the frame memory 100 is a column address CA [7: 5) indicating the position of the macroblock existing in the RAS box located at the corresponding column address, and the corresponding macro. Column address CA [4: 3], which indicates the position of the block existing in the block, and column address CA [2: 0], which indicates the position of the box in the block.

FIG. 4 is an enlarged view of one RAS box and an adjacent RAS box in FIG. 3, in which hatched portions represent even fields (or upper fields), and unhatched portions represent radix fields (or lower fields).

5 is a flowchart illustrating a method of calculating a horizontal address distance according to the present invention, wherein the reference point calculating step (step 51) of the predicted macroblock MB is performed, the macroblock in which the reference point is located, and the horizontal address distance according to the block. Comprising the step (52 to 58).

6 is a flowchart illustrating a method for calculating a vertical address distance according to the present invention, wherein the reference point calculation step (step 61) of the predicted macroblock MB is performed, the macroblock at which the reference point is located, and the vertical address distance according to the block Calculating (steps 62 to 68).

Next, an address distance calculation method according to the present invention will be described with reference to FIGS. 5 and 6.

In the frame memory 100, an address required for reading a predicted macroblock from a start address and a motion vector of a current macroblock includes a field slice structure, a half pixel compensation presence, a frame map structure, and a predicted macroblock. It depends on the mismatch of the and the location of the reference point. Here, the reference point indicates the position of the leftmost pixel above the predicted macroblock. On the other hand, when the predicted macroblock is read in units of blocks, addresses required to read the blocks b0, b1, b2, and b3 vary according to the position of the reference point. In this case, the horizontal distance of the address for calculating an address required for reading the block b1 from the block b0 or reading the block b3 from the block b2 is referred to as a horizontal address distance (hereinafter, referred to as a horizontal address distance). The vertical distance of the address for calculating an address required for reading block b2 from block b0 or reading block b3 from block b1 is referred to as HAD. Vertical Address Distance (hereafter referred to as VAD). In this case, HAD and VAD are different depending on whether the RAS line is hanging on the corresponding RAS box, or the CAS line is hanging, or both the RAS line and the CAS line are hanging.

Let's take a look at the HAD.

First, the reference point of the macroblock predicted by the motion compensation is calculated by the slice position, the macroblock position and the motion vector of the macroblock used for the prediction (step 51), and the macroblock predicted by the frame memory 100 is calculated. The macroblock and the block in which the reference point is located are determined (steps 52, 53, and 56). Looking at each case according to the position of the reference point as follows.

First, in any RAS box (RAS _i ), the macroblock MB _i where the predicted macroblock reference point is located is one of MB0, MB1, MB2, MB4, MB5, MB6, and the reference point in the macroblock. When the block blk _{i in} which is located is one of the blocks b0 and b2, the RAS line is not caught but only the CAS line. In this case, for the block (hblk _{i + 1} ) horizontally adjacent to the block (blk _i ), HAD is

blk _{i + 1} = hblk _i + 1

Becomes Therefore, when reading the block hblk _{i + 1} , the CA [4: 3] is increased by one with respect to the column address CA [7: 0] of the block blk _i (step 54).

Second, the macroblock MB _{i in} which the reference point of the predicted macroblock is located in any RAS box RAS _i is one of MB0, MB1, MB2, MB4, MB5, MB6, and the reference point in the macroblock. When the block blk _{i in} which is located is one of the blocks b1 and b3, the RAS line is not caught but only the CAS line. In this case, for the block (hblk _{i + 1} ) horizontally adjacent to the block (blk _i ), HAD is

hblk _{i + 1} = blk _i -1

MB _{i + 1} = MB _i + 1

Becomes Therefore, to read the block hblk _{i + 1} , increase CA [7: 5] by 1 and decrease CA [4: 3] by 1 for the column address CA [7: 0] of the block blk _i . (Step 55).

Third, the macroblock MB _{i in} which the reference point of the predicted macroblock is located in any RAS box RAS _i is one of MB3 and MB7, and the block in which the reference point is located is blk _i . In the case of one of these blocks b0 and b2, the RAS line does not hang but only the CAS line. In this case, for the block (hblk _{i + 1} ) horizontally adjacent to the block (blk _i ), HAD is

hblk _{i + 1} = blk _i + 1

Becomes Accordingly, in the case of reading the block hblk _{i + 1} , the CA [4: 3] is increased by one with respect to the column address CA [7: 0] of the block blk _i (step 57).

Fourth, the macroblock MB _{i in} which the reference point of the predicted macroblock is located in any RAS box RAS _i is one of MB3 and MB7, and the block in which the reference point is located is blk _i . In the case of one of the blocks b1 and b3, both the RAS line and the CAS line are caught. In this case, for the block (hblk _{i + 1} ) horizontally adjacent to the block (blk _i ), HAD is

hblk _{i + 1} = blk _i -1

MB _{i + 1} = MB _i -3

RAS _{i + 1} = RAS _i + 1

Becomes Therefore, to read the block hblk _{i + 1} , the row address RA [9: 0] of the block blk _i is increased by 1, and CA [7: 5] is increased by 3 for the column address CA [7: 0]. Reduce CA [4: 3] by 1 (step 58).

Next, let's look at VAD.

First, the reference point of the macroblock predicted by the motion compensation is calculated based on the slice position, the macroblock position and the motion vector of the macroblock used for the prediction (step 61), and the macroblock predicted by the frame memory 100. The macroblock and the block in which the reference point is located are determined (steps 62, 63, and 66). Looking at each case according to the position of the reference point as follows.

First, in any RAS box (RAS _i ), the macro block MB _{i in} which the reference point of the predicted macroblock is located is one of MB0, MB1, MB2, and MB3, and the block in which the reference point is located in the macroblock. When (blk _i ) is one of the blocks b0 and b1, the RAS line does not hang but only the CAS line. At this time, for the block (vblk _{i + 1} ) perpendicular to the block blk _i , VAD is

vblk _{i + 1} = blk _i + 2

Becomes Therefore, in order to read the block vblk _{i + 1} , CA [4: 3] is increased by 2 with respect to the column address CA [7: 0] of the block blk _i (step 64).

Second, the macroblock MB _{i in} which the reference point of the predicted macroblock is located in any RAS box RAS _i is one of MB0, MB1, MB2, and MB3, and the block in which the reference point is located in the corresponding macroblock. When (blk _i ) is one of the blocks b2 and b3, the RAS line does not hang but only the CAS line. At this time, for the block (vblk _{i + 1} ) perpendicular to the block blk _i , VAD is

vblk _{i + 1} = blk _i -2

MB _{i + 1} = MB _i + 4

Becomes Therefore, to read the block vblk _{i + 1} , increase CA [7: 5] by 4 and decrease CA [4: 3] by 2 for the column address CA [7: 0] of the block (blk _i ). (Step 65).

Third, the macroblock MB _{i in} which the reference point of the predicted macroblock is located in any RAS box RAS _i is one of MB4, MB5, MB6, and MB7, and the block in which the reference point is located in the corresponding macroblock. When (blk _i ) is one of the blocks b0 and b1, the RAS line does not hang but only the CAS line. At this time, for the block (vblk _{i + 1} ) perpendicular to the block blk _i , VAD is

vblk _{i + 1} = blk _i + 2

Becomes Therefore, in order to read the block vblk _{i + 1} , CA [4: 3] is increased by two with respect to the column address CA [7: 0] of the block blk _i (step 67).

Fourth, the macroblock MB _{i in} which the reference point of the predicted macroblock is located in any RAS box RAS _i is one of MB4, MB5, MB6, and MB7, and the block in which the reference point is located in the macroblock. When (blk _i ) is one of the blocks b2 and b3, both the RAS line and the CAS line are caught. In this case, the block with respect to _(i blk) and the vertically adjacent block (blk _{i + 1)} is HAD

blk _{i + 1} = blk _i -2

MB _{i + 1} = MB _i -4

RAS _{i + 1} = RAS _i + 30

Becomes To read block vblk _{i + 1} , increase row address RA [9: 0] by 30 in block blk _i , and decrease CA [7: 5] by 4 for column address CA [7: 0]. This is done by reducing CA [4: 3] by 2 (step 68).

On the other hand, the above detailed description is intended to describe particular embodiments presented herein and is not intended to limit the present invention. Those skilled in the art may make various changes and modifications according to the structure of the RAS box and the structure of the macroblock block within the technical spirit of the present invention with reference to the above detailed description and drawings.

As described above, according to the present invention, one memory includes an area for storing reference image data in motion compensation, an area for storing decoded image data for display, and an area for storing an encoded bitstream input to the image decoder. In the frame memory implemented on the module, when generating an address for reading the macroblock predicted by the motion vector and the start address of the current macroblock in units of blocks, the frame memory is horizontally or in accordance with the position of the reference point of the predicted macroblock. The addresses of adjacent blocks in the vertical direction can be calculated.

Claims (6)

One frame is composed of a plurality of RAS boxes, and the RAS box is a frame memory consisting of eight macroblocks (MB0 to MB7) of 4 macroblocks * 2 macroblock formats, and blocks a macroblock predicted by motion compensation. In the case of generating the row address RA [9: 0] and the column address CA [7: 0] to read in units, the method of calculating the horizontal address distance for a block horizontally adjacent to an arbitrary block, If the reference point of the predicted macroblock is located in one of the blocks b0 and b2 in one macroblock of the macroblocks MB0 to MB2 and MB4 to MB6, increase CA [4: 3] by 1 Calculating the horizontal address distance; When the reference point is located in one of the blocks b1 and b3 in one of the macroblocks MB0 to MB2 and MB4 to MB6, increase CA [7: 5] by 1 and increase CA [4]. Decrement: 3] by 1 to calculate the horizontal address distance; Calculating the horizontal address distance by increasing CA [4: 3] by 1 when the reference point is located in one of the blocks b0 and b2 in one of the macroblocks MB3 and MB7 ; And If the reference point is located in one of the blocks b1 and b3 in one of the macroblocks MB3 and MB7, increase RA [9: 0] by 1 and increase CA [7: 5] by one. And calculating the horizontal address distance by reducing the number of CAs by 3 and decreasing the CA [4: 3] by one. The method of claim 1, wherein the method further comprises determining a macroblock and a block in which the reference point of the predicted macroblock is located in the frame memory. One frame is composed of a plurality of RAS boxes, and the RAS box is a frame memory consisting of eight macroblocks (MB0 to MB7) of 4 macroblocks * 2 macroblock formats, and blocks a macroblock predicted by motion compensation. In the case of generating the row address RA [9: 0] and the column address CA [7: 0] to read in units, the method of calculating the vertical address distance for a block vertically adjacent to an arbitrary block, When the reference point of the predicted macroblock is located in one of the blocks b0 and b1 in one macroblock of the macroblocks MB0 to MB3, CA [4: 3] is increased by 2 to increase the vertical address. Calculating a distance; When the reference point is located in one of the blocks b2 and b3 in one of the macroblocks MB0 to MB3, increase CA [7: 5] by 4 and increase CA [4: 3]. Reducing the two to calculate the vertical address distance; Calculating the vertical address distance by increasing CA [4: 3] by 2 when the reference point is located in one of the blocks b0 and b1 in one of the macroblocks MB4 to MB7 ; And If the reference point is located in one of the blocks b2 and b3 in one of the macroblocks MB4 to MB7, RA [9: 0] is increased by 30 and CA [7: 5] is increased. And decreasing the CA [4: 3] by 2 to calculate the vertical address distance. 4. The method of claim 3, further comprising determining a macroblock and a block in which the reference point of the predicted macroblock is located in the frame memory. One frame is composed of a plurality of RAS boxes, and the RAS box is a frame memory consisting of eight macroblocks (MB0 to MB7) of 4 macroblocks * 2 macroblock formats, and blocks a macroblock predicted by motion compensation. When generating the row address RA [9: 0] and column address CA [7: 0] to read in units, in order to calculate the horizontal address distance for a block horizontally adjacent to any block, If the reference point of the predicted macroblock is located in one of the blocks b0 and b2 in one macroblock of the macroblocks MB0 to MB2 and MB4 to MB6, increase CA [4: 3] by 1 Calculating the horizontal address distance; When the reference point is located in one of the blocks b1 and b3 in one of the macroblocks MB0 to MB2 and MB4 to MB6, increase CA [7: 5] by 1 and increase CA [4]. Decrement: 3] by 1 to calculate the horizontal address distance; Calculating the horizontal address distance by increasing CA [4: 3] by 1 when the reference point is located in one of the blocks b0 and b2 in one of the macroblocks MB3 and MB7 ; And If the reference point is located in one of the blocks b1 and b3 in one of the macroblocks MB3 and MB7, increase RA [9: 0] by 1 and increase CA [7: 5] by one. Decreasing the CA [4: 3] by 1 to calculate the horizontal address distance; To calculate the vertical address distance for a block vertically adjacent to any block, When the reference point of the predicted macroblock is located in one of the blocks b0 and b1 in one macroblock of the macroblocks MB0 to MB3, CA [4: 3] is increased by 2 to increase the vertical address. Calculating a distance; When the reference point is located in one of the blocks b2 and b3 in one of the macroblocks MB0 to MB3, increase CA [7: 5] by 4 and increase CA [4: 3]. Reducing the two to calculate the vertical address distance; Calculating the vertical address distance by increasing CA [4: 3] by 2 when the reference point is located in one of the blocks b0 and b1 in one of the macroblocks MB4 to MB7 ; And If the reference point is located in one of the blocks b2 and b3 in one of the macroblocks MB4 to MB7, RA [9: 0] is increased by 30 and CA [7: 5] is increased. And decreasing the CA [4: 3] by 2 to calculate the vertical address distance. 6. The method of claim 5, wherein the method further comprises determining a macroblock and a block in which the reference point of the predicted macroblock is located in the frame memory.

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