KR100269427B1 - Method for generating address in a frame memory - Google Patents

Abstract

PURPOSE: A method for generating addresses in a frame memory is provided to generate an RA(Row Address), a CA(Column Address) and a PA(Pel Address) in order to read a predicted macro block as the frame memory. CONSTITUTION: A frame offset address, namely, RA(Row Address)'11:10', is decided on the basis of a scheduling order of a frame memory(S101). A start address of a current MB(Macro Block) for compensating a motion, namely, a slice position, an MB position and a motion vector are inputted(S102). Scales of inputted variables are agreed with each other(S103). Position of a predicted MB is decided(S104). A linear address is generated, an RA'9:0' and a CA(Column Address)'7:5' are decided from the linear address(S105). A CA'4:0' and a PA(Pel Address)'2:0' are decided(S106). Whether the inputted MB is the last MB is decided(S107). If so, a process is completed.

Description

Address generation method in frame memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory for a motion compensation device, in particular a row address (RA), a column address (CA) and a pixel address (PA address) PA for reading a predicted macroblock into the frame memory. The present invention relates to an address generating method for generating < RTI ID = 0.0 >

The motion compensation technique used in the Moving Picture Experts Group (MPEG) -2 standard is to reduce temporal redundancy by estimating and compensating for motion between two adjacent temporal pictures in macroblock units. That is, in the motion estimation and compensation process, a neighboring image is compared with the current image to detect a motion vector, which is information about an object's motion, and the current image is predicted using the motion vector.

In an MPEG-2 video encoder using such a motion compensation technique, the P picture performs forward motion compensation on the basis of the I picture or P picture of the previous picture with respect to the current picture, and the B picture performs the current picture. The best one is selected from among motion compensation blocks obtained by performing forward motion compensation, reverse motion compensation, and interpolated motion compensation based on the I picture or P picture of the previous picture and the I picture or P picture of the next picture.

The frame memory is used to store the I picture or P picture of the previous picture and the I picture or P picture of the next picture as the reference picture for motion compensation. In addition, the frame memory is used to temporarily store the decoded picture and read out the display order in a MPEG-2 video decoder because the decoding order and the display order are different from each other.

However, the frame memory as described above must have a capacity to store at least three frames of image data according to the I picture and the P picture or the distance M between the P picture and the P picture, and thus the price thereof is expensive, and therefore, the entire picture. In addition to raising the price of the decoder, there is a problem that the delay time from the completion of decoding to the display increases.

Accordingly, an object of the present invention is to solve the above-mentioned problems, in order to solve the above-mentioned problems, an area for storing reference image data when compensating for motion, an area for storing decoded image data for display, and a coded bitstream input to an image decoder. In a frame memory in which an area is implemented on one memory module, a location of a low address strobe (RAS) box where a macroblock predicted by a motion vector is located, a macroblock location in a corresponding RAS box, and a block in the corresponding macroblock An address generating method for generating an address for a position, a box position in a corresponding block, and a pixel position in a corresponding box is provided.

In order to achieve the above object, the address generation method according to the present invention includes one frame consisting of a plurality of RAS boxes, the RAS box has an 8 macroblock * 1 macroblock format, and the macroblock has 2 blocks for a luminance block. 2 block formats, the block has a 1 box * 8 box format, and the box has a format of 8 pixels * 1 pixels, the frame memory consisting of the first to fourth frame storage area, and the motion compensation A motion control device comprising a memory controller for supplying a start address of a current macroblock of a picture, a horizontal and vertical motion vector and various parameters as inputs, an address for reading a predicted macroblock, and various control signals to the frame memory; In

Adjusting the horizontal and vertical motion vectors to a macroblock scale;

Generating a first row address indicating a storage area in which a picture to be referred to for motion compensation is located based on a scheduling order of the frame memory;

Determining horizontal and vertical positions of the predicted macroblock using the horizontal and vertical motion vectors adjusted to the start address of the current macroblock and the macroblock scale;

Generating a second row address indicating a RAS box position in a corresponding storage area and a first column address indicating a macroblock position in a corresponding RAS box by using the predicted horizontal and vertical positions of the macroblock; And

A second column address indicating a block position in the macroblock, a third column address indicating a box position in the corresponding block, using the lower four bits of the horizontal and vertical motion vectors except for the half pixel flag; And generating a pixel address indicating a pixel position in the box.

In order to achieve the above object, the address generation method according to the present invention comprises one frame consisting of a plurality of RAS boxes, the RAS box has a format of 4 macroblocks * 2 macroblocks, and the macroblocks have 2 blocks for luminance blocks. * 2 block format, the block has a 2 box * 4 box format, the box has a 4 pixel * 2 pixel format, the frame memory consisting of the first to fourth frame storage area, and the motion compensation A motion control device comprising a memory controller for supplying a start address of a current macroblock of a picture, a horizontal and vertical motion vector and various parameters as inputs, an address for reading a predicted macroblock, and various control signals to the frame memory; In

Adjusting the horizontal and vertical motion vectors to a macroblock scale;

Generating a first row address indicating a storage area in which a picture to be referred to for motion compensation is located based on a scheduling order of the frame memory;

Determining horizontal and vertical positions of the predicted macroblock using the horizontal and vertical motion vectors adjusted to the start address of the current macroblock and the macroblock scale;

Generating a second row address representing a RAS box position in a corresponding storage area by using a quotient obtained by dividing the predicted macroblock's horizontal position and vertical position by 4 and 2, respectively;

Generating a first column address indicating a macroblock position in a corresponding RAS box using the remainder obtained by dividing the predicted macroblock's horizontal and vertical positions by 4 and 2, respectively; And

A second column address indicating a block position in the macroblock, a third column address indicating a box position in the corresponding block, using the lower four bits of the horizontal and vertical motion vectors except for the half pixel flag; And generating a pixel address indicating a pixel position in the box.

1 is a diagram showing the structure of a frame memory adopted in the present invention;

2 is a diagram illustrating a scheduling order of the frame memory shown in FIG. 1;

3 is a diagram illustrating a first example of a method for setting a RAS box for one frame in the frame memory shown in FIG. 1;

4 is a view showing an example of a macroblock structure in the RAS box shown in FIG.

5 is a flowchart for explaining a first embodiment of an address generating method according to the present invention;

6A and 6B are views illustrating the configuration of a horizontal motion vector and a vertical motion vector, respectively;

7 is a diagram illustrating a configuration of a linear address;

FIG. 8 is a diagram illustrating a second example of a method for setting a RAS box for one frame in the frame memory shown in FIG. 1;

9 is a diagram illustrating an example of a macroblock structure in the RAS box shown in FIG. 8;

10 is a flowchart for explaining a second embodiment of the address generation method according to the present invention;

FIG. 11 is a block diagram illustrating an apparatus in which the address generation method illustrated in FIGS. 5 and 10 is executed.

* Explanation of symbols for main parts of the drawings

100: frame memory 200: memory control unit

100-1 to 100-4: First to fourth frame storage areas

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 illustrates a structure of a frame memory adopted in the present invention, in which the frame memory 100 includes a restored image data write operation, a data read operation for motion compensation, and a data read operation for display to a memory controller (not shown). Synchronous-DRAM (SDRAM) controlled by a burst length of 8 will be taken as an example. The frame memory 100 has two memory banks, bank 1 and bank 2, bank 1 has first and second frame storage areas 100-1 and 100-2, and bank 2 stores third and fourth frames. There are regions 100-3 and 100-4. Here, the first to fourth frame storage areas 100-1, 100-2, 100-3, and 100-4 have a capacity for storing pixel data of one frame, respectively, and the first to fourth frame storage areas 100-1, 100-. 2,100-3 and 100-4 each have 1,024 row addresses, and have a column address of 256 words (where 1 word is 8 bits). One address stores eight Y pixels, two Cr pixels, two Cb pixels, and a total of 12 pixel data. Here, 1,024 row addresses mean the number of RAS boxes. The column address of 256 words is derived by 8 macroblocks per one RAS box * 32 pixels per macroblock (= 256 pixels).

The actual physical row address of the frame memory 100 is 000 _H to 3FF _H , 400 _H to 7FF _H for the first to fourth frame storage areas 100-1 to 100-4, respectively. , 800 _H to BFF _H and C00 _H to FFF _H. However, the first to fourth frame storage regions 100-1 to 100-4 exist independently, and the second and fourth frames corresponding to the macroblocks located at predetermined row addresses of the first frame storage region 100-1 are respectively provided. The macroblocks of the third frame storage areas 100-2 and 100-3 have the same row address. As such, the row address in the first to third frame storage areas 100-1 to 100-3 is referred to as a virtual row address. Then, based on the scheduling order of the frame memory 100 as shown in FIG. 2 during motion compensation, an address used to convert a virtual row address in a corresponding storage area in which a reference image is located into a physical row address is framed. It is called the frame offset address and is called RA [11:10]. That is, if RA [11:10] is '00', the first frame storage area 100-1, if '01', the second frame storage area 100-2, and if the '10', the third frame storage area 100 -3) and '11' indicate the fourth frame storage areas 100-4, respectively.

Here, the first and second frame storage areas 100-1 and 100-2 are used to store reconstructed I-picture or motion-compensated P-picture image data for use as a reference image for motion compensation and simultaneously for display. The three-frame storage area 100-3 is used to store the motion compensated B-picture image data, and the fourth frame storage area 100-4 stores the encoded bitstream input to the image decoder in units of predetermined bits. Used to save.

FIG. 2 shows a scheduling order of the frame memory 100 shown in FIG. 1, and the decoding order is I, P, B, B, P, B, B, P, B, B, P, B, B, I. , P, B, B, ... and the display order is I, B, B, P, B, B, P, B, B, P, B, B, P, I, B, B, ... For example, the display latency is 2 pictures. Here, the underlined portion indicates the picture currently being decoded, the arrow indicates the picture to be referred for motion compensation, and the storage area to which 'D' is added indicates that image data is being read out for display.

FIG. 3 illustrates a first example of a method for setting a RAS box for one frame in the frame memory 100 shown in FIG. 1. For example, when one frame includes 1,920 pixels * 1,088 pixels, 15 RAS boxes are illustrated. * 68 RAS boxes, divided into 1,020 RAS (Row Address Strobe) boxes. That is, the number of the RAS box is the row address (RA) of the frame memory 100. Here, one RAS box is composed of eight macroblocks * 1 macroblocks and a total of eight macroblocks MB0 to MB7. Each macroblock is divided into four blocks b0 to b3 when the luminance Y block is taken as an example.

FIG. 4 shows an example of a macroblock structure in the RAS box shown in FIG. 3, and includes four luminance (Y) blocks, one color difference (Cr) block, and one color difference (Cb) block. The luminance (Y) block consists of eight boxes (b0-0 to b0-7, b1-0 to b1-7, b2-0 to b2-7, and b3-0 to b3-7), respectively, and two color differences. The (Cr, Cb) block is composed of eight sub boxes (sb0-0 to sb0-7, sb1-0 to sb1-7, sb2-0 to sb2-7, sb3-0 to sb3-7), respectively. Then, 8 pixel data in 8 * 1 format for each box constituting the Y block, 2 pixel data in 2 * 1 format for each box constituting the Cr block, and 2 * 1 format for each box constituting the Cb block. There are two pixel data of.

5 is a flowchart illustrating a first embodiment of the address generation method according to the present invention, which is applied to the frame structure shown in FIGS. 3 and 4.

Referring to FIG. 5, in operation 101, a frame offset address, that is, RA [11:10] is determined based on a scheduling order of the frame memory 100 as illustrated in FIG. 2. . For example, as in step (b) of FIG. 2, motion compensation may be performed by referring to an I picture stored in the first frame storage area 100-1 with respect to a B picture stored in the second frame storage area 100-2. In case of execution, RA [11:10] becomes '00'.

In step 102 (S102), the start address of the current macroblock MB to be motion compensated, that is, the slice position and the macroblock position mb_position, and the motion vectors mv_v and mv_h are input.

In step 103, the scales of the variables input in step S102 are matched. Among the input variables, the slice position (slice_position) and the macroblock position (mb_position) each consist of 7 bits and have a macroblock scale, while the motion vector has a half pixel scale. The horizontal motion vector mv_h [12: 0] and the vertical motion vector mv_v [8: 0] have configurations as shown in FIGS. 6A and 6B, respectively. Therefore, in order to fit the motion vector on the macroblock scale, it is divided by 16, that is, mv_h [11: 5] and mv_v [7: 5] are taken and set as 'mv_h_mb' and 'mv_v_mb', respectively.

In step 104, a linear transformation of the horizontal and vertical coordinate systems is performed as in Equation 1 below to determine the predicted macroblock position (predict_MB_v, predict_MB_h).

[Equation 1]

slice_position ± mv_v_mb = predict_MB_v

mb_position ± mv_h_mb = predict_MB_h

Here, 'predict_MB_h' indicates a horizontal position of the predicted macroblock, and 'predict_MB_v' indicates a vertical position of the predicted macroblock.

In step 105, a linear address (LA) indicating a macroblock position within one frame is generated by the following equation (2), and RA [9: 0] and CA [7: 5].

[Equation 2]

LA = predict_MB_v * 120 + predict_MB_h

Here, since there are 120 macroblocks in the horizontal direction in one frame (1920 pixels * 1088 pixels), 'predict_MB_v' is multiplied by 120. Since 'predict_MB_v' is 7 bits, '120' is 7 bits, and 'predict_MB_h' is 7 bits, the calculation result of Equation 2 is 14 bits and has the configuration as shown in FIG. That is, in FIG. 7, LA [12: 3] becomes RA [9: 0] indicating the position of the RAS box in the storage area indicated by RA [11:10] determined in S101, and LA [2: 0] Becomes CA [7: 5] indicating the position of the macroblock in the RAS box.

In step 106 (S106), CA [4: 0] and PA [2: 0] are determined by the following equation (3).

[Equation 3]

MA = mv_h [4: 1] * mv_v [4: 1] ⇒ MA [7: 0]

That is, the lower four bits are taken from the horizontal and vertical motion vectors mv_h and mv_v shown in Figs. 6A and 6B, respectively, to determine the block position in the macroblock, the box position in the block, and the pixel position in the box. In MA [7: 0], MA [7: 6] becomes CA [4: 3], which indicates the block position in the macroblock, and MA [5: 3] represents CA [2: 0], which indicates the box position in the block. MA [2: 0] becomes PA [2: 0] indicating the pixel position in the box. Here, PA [2: 0] is used to determine the reference point (R.P) of the predicted macroblock.

In a step S107, it is determined whether the current macroblock inputted in S102 is the last macroblock in the picture to be motion compensated, and if the last macroblock is the end of the flowchart, the flow returns to S102.

In the address generation method according to the first embodiment, S101, S105 and S106 are performed sequentially or in parallel to reduce the address generation time.

FIG. 8 illustrates a second example of a method for setting a RAS box for one frame in the frame memory 100 shown in FIG. 1. For example, when one frame includes 1,920 pixels * 1,088 pixels, 30 RAS boxes are illustrated. * 34 RAS boxes, divided into 1,020 RAS (Row Address Strobe) boxes. That is, the number of the RAS box is the row address (RA) of the frame memory 100. Here, one RAS box is composed of four macroblocks * 2 macroblocks and a total of eight macroblocks MB0 to MB7. Each macroblock is divided into four blocks b0 to b3 when the luminance Y block is taken as an example.

FIG. 9 shows an example of a macroblock structure in the RAS box shown in FIG. 8, and is composed of four luminance (Y) blocks, one color difference (Cr) block, and one color difference (Cb) block. The luminance (Y) block consists of eight boxes (b0-0 to b0-7, b1-0 to b1-7, b2-0 to b2-7, and b3-0 to b3-7), respectively, and two color differences. The (Cr, Cb) block is composed of eight sub boxes (sb0-0 to sb0-7, sb1-0 to sb1-7, sb2-0 to sb2-7, sb3-0 to sb3-7), respectively. Then, 8 pixel data in 4 * 2 format is included in each box constituting the Y block, 2 pixel data in 2 * 1 format is used in each box constituting the Cr block, and 2 * 1 format in each box constituting the Cb block. There are two pixel data of.

10 is a flowchart illustrating a second embodiment of the address generation method according to the present invention, which is applied to the frame structure shown in FIGS. 8 and 9.

Referring to FIG. 10, in operation 201, a frame offset address, that is, RA [11:10] is determined based on a scheduling order of the frame memory 100 as shown in FIG. 2. . For example, as in step (b) of FIG. 2, motion compensation may be performed by referring to an I picture stored in the first frame storage area 100-1 with respect to a B picture stored in the second frame storage area 100-2. In case of execution, RA [11:10] becomes '00'.

In operation 202 (S202), a start address of a current macroblock MB to be motion compensated, that is, a slice position and a macroblock position mb_position, and a motion vector mv_v and mv_h are input.

In step S203, the scales of the variables input in step S202 are matched. Among the input variables, the slice position (slice_position) and the macroblock position (mb_position) each consist of 7 bits and have a macroblock scale, while the motion vector has a half pixel scale. The horizontal motion vector mv_h [12: 0] and the vertical motion vector mv_v [8: 0] have configurations as shown in FIGS. 6A and 6B, respectively. Therefore, in order to fit the motion vector on the macroblock scale, it is divided by 16, that is, mv_h [11: 5] and mv_v [7: 5] are taken and set as 'mv_h_mb' and 'mv_v_mb', respectively.

In operation 204 (S204), the linear transformation of the horizontal and vertical coordinate systems is performed as in Equation 1 to determine the predicted macroblock positions (predict_MB_v, predict_MB_h).

In step S205, RA [9: 0], which is the position (RAS box_position) of the RAS box in which the predicted macroblock is located, is determined by the following equation (4).

[Equation 4]

RAS box_position = ras_v * 30 + ras_h

Since the structure of the RAS box is four macroblocks * 2 macroblocks as shown in FIG. . Here, since 'ras_v' is 6 bits, '30' is 6 bits, and 'ras_h' is 5 bits, the calculation result in Equation 4 is 12 bits. Since the effective number of bits of the row address RA is 10 bits, the upper two bits are discarded and the remaining 10 bits are taken and left as RA [9: 0].

In step S206, CA [7: 5], which is the macroblock position MB_position in the corresponding RAS box, is determined by the following equation (5).

[Equation 5]

MB_position = ras_v_rem * 4 + ras_h_rem

Since the structure of the RAS box is 4 macroblocks * 2 macroblocks as shown in FIG. 8, 'ras_h_rem' and 'ras_v_rem' represent the remainder of 'predict_MB_h' divided by 4 and 'prediction_MB_v' divided by 2. . Here, since 'ras_v_rem' is 1 bit, '4' is 2 bits, and 'ras_h_rem' is 2 bits, the calculation result in Equation 5 is 3 bits.

In step 207 (S207), CA [4: 3], which is a block position blk_position in the macroblock, is determined by the following equation.

[Equation 6]

CA [4: 3] = (mv_v (4), mv_h (4))

Here, the motion vectors mv_v and mv_h are converted to the macroblock scale, and the upper bits mv_v (4) and mv_h (4) among the remaining bits, mv_v [4: 1] and mv_h [4: 1], are taken and (mv_v (4) ), mv_h (4)) is (0,0), b0, (1, 0), b1, (1,0), b2, and b3.

In step S208, CA [2: 0], which is a box position (box_position) in the block, is determined by the following equation.

[Equation 7]

box_position = mv_v [3: 2] * 2 + mv_h (3)

Since the box structure in each block is in 2 * 4 format as shown in Fig. 9, the remaining 1 bit of mv_h [4: 1], that is, mv_h (3), is taken, and the remaining 2 bits of mv_v [4: 1], that is, mv_v Take [3: 2], multiply it by two, and add it linearly. Here, 'mv_v [3: 2]' is 2 bits, '2' is 2 bits, and mv_h (3) is 1 bit, so the calculation result in Equation 7 is 4 bits. However, since the number of valid bits is three bits, the most significant one bit is discarded and the remaining three bits are taken to determine CA [2: 0].

In operation 209 (S209), PA [2: 0], which is a pixel position (pel_address) in the corresponding box, is determined by the following Equation (8).

[Equation 8]

pel_address = mv_v (1) * 4 + mv_h [2: 1]

Since the pixel structure in each box is in 4 * 2 format as shown in Fig. 9, the remaining two bits of mv_h [4: 1], that is, mv_h [2: 1], are taken, and the remaining 1 bit of mv_v [4: 1], i.e. Take mv_v (1), multiply it by 4, and add it linearly. Here, 'mv_v (1)' is 1 bit, '4' is 3 bits, and mv_h (3) is 2 bits, so the calculation result in Equation 8 is 3 bits.

In operation S210, it is determined whether the current macroblock inputted in S202 is the last macroblock in the picture to be motion compensated, and if the last macroblock is completed, the flowchart ends, and otherwise, returns to S202.

In the address generation method according to the second embodiment, S201, S205 to S209 can be performed sequentially or in parallel to reduce the address generation time.

RA [11: 0] and CA [7: 0] obtained by the first and second embodiments are required to read the macroblocks predicted from the corresponding storage areas of the frame memory 100 in box units. Address, and PA [2: 0] is the address needed to determine the reference point of the predicted macroblock.

FIG. 11 is a diagram illustrating an apparatus in which the address generation method illustrated in FIGS. 5 and 10 is performed, and is typically performed by the memory controller 200. That is, the memory controller 200 inputs a start address, a motion vector, and various parameters of a current macroblock in a picture to be motion compensated, and addresses an address for fetching a corresponding macroblock of a picture to be referred to in a box unit. Through the frame memory 100 through. In addition, various control signals for controlling write and read operations of the frame memory 100 are applied to the frame memory 100.

On the other hand, the above detailed description is intended to describe particular embodiments presented herein and is not intended to limit the present invention. Those skilled in the art may make various changes and modifications according to the structure of the RAS box and the structure of the macroblock block within the technical spirit of the present invention with reference to the above detailed description and drawings.

As described above, according to the present invention, one memory includes an area for storing reference image data in motion compensation, an area for storing decoded image data for display, and an area for storing an encoded bitstream input to the image decoder. In the frame memory implemented on the module, an address for reading the macroblock predicted by the start address and the motion vector of the current macroblock in units of boxes may be generated. In addition, the address of the RAS box position where the predicted macroblock is located, the macroblock position in the RAS box, the block position in the macroblock, the box position in the block, and the pixel position in the box are paralleled. By generating this, the time required for generating the entire address can be shortened.

Claims (4)

One frame consists of a plurality of RAS boxes, the RAS box has 8 macroblock * 1 macroblock formats, the macroblock has a 2 block * 2 block format for the luminance block, and the block has 1 box * 8 When the box has an 8-pixel * 1-pixel format, the box has a frame memory including first to fourth frame storage areas, a start address of a current macroblock of a picture to be motion compensated, horizontal and vertical motion vectors. And a memory controller for supplying an address and various control signals for reading a predicted macroblock by inputting various parameters to the frame memory. Adjusting the horizontal and vertical motion vectors to a macroblock scale; Generating a first row address indicating a storage area in which a picture to be referred to for motion compensation is located based on a scheduling order of the frame memory; Determining horizontal and vertical positions of the predicted macroblock using the horizontal and vertical motion vectors adjusted to the start address of the current macroblock and the macroblock scale; Generating a second row address indicating a RAS box position in a corresponding storage area and a first column address indicating a macroblock position in a corresponding RAS box by using the predicted horizontal and vertical positions of the macroblock; And A second column address indicating a block position in the macroblock, a third column address indicating a box position in the corresponding block, using the lower four bits of the horizontal and vertical motion vectors except for the half pixel flag; And generating a pixel address indicating a pixel position in the box. 2. The method of claim 1, wherein each address generating step is processed in parallel. One frame consists of a plurality of RAS boxes, the RAS box has a format of 4 macroblocks * 2 macroblocks, the macroblocks have a format of 2 blocks * 2 blocks for the luminance block, and the blocks are 2 boxes * When the box has a 4 box format and the box has a 4 pixel * 2 pixel format, the frame memory including the first to fourth frame storage areas, and the start address, horizontal and vertical motion of the current macroblock of the picture to be motion compensated. A motion compensation device comprising a memory controller for supplying an address and various control signals for reading a predicted macroblock by inputting a vector and various parameters to the frame memory, Adjusting the horizontal and vertical motion vectors to a macroblock scale; Generating a first row address indicating a storage area in which a picture to be referred to for motion compensation is located based on a scheduling order of the frame memory; Determining horizontal and vertical positions of the predicted macroblock using the horizontal and vertical motion vectors adjusted to the start address of the current macroblock and the macroblock scale; Generating a second row address representing a RAS box position in a corresponding storage area by using a quotient obtained by dividing the predicted macroblock's horizontal position and vertical position by 4 and 2, respectively; Generating a first column address indicating a macroblock position in a corresponding RAS box using the remainder obtained by dividing the predicted macroblock's horizontal and vertical positions by 4 and 2, respectively; And A second column address indicating a block position in the macroblock, a third column address indicating a box position in the block, using the lower 4 bits of the horizontal and vertical motion vectors except for the half pixel flag; And generating a pixel address indicating a pixel position in the box. 4. The method of claim 3, wherein each address generating step is processed in parallel.

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