JPH10304373A - Moving image decoding method and moving image decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain high speed decoding process and to reduce an occupancy rate of a memory data bus. SOLUTION: A predicted error from an inverse discrete cosine transformation(IDCT) 4 is supplied to a detection circuit 21 that detects a level below a threshold level, in which it is determined whether or not the predicted error is below a prescribed threshold level T. In the case that the predicted error is higher than the threshold level T, a reference image from a reference memory 8 is fed to a half pel arithmetic circuit 12, where interpolation processing is conducted and the result is added to the predicted error at an adder 5 and decoded image data are obtained. The decoded image data are outputted via a selector 23. In the case that the predicted error is equal to the threshold level T or below, the addition processing is skipped and the selector 23 selects an output of the half pel arithmetic circuit 12 and provides an output of the selected output. Thus, the addition processing is omitted and the decoding processing is accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a moving picture decoding method and a moving picture decoding apparatus for decoding a prediction coded signal.

[0002]

2. Description of the Related Art In recent years, moving picture coding systems such as MPEG2 have been used in digital broadcasting and package media. The image encoding method and the decoding method of MPEG2 are described in detail in the latest book, "Latest MPEG Textbook" (ASCII).

In the MPEG2 standard, image data is compressed by an orthogonal transformation process, a quantization process, and a variable length coding process. The orthogonal transform is for transforming an input sample value into an orthogonal component such as a spatial frequency component, and performs DCT (discrete cosine transform) processing or the like for each block of m × n pixels. Thereby, a spatial correlation component can be reduced. The components subjected to the orthogonal transformation are quantized to reduce the redundancy of the signal of the block.

Further, the data amount is further reduced by subjecting the quantized output to variable length coding such as Huffman coding. In Huffman coding, coding is performed based on the result calculated from the statistical code amount of a quantized output, and short bits are assigned to data with a high occurrence probability and long bits are assigned to data with a low occurrence probability. The entire data amount is reduced by the variable length coding to be assigned.

[0005] In MPEG2, in addition to intra-frame compression in which an image in a frame is subjected to DCT processing, inter-frame compression for reducing redundancy in the time axis direction using correlation between frames is also employed. The inter-frame compression uses the property that a general moving image is very similar in the preceding and succeeding frames, and calculates a difference between the preceding and succeeding frames to obtain a difference value (prediction error).
Is encoded, thereby further reducing the bit rate. In particular, motion-compensated inter-frame predictive coding that reduces the prediction error by estimating the motion of an image and calculating the inter-frame difference is effective. The motion vector data used for the motion compensation prediction is variable-length coded and multiplexed.

As described above, according to MPEG2, in addition to intra-frame encoding in which image data of a predetermined frame is directly subjected to DCT processing and encoding, a difference between image data of a predetermined frame and reference image data of frames before and after this frame is obtained. Predictive coding in which only data is subjected to DCT processing and coding is adopted. The prediction encoding method includes forward prediction encoding for obtaining a prediction error by performing motion compensation on temporally forward reference image data, and backward prediction for obtaining a prediction error by performing motion compensation on temporally backward reference image data. There are predictive coding and bidirectional predictive coding using either forward or backward or an average in both directions in consideration of coding efficiency.

The sampling clock differs between the luminance signal and the color difference signal processed by the MPEG encoder. For example, assuming that the sampling clock of the color difference signal has a frequency that is 1/4 of the sampling clock of the luminance signal, the size ratio between the luminance block and the color difference block is 1: 4. In this case, a macroblock is composed of 6 DCT blocks of 4 blocks of luminance and 1 block of each chrominance, and is used as an encoding unit. Motion vector detection is also performed on a macroblock basis. Assuming that the DCT block has a size of 8 × 8 pixels, the luminance signal and the chrominance signal are processed separately, so that the size of one macroblock is 16 × 16 pixels.

In detecting a motion vector, a target block (macro block) to be coded in the current frame
A predetermined search range centered on a block of the reference frame having the same relative positional relationship with respect to is set. Then, a block having a pattern most similar to the pattern of the target block in the current frame is searched for in the search range by matching calculation. That is, a matching calculation is performed in which the blocks are sequentially set within the search range while moving in units of 0.5 pixels, and the absolute value of the difference between each corresponding pixel between the block of interest and the block set in the search range is calculated. Then, the block having the smallest cumulative value is set as a reference macro block. A vector indicating the positional relationship between the reference macroblock and the block of interest is determined as a motion vector.

FIG. 14 is a block diagram showing a conventional moving picture decoding apparatus conforming to the MPEG2 standard. FIG. 15 is a flowchart for explaining the motion compensation prediction decoding process.

[0010] The coded data input via the input terminal 1 is supplied to a variable length decoding circuit (hereinafter referred to as VLD) 2. The input coded data is obtained by subjecting image data or a prediction error to DCT processing, quantizing, and then performing variable-length coding. The VLD 2 performs variable-length decoding on the input coded data, and returns the data before the variable-length coding processing on the coding side. The motion vector included in the output of the VLD 2 is supplied to a virtual address generation circuit 10, and the quantized output is supplied to an inverse quantization circuit (hereinafter, referred to as IQ) 3.

[0011] IQ3 dequantizes the output of VLD2 and expands it in the amplitude direction, and then an inverse DCT circuit (hereinafter referred to as IDCT).
4 is output. The IDCT 4 performs an inverse DCT process on the inversely quantized output and returns the data before the DCT process on the encoding side. IDC
The output of T4 is transferred to the memory data bus 6 via the adder 5, and further transferred to the image memory 7.

Now, assume that the intraframe encoded data is decoded. In this case, the output of the IDCT 4 is a restored image of the frame, and the output of the IDCT 4 is supplied to the image memory 7 via the adder 5 as it is.
The output of IDCT4 is pixel data in block units,
The image memory 7 stores pixel data for one frame in line units.

When the restored image data from the adder 5 is used as a reference image for motion-compensated prediction decoding, the restored image data is stored in the reference memory 8 of the image memory 7 and is not used as a reference image. Is stored in the restoration memory 9.

The writing and reading of the image memory 7 are controlled by a physical address generation circuit 11. The physical address generation circuit 11 generates a write address indicating a position on the image memory 7 corresponding to the position of the decoded macro block on the screen. In this case, the physical address generation circuit 11
Add an offset value determined by the memory usage.

On the other hand, the physical address generation circuit 11 provides a virtual address generation circuit for the read address of the reference image.
Generate based on 10 outputs. Virtual address generation circuit 10
Calculates the position on the screen of the reference macroblock referred to by the block to be decoded (hereinafter referred to as the screen address) based on the motion vector data from the VLD2. The physical address generation circuit 11 reads the reference memory 8 by converting the screen address into a position of the reference macro block on the reference memory 8 (hereinafter, referred to as a read address).

Here, it is assumed that the inter-frame coded data is decoded. In this case, IDCT
The output of 4 is a prediction error, and the original image can be restored by adding the prediction error and the reference image. In this case, the reference image is motion-compensated with the motion vector used at the time of encoding, and then added to the prediction error. Hereinafter, a series of processes from the reading of the reference image to the half-pel process and the process of adding the prediction error are referred to as motion compensation decoding.

The motion compensation decoding processing is performed based on the processing flow of FIG. First, in step S1 of FIG. 15, k indicating the number of a macroblock is initialized to 1. Next, in step S2, the virtual address generation circuit 10
Acquires the motion vector information and the encoding unnecessary information from the VLD2.

FIG. 16 and FIG. 17 are explanatory diagrams for explaining the encoding unnecessary information.

The coding unnecessary information is information indicating that coding processing for a predetermined macroblock can be omitted. For example, in the MPEG system, MBA (Macro
Block Address), MBT (Macro Block Type) and C
BP (Coded Block Pattern) and the like. This encoding unnecessary information is inserted into encoded data and transmitted. The decoding side determines whether or not the encoding process has been omitted based on the encoding unnecessary information.

The MBA indicates how many macroblocks are skipped before the macroblock to be decoded. The skip indicates that the motion vector matches the previous block for the B picture (bidirectionally coded frame) and the prediction error is 0, and the motion vector is 0 for the P picture (forward coded frame). And the prediction error is also 0.

[0021] The MBT indicates which of the prediction error and the motion information the macroblock to be decoded has.

The CBP indicates which of the plurality of DCT blocks in the macroblock has a prediction error. In CBP, a predetermined numerical value (hereinafter, DCT) is assigned to each DCT block in a macroblock.
A DCT block is specified by the sum of the numerical values in the DCT block. FIG. 16 shows the assignment of numerical values in the DCT block.

As shown in FIG. 16, four luminance blocks Y and one chrominance block Cb and Cr constituting one macroblock are respectively represented by 32,
16, 8, 4, 2, and 1 are assigned.

FIG. 17 shows the same notation as FIG.
The first to seventh macro blocks continuous in the horizontal direction are shown. In the DCT block shown by hatching in FIG. 17, all 8 × 8 prediction error values in the DCT block are 0.
Is a non-zero block. A non-zero block in each macroblock can be represented as shown in FIG. 17 by CBP which is a sum of numerical values in blocks in DCT. For example, the third and fourth macroblocks do not have non-zero blocks, indicating that the CBP is zero.

The dMV in FIG. 17 indicates a difference value of a motion vector from a previous macro block, and becomes 0 when the current macro block has the same motion as the previous macro block. The MBT in FIG. 17 indicates CBP, dMV ≠ 0 by a circle, dMV ≠ 0 by a triangle, and CB by a square.
P ≠ 0, CBP, dMV = 0 by X mark. For example, the fourth macro block is dMV, CBP
Is 0, the MBT is marked with a cross. That is, M
A macroblock with a BT mark x indicates that it has no information to be coded, and the coding process is skipped for the fourth macroblock in FIG.

The MBA indicates the number of macroblocks before which the coding process has not been skipped. For example, for the fifth macroblock,
This shows that the encoding process of the third macroblock two macroblocks before is not skipped. Therefore,
If the MBT of the previous macroblock is indicated by a mark x, the MBA takes a value of 2 or more.

Note that in MPEG, the MBA may indicate the horizontal position of a macroblock.

The virtual address generation circuit 10 calculates a screen address of a reference macro block referred to to obtain a prediction error on the encoding side based on the motion vector information and the encoding unnecessary information acquired from the VLD 2 ( Step S
3). This screen address is given to the physical address generation circuit 11, and the read address of the reference memory 8 is generated in step S4. In this way, the motion-compensated reference macroblock is read from the reference memory 8 in step S5 and supplied to the half-pel operation circuit 12.

On the coding side, the accuracy of the motion vector can be reduced to half of the pixel unit. When a value between pixels is specified as a reference image by a motion vector, it is necessary to interpolate the reference image data read from the reference memory 8 to obtain an intermediate value between adjacent pixels. Therefore, the half-pel operation circuit 12 performs an interpolation operation (half-pel operation) on the reference image data and outputs the result to the adder 5. In consideration of the interpolation, it is necessary to read out the reference image data from the reference memory 8 in a range wider by one pixel than one macroblock.

In step S6, the adder 5 restores the original image by adding the motion-compensated and interpolated reference image data output from the half-pel operation circuit 12 and the prediction error. The restored image is stored in the restored memory 9 of the image memory 7 via the memory data bus 6 (Step S7). In this case, the physical address generation circuit 11 receives the screen address of the macroblock being decoded from the virtual address generation circuit 10, generates a write address of the restoration memory 9 from this screen address, and supplies the write address to the restoration memory 9. I do.

Thereafter, decoding is performed in the same manner. In step S8, it is determined whether or not decoding of all macroblocks is completed. If the decoding process has not been completed, the macroblock number k is incremented in step S9, and the process returns to step S2.

When the motion compensation decoding process is completed, a display process after step S10 is performed. In step S10, the virtual address generation circuit 10 generates a screen address of the restored image read from the image memory 7, and the physical address generation circuit 11 converts the screen address into a read address (step S11). Thus, the readout of the restored image from the image memory 7 is performed in step S12.

The restored image data read from the image memory 7 is supplied to the display buffer 13, read out from the display buffer 13 in display order, and output via the output terminal 14. In step S13, it is determined whether the display process for the restored image has been completed. If the display process has not been completed, the process returns to step S10, and the process is repeated. Thus, the display of the restored image is performed.

By supplying the restored image data from the output terminal 14 to a display device (not shown), the restored image can be displayed. Also, since the motion compensation decoding processing is performed in units of macroblocks, while the display is performed in units of lines, the display buffer 13 may have a function of rearranging from block scan order to line scan order.

As described above, in the apparatus shown in FIG. 14, for the motion compensation decoding process, regardless of the presence or absence of the prediction error, the reading process of the reference macro block from the reference memory 8 and the prediction error The addition processing and the writing processing of the restored image to the restoration memory 9 or the reference memory 8 are performed, the number of accesses to the image memory 7 is extremely large, the processing time is long, and the bus occupancy of the memory data bus 6 is extremely high. There was a problem.

In particular, in a B picture that has been bidirectionally predicted according to the MPEG standard, it is necessary to read a reference macroblock twice for decoding one macroblock, and the decoding process takes a long time. And the bus occupancy is significantly higher.

Therefore, in order to reduce the memory capacity required for the circuit, the image memory 7 is replaced with another function such as an OSD.
(On Screen Display) There is a problem that even if an attempt is made to use the memory as a memory for use in, for example, the bus occupancy is high, the memory cannot be shared.

[0038]

As described above, in the conventional moving picture decoding apparatus described above, the decoding process takes a long time by reading the reference macroblock, and the bus occupancy of the picture memory is extremely high. There is a problem that it is difficult to use the memory for other functions.

The present invention has been made in view of such a problem, and can speed up the decoding process and reduce the bus occupancy of the image memory so that the image memory can be used for other functions. It is an object of the present invention to provide a moving picture decoding method and a moving picture decoding apparatus which can be used for both purposes and can reduce the circuit scale.

[0040]

According to a first aspect of the present invention, there is provided a moving picture decoding method comprising the steps of: performing motion compensation prediction coding using a prediction error between a current picture and a reference picture; A procedure for detecting a prediction error value indicating the magnitude of the prediction error of the encoded signal, and obtaining the reference image from the encoded signal, while skipping the motion compensation decoding process based on the magnitude of the prediction error. A decoding procedure for obtaining a decoded image using the reference image and the prediction error,
An output step of outputting the reference image as the decoded image when outputting the decoded image when the motion compensation decoding process is skipped in the decoding procedure. The image decoding apparatus receives a coded signal coded in a predetermined block unit by motion compensation prediction coding using a prediction error between a current image and a reference image, and obtains a decoded image by a predetermined decoding process. Storage means for holding the decoded image as a reference image, prediction error detection means for detecting the magnitude of the prediction error obtained in the course of the predetermined decoding processing and outputting a detection result, The addition processing of the reference image from the storage unit and the prediction error is skipped based on the motion compensation decoding process of the predetermined decoding process of the decoding unit. Kipping means, and output means for outputting the reference image held in the storage means as the decoded image when outputting the decoded image when the motion compensation decoding process is skipped by the skip means. is there.

According to the first aspect of the present invention, a prediction error value indicating the magnitude of the prediction error of the encoded signal is detected. In the decoding procedure, whether or not to perform the motion compensation decoding process is determined based on the magnitude of the prediction error. In the motion compensation decoding process, a decoded image is obtained by adding a reference image and a prediction error. By skipping the motion compensation decoding process, the processing time of the motion compensation decoding process is reduced. When the motion compensation decoding process is skipped, a reference image is obtained but a decoded image is not obtained. Therefore, in the output procedure, when the motion compensation decoding process is skipped, the reference image is output as a decoded image. Since the motion compensation decoding process is skipped based on the magnitude of the prediction error value, even when the reference image is output as a decoded image, the effect on the image quality of the decoded image is small.

According to the sixth aspect of the present invention, the encoded signal is decoded by the decoding means to obtain a decoded image. This decoded image is stored in the storage unit as a reference image. The decoded image is restored by adding the reference image to the prediction error by the motion compensation decoding process of the predetermined decoding process. The prediction error detection means detects the magnitude of the prediction error obtained in the course of the decoding process. The skip unit skips the motion compensation decoding process based on the detection result of the magnitude of the prediction error. Thereby, the time required for the decoding process is reduced. The output unit outputs the reference image stored in the storage unit as a decoded image when the motion compensation decoding process is skipped.

[0043]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a moving picture decoding apparatus according to the present invention. In FIG. 1, the same components as those in FIG. 14 are denoted by the same reference numerals.

The image quality evaluation value of the restored image is the ratio between the original signal and the restored image signal. N. R (Signal to Nois
e Ratio). When the sum of the prediction error values of the respective image data in the macroblock is zero or near zero, or the total number of image data in which the prediction error value is zero or near zero is zero or near zero. In such a case, even if the reference image is output as a restored image without adding the prediction error to the reference macroblock, the S.I. N. The effect on R is extremely small. For this reason, in this embodiment, the decoding process is speeded up by omitting the process of adding the reference image and the prediction error.

In FIG. 1, coded data is input to an input terminal 1. This coded data is created by, for example, DCT processing, quantization processing, and variable-length coding processing. In addition to intra-frame coding processing, unidirectional prediction using a reference image of a forward or backward frame is performed. An encoding process and a bidirectional prediction encoding process using a reference image of a bidirectional frame are performed. The encoded data is multiplexed with the information of the motion vector used in the predictive encoding and the unnecessary information for encoding, which are variable-length encoded.

The encoded data input through the input terminal 1 is supplied to the VLD 2. The VLD 2 performs variable-length decoding on the input coded data, and returns the data before the variable-length coding processing on the coding side. As a result, a quantized output, data of a motion vector, and unnecessary coding information are obtained from the VLD 2. VLD2 provides the quantized output to IQ3,
The motion vector and the encoding unnecessary information are supplied to the virtual address generation circuit 10.

IQ3 dequantizes the output of VLD2 and expands it in the amplitude direction, and then outputs it to IDCT4. IDCT
4 is an inverse DCT processing of the inversely quantized output and a DCT on the encoding side.
Return to the data before processing. The output of the IDCT 4 is supplied to the adder 5 via the below-threshold detection circuit 21. The below-threshold detecting circuit 21 detects whether or not the prediction error is below a predetermined threshold T.

When the output of the IDCT 4 is based on the intra-frame coded data, the adder 5 outputs the IDCT 4
Is output to the switch 22 as it is, and when the output of the IDCT 4 is a prediction error based on the inter-frame coded data, a half-pel operation circuit to be described later is added to the input prediction error.
The twelve outputs are added and output to the switch 22. Switch 22
Supplies the output of the adder 5 to the selector 23 by selecting the terminal a, and supplies the output of the adder 5 to the reference memory 8 via the memory data bus 6 by selecting the terminal b. I have.

The reference memory 8 is supplied with restored image data from the switch 22 via the memory data bus 6, and stores the restored image data as reference image data. The writing and reading of the reference memory 8 are controlled by the physical address generation circuit 11. Physical address generation circuit
Reference numeral 11 designates a block position of the reference memory 8 based on the output of the virtual address generation circuit 10 so that the motion-compensated reference image data is read in macroblock units and output to the half-pel operation circuit 12. ing.

The virtual address generation circuit 10 receives the motion vector information from the VLD 2 and calculates the position on the screen of the reference macroblock referred to by the macroblock to be decoded, based on the motion vector information. The virtual address generation circuit 10 outputs the obtained screen address to the physical address generation circuit 11.

The half-pel operation circuit 12 interpolates the motion-compensated reference image data from the reference memory 8 by half-pel operation and outputs the result to the adder 5. Adder 5 has ID
When the restored image data of the prediction error is input from CT4, the original image is restored and output by reading out and adding the reference image data from the half-pel operation circuit 12.

In this embodiment, the output of the half-pel operation circuit 12 is also given to the selector 23. The selector 23 is controlled by the threshold detection circuit 21. That is, the selector 23 selects the output of the half-pel operation circuit 12 when the prediction error is equal to or smaller than the threshold T and outputs the output to the display buffer 19, and when the prediction error is larger than the threshold T, adds the output from the switch 22. The output of the device 5 is selected and output to the display buffer 19. The display buffer 19 holds the restored image data until the display timing and outputs the restored image data via the output terminal 14 in the display order.

Next, the operation of the embodiment configured as described above will be described with reference to the flowchart of FIG. FIG. 2 shows a processing flow of the motion compensation decoding processing.

Variable length decoding processing, inverse quantization processing and inverse DC processing for the encoded data input through the input terminal 1
The T processing is the same as the conventional one. By performing variable-length decoding on the encoded data, data before the variable-length encoding on the encoding side is obtained. The VLD 2 outputs the quantized output obtained by the variable length decoding process to the IQ 3, and outputs the motion vector and the coding unnecessary information to the virtual address generation circuit 10.

The quantized output is inversely quantized by IQ3, and the inverse quantized output is subjected to inverse DCT processing by IDCT4. As a result, data before DCT processing on the encoding side is obtained.

If the encoded data has been intra-frame encoded, the IDCT for the encoded data
The output of No. 4 is a restored image. In this case, IDCT4
Is supplied to the adder 5 through the below-threshold detection circuit 21. Further, the output of the memory data bus 6
Is supplied to the reference memory 8 via the.

The physical address generation circuit 11 gives a write address to the reference memory 8 and stores the restored image data transferred via the memory data bus 6. Thus, the reference image data is stored in the reference memory 8.

On the other hand, if the encoded data is inter-frame encoded, the output of the IDCT 4 is a prediction error. When the prediction error value t is obtained in step S21 of FIG. 2, next, a reference image is obtained (step S21).
twenty two).

That is, when the coded data obtained by the inter-frame coding is input via the input terminal 1, the VLD2
, The motion vector information is supplied to the virtual address generation circuit 10. The virtual address generation circuit 10 calculates the screen address of the reference macro block based on the motion vector information. The virtual address generation circuit 10 outputs the generated screen address to the physical address generation circuit 11.

The physical address generation circuit 11 converts the screen address given from the virtual address generation circuit 10 into a read address and sequentially outputs the read address to the reference memory 8. As a result, the motion-compensated reference macroblock is read from the reference memory 8 and transferred to the half-pel operation circuit 12 via the memory data bus 6.

Next, in step S23, the prediction error t
Is less than or equal to the threshold value T. The prediction error from the IDCT 4 is supplied to the below-threshold detection circuit 21, and the prediction error t and the threshold T are compared. If the prediction error t is larger than the threshold T, the process proceeds to step S24,
The prediction error is added.

The adder 5 restores the original image by adding the prediction error from the below-threshold detection circuit 21 and the reference image from the half-pel operation circuit 12. The restored image data from the adder 5 is supplied to the selector 23 via the terminal a of the switch 22. In this case, the selector 23 selects the terminal a under the control of the below threshold value detection circuit 21, and the restored image data from the adder 5 is supplied from the selector 23 to the display buffer 19. Thus, the restored image data is read out from the display buffer 19 in the display order in step S25, and
Is output via.

On the other hand, when the prediction error t is equal to or smaller than the threshold value T, the processing shifts from step S23 to step S25. That is, in this case, the addition processing of the prediction error is not performed, and the reference image data from the half-pel operation circuit 12 is provided to the display buffer 19 via the selector 23. In this case, the reference image data is provided to the display buffer 19 as restored image data. In step S25, the restored image data is read out in the display order and output to the output terminal 14. As described above, in this case, the S.P.M. of the image based on the reference image data and the S.M. N. R has substantially the same value.

In step S26, it is determined whether the motion compensation decoding process has been completed. If the motion compensation decoding process has not been completed, the processes of steps S21 to S25 are repeated. Thus, all the restored image data of one screen is output from the output terminal 14.

As described above, in the present embodiment, when the prediction error is smaller than the predetermined threshold, the motion-compensated reference image data is used as the restored image data without adding the prediction error. The decoding process can be sped up by omitting the addition process.

FIG. 3 is a flowchart showing a moving picture decoding method according to another embodiment of the present invention. In FIG. 3, the same steps as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

In the present embodiment, the comparison between the prediction error value and the threshold value in the motion compensation decoding process is performed on a macroblock basis. Other decoding processes are the same as in the embodiment of FIG. Further, the present embodiment can be realized by the same configuration as the moving picture decoding device in the embodiment of FIG.

Step S31 in FIG. 3 is a process for initializing a variable S used as the sum of the prediction error values t in the macroblock. Step S32 is processing to add the prediction error value t to the variable S. In step S33, steps S21 and S32 are performed for all prediction error values of one macroblock.
It is determined whether or not the process has ended, and if not, the process returns to step S21.

Step S34 is a process for judging whether or not the sum S of the prediction error values t in the macroblock is equal to or smaller than a predetermined threshold value T1. If the sum S is greater than the threshold T1, the process proceeds to step S24. If the sum S is less than the threshold T1, the process of step S24 is skipped and the process proceeds to step S25.

In the motion compensation decoding process of FIG. 3, the below-threshold detection circuit 21 of FIG. 1 has one register (or memory) for storing a prediction error value, and sequentially stores the prediction error values of one macroblock. This can be realized by adding the sum S to obtain the sum S and comparing the obtained sum S with the threshold value T1.

In the embodiment configured as described above, only the operation of the motion compensation decoding process is different from the embodiment of FIG.

First, in step S31 of FIG. 3, the variable S of the sum is initialized to zero. Next, in step S21, a prediction error value t is obtained. The inter-frame coded data input via the input terminal 1 of FIG. 1 is subjected to variable length decoding by the VLD 2, inverse quantization by the IQ 3, inverse DCT by the IDCT 4, and returns to a prediction error.

The prediction error is sequentially applied to the detection circuit 21 below the threshold value in pixel units. The below-threshold detection circuit 21 determines in step S
At step 32, steps S33 and S21, the prediction error values are sequentially added to obtain the sum S of the prediction error values in the macroblock.

In the next step S22, a reference image is obtained. The virtual address generation circuit 10 obtains a screen address based on the motion vector, and the physical address generation circuit 11 converts the screen address into a read address of the reference memory 8 and reads from the reference memory 8. The reference image stored in the reference memory 8 is read out after being blocked at a blocking position based on the motion vector and read out by the half-pel operation circuit 12.
Is subjected to half-pel operation processing.

In step S34, the sum S of the prediction error values in the macroblock is compared with the threshold value T1. If the sum S is larger than the threshold value T1, the adder 5 adds the prediction error and the half-pel operation circuit 12 in the next step S24. The selector 23 selects the terminal a of the switch 22 when the sum S is larger than the threshold T1,
The output of the adder 5 is supplied from the selector 23 to the display buffer 19, and is output to the output terminal 14 in step S25.

On the other hand, when the total sum S is equal to or smaller than the threshold value T1, the addition processing in step S24 is skipped, and the processing shifts to step S25. That is, in this case, the selector
Reference numeral 23 selects the output of the half-pel operation circuit 12, and the motion-compensated reference image is directly supplied from the selector 23 to the display buffer 19 without being subjected to the addition processing with the prediction error, and is output from the output terminal 14. Is done.

As described above, also in the present embodiment, the same effects as in the embodiment of FIG. 1 can be obtained.

FIG. 4 is a flowchart showing another embodiment of the present invention. 4, the same steps as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

This embodiment is different from the embodiment of FIG. 3 only in the method of comparing the prediction error value and the threshold value in the motion compensation decoding process.

Step S41 in FIG. 4 is a process for initializing a variable K used as a total sum of the number of prediction errors equal to or smaller than a predetermined threshold T in a macroblock. In step S42, it is determined whether or not the prediction error value t is equal to or less than the threshold value T.
If the prediction error value t is equal to or smaller than the threshold value T, step S
The process moves to step 43, and if not, the process moves to step S33. Step S43 is processing for obtaining the total number K, which is the number of times that the prediction error value t is equal to or less than the threshold value T. Step S
It is determined by 33 whether or not the processing of steps S21 to S43 has been performed for all the prediction errors of one macroblock.

In step S44, the total number K in the macroblock
Is a process for determining whether or not is less than or equal to a predetermined threshold value P. If the sum S is greater than the threshold value P, the process proceeds to step S24. If the total number K is equal to or less than the threshold value P, the process of step S24 is skipped and the process proceeds to step S25.

It is apparent that the motion compensation decoding process of FIG. 4 can be realized by the same configuration as that of FIG.

In the embodiment configured as described above, only the operation of the motion compensation decoding process is different from the embodiment of FIG.

In step S41 of FIG. 4, a variable K of the sum is initialized to zero. Next, in step S21, a prediction error value t is obtained for each pixel. In step S42, it is determined whether or not the obtained prediction error value t is equal to or smaller than the threshold T. For pixels whose prediction error value t is equal to or smaller than the threshold value T, the total number K is incremented in step S43, and for pixels not so, the process of step S43 is skipped. In this way, the total number K of pixels for which the prediction error value t is equal to or smaller than the threshold value T is obtained through steps S21 to S33.

In step S22, a reference image is obtained. In step S44, it is determined whether or not the total number K is equal to or less than a predetermined threshold value P. If the total number K is larger than the threshold value P,
In step S24, the reference image and the prediction error are added. If the total number K is equal to or less than the threshold value P, the reference image is added to the reference image without adding the prediction error and the prediction error.
At 25, it is output as restored image data. As a result, the addition processing of the reference image and the prediction error can be omitted and the decoding processing speed can be increased without lowering the image quality of the restored image.

As described above, also in this embodiment, FIG.
The same effect as that of the embodiment can be obtained.

FIG. 5 is a block diagram showing a moving picture decoding apparatus according to another embodiment of the present invention. In FIG.
The same components as those described above are denoted by the same reference numerals and description thereof is omitted.

A general display buffer has only a capacity to hold image data for a relatively short time. Therefore, when the restored image data obtained by the motion compensation decoding process is displayed some time after the output, such as when only the I and P pictures are processed, the embodiment of FIG. Although there is no problem, there is a long time lag between the motion compensation decoding process and the display process, for example, one frame time.
When (time difference) exists or when a long time lag is set, the embodiment of FIG. 1 cannot be adopted. The present embodiment is applied to an example in which a restoration memory for holding restored image data by the motion compensation decoding process until the display process is provided.

It is clear that the above-described time lag can be applied by adding the same capacity as the restoration memory to the display buffer 19.

The below-threshold detection circuit 21 detects whether or not the prediction error value t is below the threshold T, and outputs the detection result to the skip information holding circuit 31. In addition, the threshold detection circuit 21
4 may detect whether or not the sum S of the prediction error values t in the macroblock is equal to or smaller than the threshold value T1, and output the detection result to the skip information holding circuit 31, as shown in FIG.
, The total number K of pixels in which the prediction error value t is equal to or smaller than the threshold value T is determined, whether or not the total number K is equal to or smaller than the threshold value P, and the detection result is skipped.
May be output.

The output of the virtual address generation circuit 10 is also supplied to the skip information holding circuit 31. When it is detected that the prediction error value t is equal to or smaller than the threshold value T, the skip information holding circuit 31
Is held as the skip address. Further, the skip information holding circuit 31 holds other necessary information, for example, information on the number k of the macroblock to be decoded and the presence / absence of half-pel processing.

[0092] The skip information holding circuit 31 controls the physical address generation circuit 33 based on the held skip address. The physical address generation circuit 33 is a virtual address generation circuit
The screen address given from 10 is converted into the write and read addresses of the image memory 7, and the skip address is controlled by the skip information holding circuit 31.
Read address for reference memory 8 and restoration memory 9
Is not generated. Thereby, the addition process of the adder 5 when the prediction error value t is equal to or smaller than the threshold value T is omitted, and the output of the adder 5 when the prediction error value t is equal to or smaller than the threshold value T is written to the restoration memory 9. It is not inserted.

When reading from the image memory 7 for display, the decoded image read determination circuit 32 corresponds to the skip address held in the skip information holding circuit 31 by the screen address from the virtual address generation circuit 10. In this case, the skip address holding circuit 31 is added to the physical address generation circuit 33.
An instruction is given to use the skip address from. It should be noted that the function of the skip information holding circuit 31 may be only the holding function, and the control function of the physical address generation circuit 33 may be included in the decoded image readout determination circuit 32 or may be included in the physical address generation circuit 33 itself. Yes, the present invention includes this.

The half-pel operation circuit 34 has the same configuration as that of the half-pel operation circuit 12, and it is necessary to perform half-pel processing on the read image data when reading from the reference memory 8 is performed at the time of reading for display. In this case, the read image data is subjected to half-pel processing and output to the display buffer 19. The half-pel operation circuit 34 gives the image data read from the restoration memory 9 to the display buffer 19 as it is.

The skip information holding circuit 31 does not always need to hold the skip address in pixel units.
What is necessary is just to hold the information necessary for generating the address for reading the decoded image.

For example, as an image memory, columns
An access may be performed by supplying an address and a row (row) address, and a DRAM having a page structure having a plurality of column addresses for one row address may be used. FIG. 6 is an explanatory diagram for explaining such writing in the image memory. FIG. 6A shows a page structure of a storage area, and FIG. 6B shows a macro block on a screen.

As shown in FIG. 6A, the image memory has a plurality of pages, and the division of each page is indicated by a broken line. A page can be specified by a row (page) address, and each column of each page can be specified by a column address. On the other hand, FIG.
As shown in (b), one screen is divided into a plurality of macroblocks, and the division of each macroblock is indicated by a broken line. The number of macroblocks in the horizontal and vertical directions shown in FIG. 6B is different from the actual number.

Now, the macroblock being decoded is shown in FIG.
It is assumed that this is the part shown by the solid line in (b), and the reference macroblock used in the decoding processing of this macroblock is written in the part shown by the thick frame in FIG. In this case, the skip information holding circuit 31 should hold the head address of the portion where the reference macroblock is stored, that is, the address (C, R) of the set of the column address C and the row address R. Thus, it is clear that the read address of the decoded image can be generated.

That is, in the case where the below-threshold detection circuit 21 obtains a detection result in macroblock units, and when the reference macroblock is stored in one page, the skip information holding circuit 31 stores the skip address for each pixel. It is not necessary to hold, and only the skip address of the first pixel of the reference macroblock (for example, the upper left pixel on the screen) need be held.

Next, the operation of the embodiment configured as described above will be described with reference to the flowcharts of FIGS. FIGS. 7 and 8 show that the processes are linked by a circled number 1.

In the present embodiment, decoding processing for an I picture (intra-coded frame) and a P picture is the same as in the embodiment of FIG. The restored image data of the I and P pictures obtained from the adder 5 is provided to a reference memory 8 via a memory data bus 6 and stored therein in order to obtain a reference image.

Here, it is assumed that the encoded data of the B picture is decoded. The following description is made on the assumption that the below-threshold detection circuit 21 outputs a detection result indicating whether or not the sum S of the prediction error values in the macroblock is equal to or less than the threshold T1. After the block number k is initialized to 1 in step S51 of FIG. 7, motion information and coding unnecessary information are acquired in step S52. That is, the VLD 2 performs variable length decoding of the encoded data to obtain a quantized output, and also obtains a motion vector and encoding unnecessary information.

The quantized output is returned to the original pixel data by IQ3 and IDCT4. In this case, IDCT
The output of No. 4 is a prediction error (step S53). The prediction error is given to the below threshold detection circuit 21. Below threshold detection circuit
21 obtains the sum S of the prediction error values in step S54.

On the other hand, the motion vector and the coding unnecessary information from the VLD 2 are supplied to the virtual address generation circuit 10.
In step S55, the virtual address generation circuit 10 obtains the screen address of the reference macroblock referred to by the kth macroblock from the motion vector information. This screen address is supplied to the physical address generation circuit 33 and also to the skip information holding circuit 31. The physical address generation circuit 33 converts the screen address into a read address (mRa, mCa) of the reference image in step S56.

In the next step S57, a threshold value or less detection circuit
According to 21, it is determined whether or not the sum S is less than or equal to the threshold value T1. The below-threshold detection circuit 21 outputs a detection result of whether or not the sum S is below the threshold T1 to the skip information holding circuit 31. When it is indicated that the sum S is equal to or smaller than the threshold value T1, the skip information holding circuit 31 stores the number k of the macroblock to be skipped in step S62, and refers to the k-th macroblock in step S63. The read address of the reference macro block is stored as a skip address, and the process proceeds to step S61. That is, in this case, the physical address generation circuit 33 does not output the write and read addresses, and the motion compensation decoding processing and the writing processing of the decoded image in steps S58 to S60 are not performed.

When the sum S is larger than the threshold T1,
Normal motion compensation decoding processing and decoding processing of a decoded image are performed. That is, in step S58, the physical address generation circuit 33 gives the read address to the reference memory 8, reads the motion-compensated reference macro block, and supplies it to the half-pel operation circuit 12. After the reference macroblock is subjected to the interpolation processing in the half-pel operation circuit 12, in step S59, it is added to the prediction error by the adder 5 to return to the original restored image. The restored image data is supplied from the adder 5 via the memory data bus 6 to the restored memory 9 and stored therein.

In step S61, it is determined whether or not the motion compensation decoding processing has been completed. If the motion compensation decoding process has not been completed for all the screens, the process shifts to step S64 to increment the block number k, and repeats the process from step S52. When the motion compensation decoding process is completed for all the macroblocks on the screen, step S
The process shifts from 61 to the display process of step S65 and thereafter.

As described above, the sum S of the prediction error values is equal to the threshold value T.
For macroblocks of 1 or less, the motion compensation decoding processing and the writing processing of the restored image data are omitted, and the processing speed is increased, and the occupancy of the memory data bus 6 is significantly reduced.

Next, at the display timing, the display processing from step S65 is performed. In step S65, the virtual address generation circuit 10 generates a screen address for reading out the restored image data. This screen address is supplied to the physical address generation circuit 33 and the decoded image read determination circuit 32.

In the next step S66, the decoded image read determination circuit 32 determines whether the restored image data specified by the screen address is the data in the skipped k-th macroblock section stored in the skip information holding circuit 31. It is determined whether or not there is. If the restored image data to be read is I, P
K based on picture or skipped
If the data is not in the
In step S69, the physical address generation circuit 33 converts the screen address into a read address (dRa, dCa). The read address from the physical address generation circuit 33 is supplied to the reference memory 8 or the restoration memory 9, and the restoration image data is read (step S70).

The skipped restored image data is skipped k
If the data is in the macroblock partition of the
The process proceeds from step S66 to step S67. The decoded image read determination circuit 32 controls the physical address generation circuit 33 to read the skip address corresponding to the k-th macro block stored in the skip information storage circuit 31 (step S67). Here, the read address is
This corresponds to the address on the reference memory 8 where the reference macroblock referred to by the k-th macroblock during the motion compensation decoding processing in step S58. In step S68, the physical address generation circuit 33 converts the skip address (mRa, mCa) into the read address (dRa, dC
a).

In the next step S70, the physical address generation circuit 33 reads out image data by designating a read address of the reference memory 8. That is, in this case,
A reference image that has not been subjected to motion compensation decoding is read as restored image data. Even in this case, since the total sum S of the prediction error values is equal to or less than the threshold value T1, the influence on the image quality of the restored image is extremely small. In step S71, it is determined whether or not all the display processes for one screen have been completed. If not, the processes from step S65 are repeated.

As described above, in the present embodiment, the motion compensation decoding process and the writing process of the restored image data are skipped for the B picture based on the detection result of the below-threshold detection circuit 21. The speed can be increased and the occupancy of the memory data bus can be significantly reduced. As a result, the image memory can be used for other functions, and the circuit scale can be reduced.

It is apparent that the below-threshold detection circuit 21 may compare the prediction error with a predetermined threshold not only in pixel units and macroblock units but also in other units. Further, in the present embodiment, an example has been described in which processing is skipped only for B pictures in consideration of image quality. However, it is apparent that processing may be skipped for P pictures. Further, in the present embodiment, the image memory is described as being divided into the reference memory and the restoration memory. However, the present invention can be applied to a case where one memory having these two functions is used. it is obvious.

Further, in the present embodiment, description has been made on the assumption that the skip information holding circuit 31 holds a memory address. However, a screen address may be held instead of a memory address. It is clear that the same effect can be obtained.

FIG. 9 is a block diagram showing another embodiment of the present invention. In FIG. 9, the same components as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, a skip information holding circuit for holding a skip address and the like is also used as a restoration memory. As described above, the image data for which the motion compensation decoding processing and the writing processing of the restored image data are skipped are not written in the restoration memory. Therefore, an unused portion occurs in the restoration memory. In this embodiment, information such as a skip address is stored in the unused portion.

That is, the screen address from the virtual address generation circuit 10 is supplied to the physical address generation circuit 33 and the decoded image read determination circuit 32, and is also supplied to the restoration memory 35 via the memory data bus 6. It has become.
The restoration memory 35 holds the restoration image data for the B picture from the adder 5 and also stores the threshold value or less detection circuit 21.
Accordingly, when it is indicated that the prediction error value t is equal to or less than the threshold value T, the read address from the physical address generation circuit 33 is held as a skip address.

Also in the embodiment configured as described above, the prediction error value t is set to the threshold T
If the following is detected, the reference image is not read from the reference memory 8 and the motion compensation decoding process and the process of writing the restored image data to the restoration memory 35 are not performed.

The read address indicating the skipped image data is stored in the restoration memory 35 from the physical address generation circuit 33 via the memory data bus 6. The restoring memory 35 stores not only the skip address but also the number k of the macroblock to be skipped and other necessary information, as in the embodiment of FIG.

At the display timing, the decoded image read determination circuit 32 determines whether or not the skip address corresponding to the screen address from the virtual address generation circuit 10 is stored in the restoration memory 35, and the physical address generation circuit Control 33. Accordingly, the physical address generation circuit 33 converts the skip address into a read address for the image data for which the motion compensation decoding process and the write process of the restored image data have been skipped, and thereby converts the corresponding image data from the reference memory 8. Read.

The decoded image read judgment circuit 32 needs to hold some kind of judgment information in order to judge whether or not the skip address has been written. For example, there is a macro block number.

The other operations are the same as those of the embodiment shown in FIG.

As described above, the present embodiment has the advantages that the same effects as those of the embodiment of FIG. 5 can be obtained and that the skip information holding circuit 31 can be omitted.

By writing the skip address and the mark in which the skip address is written in the restoration memory 35 at the same time, the data read from the restoration memory 35 is a decoded image or a skip address. This can be determined by the decoded image reading determination circuit 32 without holding the determination information, and whether or not the reference image is read as the decoded image can be controlled.

FIG. 10 is a block diagram showing another embodiment of the present invention. 10, the same components as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted.

This embodiment is an example in which the threshold value T is set to 0 in the embodiment of FIG. 5, and the skip of the motion compensation decoding process and the writing process of the restored image data is controlled by the presence or absence of a prediction error. It was made.

This embodiment is different from the embodiment shown in FIG. 5 in that the below-threshold detection circuit 21 is omitted and a prediction error 0 detection circuit 41 is provided. The image memory 42 is a single memory having the same function as the image memory 7.

In the present embodiment, the prediction error data from IDCT 4 is supplied to adder 5. Also, VL
The encoding unnecessary information from D2 is given to the prediction error 0 detection circuit 41. The presence / absence of the prediction error can be detected by the coding unnecessary information. The prediction error 0 detection circuit 41 detects the presence or absence of a prediction error from the encoding unnecessary information, and outputs the detection result to the skip information holding circuit 31.

When there is no prediction error, the skip information holding circuit 31 holds the read address from the physical address generation circuit 33 as a skip address.

Next, the operation of the embodiment configured as described above will be described with reference to the flowcharts of FIGS. 7 and 8 in FIGS.
The same steps as those described above are denoted by the same reference numerals and description thereof is omitted. FIG. 11 and FIG. 12 show that the processes are linked by a circle numeral 1.

The processing flow of this embodiment is different from the processing flow of FIG. 7 in that steps S53 and S54 are omitted and step S75 is provided instead of step S57. In step S75, the presence or absence of a prediction error is determined. If there is a prediction error, the process proceeds to step S58. If there is no prediction error, the process proceeds to step S62.

That is, when the VLD 2 acquires the motion information and the encoding unnecessary information in step S52, a screen address is generated in step S55.

In step S75, the prediction error 0 detection circuit 41
Is used to determine the presence or absence of a prediction error. If the encoding unnecessary information indicates that there is a prediction error, motion compensation decoding processing and writing processing of restored image data are performed in steps S58 to S60. On the other hand, if the encoding unnecessary information indicates that there is no prediction error, the macro block number k is stored in step S62, and the skip address is stored in step S63. Then, the process proceeds to step S61.

The other operations are the same as those of the embodiment shown in FIG.

As described above, in the present embodiment, since the presence / absence of a prediction error can be detected based on the encoding unnecessary information, calculation for calculating the sum of the prediction error values is unnecessary, and circuits such as a counter are required. There is no need to incorporate it. For this reason, the method of detecting whether or not to skip can be simplified as compared with the embodiment of FIG. 5, and the circuit scale can be reduced. In addition, by limiting the skip condition to no prediction error, image quality degradation (SNR degradation) from the conventional example is reduced.
Not at all.

FIG. 13 is a block diagram showing a moving picture decoding apparatus according to another embodiment of the present invention. 13, the same components as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted.

This embodiment is an example in which the half-pel operation circuit 34 and the half-pel operation circuit 12 are shared. This embodiment is different from the embodiment of FIG. 10 in that the half-pel operation circuit 34 is omitted and a selector 45 is provided.

The selector 45 receives the output of the half-pel operation circuit 12 and the restored image data read from the image memory 42 via the memory data bus 6.
The selector 45 is controlled by the decoded image reading determination circuit 32, and when reading from the image memory 42 for display processing, the half-pel operation circuit is used for the image data for which the motion compensation decoding processing and the writing processing of the restored image data are skipped. Twelve outputs are selected, and for image data not skipped, the output of the memory data bus 6 is selected and output to the display buffer 19.

In the embodiment configured as described above, when the image data subjected to the motion compensation decoding processing and the writing processing of the restored image data is read out from the image memory 42 during the display processing, this image data is read. Are supplied from the memory data bus 6 to the display buffer 19 via the selector 45.

On the other hand, the decoded image read determination circuit 32 causes the selector 45 to select the output of the half-pel operation circuit 12 when instructing the physical address generation circuit 33 to use the skip address during the display processing. Image memory 42
Then, the image data skipped in the motion compensation decoding process and the writing process of the restored image data are read and supplied to the half-pel operation circuit 12 via the memory data bus 6.

The half-pel operation circuit 12 performs a half-pel operation, interpolates the image data, and outputs it to the selector 45. The selector 45 is controlled by the decoded image read determination circuit 32 to select the output of the half-pel operation circuit 12, and the image data subjected to the interpolation processing is supplied from the selector 45 to the display buffer 19.

The other operation is the same as that of the embodiment shown in FIG.

As described above, this embodiment has the same effects as the embodiment of FIG. 10 and has the advantage that the half-pel operation circuit can be omitted. It is necessary to provide the selector 45,
45 is the output of the half-pel operation circuit 12 and the memory data bus 6
Since only the output of the half-pel arithmetic circuit 12 is switched, the configuration is simpler.

Further, the prediction error 0 detection circuit 41 can detect not only information on the presence or absence of a prediction error but also information on whether or not there is half-pel motion information from the encoding unnecessary information. And if there is half-pel motion information, even when there is no prediction error,
It is also conceivable that the motion compensation decoding process and the writing process of the restored image data are not skipped. In this case, the reduction rate of the access to the image memory 42 is reduced, but the half-pel operation circuit 34 in FIG. 10 and the selector 45 in FIG. 13 can be omitted, and the circuit scale can be reduced.

Similarly, in the embodiment shown in FIGS. 5 and 9, when there is half-pel motion information, even when the prediction error value is equal to or smaller than the threshold, the motion compensation decoding process and the restoration are performed. Obviously, the half-pel operation circuit 34 can be omitted by not skipping the writing process of the image data.

The CBP of the encoding unnecessary information is
Information indicating the presence or absence of a prediction error may be included in blocks lower than the macro block. In this case, the prediction error 0 detection circuit 41 may determine the presence or absence of a prediction error in units of lower blocks, and control skipping in units of lower blocks.

In the present embodiment, a frame image has been described as an example, but it is apparent that the present invention can be applied to a field image.

[0149]

As described above, according to the present invention, the decoding process can be sped up, and the bus occupancy of the image memory is reduced, so that the image memory can be used for other functions. And the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a video decoding device according to the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment of FIG. 1;

FIG. 3 is a flowchart showing a moving image decoding method according to another embodiment of the present invention.

FIG. 4 is a flowchart showing a moving image decoding method according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a moving picture decoding apparatus according to another embodiment of the present invention.

FIG. 6 is an explanatory diagram for explaining the embodiment in FIG. 5;

FIG. 7 is a flowchart for explaining the operation of the embodiment of FIG. 5;

FIG. 8 is a flowchart for explaining the operation of the embodiment of FIG. 5;

FIG. 9 is a block diagram showing a video decoding device according to another embodiment of the present invention.

FIG. 10 is a block diagram showing a video decoding device according to another embodiment of the present invention.

FIG. 11 is a flowchart for explaining the operation of the embodiment of FIG. 10;

FIG. 12 is a flowchart for explaining the operation of the embodiment of FIG. 10;

FIG. 13 is a block diagram showing a moving picture decoding apparatus according to another embodiment of the present invention.

FIG. 14 is a block diagram showing a conventional video decoding device.

FIG. 15 is a flowchart for explaining the operation of the conventional example.

FIG. 16 is an explanatory diagram for explaining encoding unnecessary information.

FIG. 17 is an explanatory diagram for explaining encoding unnecessary information.

[Explanation of symbols]

5 ... adder, 6 ... memory data bus, 8 ... reference memory,
21: Below threshold detection circuit, 22: Switch, 23: Selector

Claims (13)

[Claims] 1. A prediction error value indicating a magnitude of a prediction error of an encoded signal encoded in a predetermined block unit by motion compensation prediction encoding using a prediction error between a current image and a reference image. A procedure for obtaining the reference image from the encoded signal, and for obtaining a decoded image using the reference image and the prediction error while skipping motion compensation decoding based on the magnitude of the prediction error. An output step of outputting the reference image as the decoded image when outputting the decoded image when the motion compensation decoding process is skipped in the decoding procedure. 2. The decoding step, wherein the prediction error value is a first
2. The moving picture decoding method according to claim 1, wherein the motion compensation decoding process is skipped when the difference is equal to or less than the threshold value. 3. The moving picture according to claim 1, wherein the decoding step skips the motion compensation decoding when the sum of the prediction error values in the predetermined block unit is equal to or less than a second threshold. Image decoding method. 4. The decoding procedure according to claim 1, wherein a total number of the prediction error values equal to or smaller than a third threshold value is equal to a fourth threshold value in units of the predetermined block.
2. The moving picture decoding method according to claim 1, wherein the motion compensation decoding process is skipped when the difference is equal to or less than the threshold value. 5. The decoding procedure according to claim 1, wherein the motion compensation decoding process is skipped in the prediction error unit, the motion compensation decoding process is skipped in the predetermined block unit, or the motion compensation decoding process is performed in the predetermined image block unit. The moving picture decoding method according to claim 1, wherein whether to skip the moving picture can be changed. 6. A decoding means for receiving a coded signal coded in a predetermined block unit by motion compensation prediction coding using a prediction error between a current image and a reference image and obtaining a decoded image by a predetermined decoding process A storage unit that holds the decoded image as a reference image; a prediction error detection unit that detects a magnitude of the prediction error obtained in the process of the predetermined decoding process and outputs a detection result; A skip unit for omitting an addition process between the reference image and the prediction error from the storage unit based on the motion compensation decoding process among predetermined decoding processes of the decoding unit; Output means for outputting the reference image held in the storage means as the decoded image when outputting the decoded image when the decoding process is skipped. Video decoding apparatus characterized by Bei was. 7. The skip unit can change whether to skip the motion compensation decoding process in units of the prediction error, in units of the predetermined blocks, or in units of predetermined image blocks. 7. The moving picture decoding apparatus according to claim 6, wherein: 8. The video decoding apparatus according to claim 6, wherein the skip unit skips the motion compensation decoding process when the value of the prediction error is equal to or less than a first threshold. 9. The motion compensation decoding process according to claim 6, wherein the skip unit skips the motion compensation decoding process when the sum of the prediction error values in the predetermined block unit is equal to or less than a second threshold value. Video decoding device. 10. The motion compensation decoding process when the total number of prediction error values equal to or less than a third threshold value is equal to or less than a fourth threshold value in units of the predetermined block. The moving picture decoding apparatus according to claim 6, wherein 11. The decoding device according to claim 1, wherein the output unit stores a decoded image that has been subjected to the motion compensation decoding process by the decoding unit, and information about a storage position on the storage unit of the reference image that skips the motion compensation decoding process. The skip information storage means to be held, and by switching readout between the decode storage means and the storage means based on the information stored in the skip information storage means, the decoded image stored in the decode storage means 7. The moving picture decoding apparatus according to claim 6, further comprising: reading means for outputting a reference picture whose motion compensation decoding processing has been skipped. 12. The moving picture decoding apparatus according to claim 11, wherein said decoding storage means is shared with said storage means. 13. The moving picture decoding apparatus according to claim 11, wherein said skip information storage means is shared with said decoding storage means.