KR100226702B1 - Method for transitioning block status during address generation in a frame memory - Google Patents

Abstract

Disclosed is a block state transition method when an address is generated in a frame memory used in a motion compensation device. In the block state transition method, when the position of the luminance blocks b0 to b3 of the macroblock predicted by the motion compensation is applied to the RAS line in the vertical and horizontal directions with respect to one frame, the block b0 is fetched, and then the blocks b2, changing the row address whenever fetching in the order of b1 and b3; If the CAS lines are hung in the vertical and horizontal directions, fetching the block b0 and then changing the dress every time it fetches in the order of blocks b2, b1, b3; When the RAS line in the vertical direction and the CAS line in the horizontal direction are hung, fetch block b0, fetch block b2 by changing the open address of block b0, fetch block b1 by changing the row address of block b0, Fetching block b3 by changing the open dress of block b1; When the CAS line in the vertical direction and the RAS line in the horizontal direction are hung, fetch block b0, fetch block b2 by changing the row address of block b0, fetch block b1 by changing the open address of block b0, Fetching block b4 by changing the row address of block b1.

Description

Block state transition method when address occurs in frame memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory for a motion compensator, particularly when generating a row address (RA) and a column address (CA) to read a predicted macroblock from the frame memory. The present invention relates to a method for transitioning states of blocks to be read according to a position within one frame of a macroblock.

The motion compensation technique used in the Moving Picture Experts Group (MPEG) -2 standard is to reduce temporal redundancy by estimating and compensating for motion between two adjacent temporal pictures in macroblock units. That is, in the motion estimation and compensation process, a neighboring image is compared with the current image to detect a motion vector, which is information about an object's motion, and the current image is predicted using the motion vector.

In an MPEG-2 video encoder using such a motion compensation technique, the P picture performs forward motion compensation on the basis of the I picture or P picture of the previous picture with respect to the current picture, and the B picture performs the current picture. The best one is selected from among motion compensation blocks obtained by performing forward motion compensation, reverse motion compensation, and interpolated motion compensation based on the I picture or P picture of the previous picture and the I picture or P picture of the next picture.

The frame memory is used to store the I picture or P picture of the previous picture and the I picture or P picture of the next picture as the reference picture for motion compensation. In addition, the frame memory is used to temporarily store the decoded picture and read out the display order in a MPEG-2 video decoder because the decoding order and the display order are different from each other.

However, the frame memory as described above must have a capacity to store at least three frames of image data according to the I picture and the P picture or the distance M between the P picture and the P picture, and thus the price thereof is expensive, and therefore, the entire picture. In addition to raising the price of the decoder, there is a problem that the delay time from the completion of decoding to the display increases.

Accordingly, an object of the present invention is to solve the above-mentioned problems, in order to solve the above-mentioned problems, an area for storing reference image data when compensating for motion, an area for storing decoded image data for display, and a coded bitstream input to an image decoder. In a frame memory in which a region is implemented on one memory module, when a row address (RA) and a column address (CA) are generated to read a predicted macroblock from the frame memory, The present invention provides a method for transitioning states of blocks to be read according to a predicted position of a macroblock in one frame having a RAS box structure and a predetermined macroblock structure.

In order to achieve the above object, a block state transition method according to the present invention when an address is generated in a frame memory includes first to fourth frames for storing an image signal of one frame each having a predetermined RAS box structure and a predetermined macroblock structure. In a frame memory consisting of a storage area, when the position of the luminance blocks b0 to b3 of the macroblock predicted by the motion compensation is RAS line in the vertical and horizontal directions with respect to the one frame, the block b0 is fetched. Changing the row address every time the blocks are fetched in the order of blocks b2, b1, and b3; If the CAS lines are hung in the vertical and horizontal directions, fetching the block b0 and then changing the dress every time it fetches in the order of blocks b2, b1, b3; When the RAS line in the vertical direction and the CAS line in the horizontal direction are hung, fetch block b0, fetch block b2 by changing the open address of the block b0, and fetch block b1 by changing the row address of the block b0. Fetching block b3 by changing the opening dress of block b1; When the CAS line in the vertical direction and the RAS line in the horizontal direction are hung, fetch block b0, fetch block b2 by changing the row address of block b0, and fetch block b1 by changing the open address of block b0. Fetching block b4 by changing the row address of block b1; Fetching the block b0 when the RAS line is hung only in the horizontal direction, and changing the row address of the block b0 to fetch the block b2; If the CAS line is hung only in the horizontal direction, fetching block b0, fetching block b2 by changing the open dress of block b0; If the RAS line is hung only in the vertical direction, fetching the block b0 and fetching the block b1 by changing the row address of the block b0; And fetching the block b0 when the CAS line is hung only in the vertical direction, and changing the open dress of the block b0 to fetch the block b1.

1 is a diagram showing the structure of a frame memory adopted in the present invention;

2 is a diagram illustrating a scheduling order of the frame memory shown in FIG. 1;

3 is a diagram illustrating an example of a method for setting a RAS box for one frame in the frame memory shown in FIG. 1;

4 is a view showing an example of a macroblock structure in the RAS box shown in FIG.

FIG. 5 is a diagram illustrating the number of cases where a predicted macroblock is located in one frame consisting of the RAS box shown in FIG.

6 is a state diagram showing a block state transition method when an address is generated according to the present invention;

FIG. 7 is a block diagram illustrating an apparatus in which the block state transition method illustrated in FIG. 6 is executed.

* Explanation of symbols for main parts of the drawings

100: frame memory 200: memory control unit

100-1 to 100-4: First to fourth frame storage areas

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 illustrates a structure of a frame memory adopted in the present invention, in which the frame memory 100 includes a restored image data write operation, a data read operation for motion compensation, and a data read operation for display to a memory controller (not shown). Synchronous-DRAM (SDRAM) controlled by a burst length of 8 will be taken as an example. The frame memory 100 has two memory banks, bank 1 and bank 2, bank 1 has first and second frame storage areas 100-1 and 100-2, and bank 2 stores third and fourth frames. There are regions 100-3 and 100-4. Here, the first to fourth frame storage areas 100-1, 100-2, 100-3, and 100-4 have a capacity for storing pixel data of one frame, respectively, and the first to fourth frame storage areas 100-1, 100-. 2,100-3 and 100-4 each have 1,024 row addresses, and have a column address of 256 words (where 1 word is 8 bits). One address stores eight Y pixels, two Cr pixels, two Cb pixels, and a total of 12 pixel data. Here, 1,024 row addresses mean the number of RAS boxes. The column address of 256 words is derived by 8 macroblocks per one RAS box * 32 pixels per macroblock (= 256 pixels).

The actual physical row address of the frame memory 100 is 000 _H to 3FF _H , 400 _H to 7FF _H for the first to fourth frame storage areas 100-1 to 100-4, respectively. , 800 _H to BFF _H and C00 _H to FFF _H. However, the first to fourth frame storage regions 100-1 to 100-4 exist independently, and the second and fourth frames corresponding to the macroblocks located at predetermined row addresses of the first frame storage region 100-1 are respectively provided. The macroblocks of the third frame storage areas 100-2 and 100-3 have the same row address. As such, the row address in the first to third frame storage areas 100-1 to 100-3 is referred to as a virtual row address. Then, based on the scheduling order of the frame memory 100 as shown in FIG. 2 during motion compensation, an address used to convert a virtual row address in a corresponding storage area in which a reference image is located into a physical row address is framed. It is called the frame offset address and is called RA [11:10]. That is, if RA [11:10] is '00', the first frame storage area 100-1, if '01', the second frame storage area 100-2, and if the '10', the third frame storage area 100 -3) and '11' indicate the fourth frame storage areas 100-4, respectively.

Here, the first and second frame storage areas 100-1 and 100-2 are used to store reconstructed I-picture or motion-compensated P-picture image data for use as a reference image for motion compensation and simultaneously for display. The three-frame storage area 100-3 is used to store the motion compensated B-picture image data, and the fourth frame storage area 100-4 stores the encoded bitstream input to the image decoder in units of predetermined bits. Used to save.

FIG. 2 shows a scheduling order of the frame memory 100 shown in FIG. 1, and the decoding order is I, P, B, B, P, B, B, P, B, B, P, B, B, I. , P, B, B, ... and the display order is I, B, B, P, B, B, P, B, B, P, B, B, P, I, B, B, ... For example, the display latency is 2 pictures. Here, the underlined portion indicates the picture currently being decoded, the arrow indicates the picture to be referred for motion compensation, and the storage area to which 'D' is added indicates that image data is being read out for display.

FIG. 3 shows an example of a method for setting a RAS box for one frame in the frame memory 100 shown in FIG. 1. For example, when one frame includes 1,920 pixels * 1,088 pixels, 30 RAS boxes * 34 It is divided into RAS boxes, a total of 1,020 Row Address Strobe (RAS) boxes. That is, the number of the RAS box is the row address (RA) of the frame memory 100. Here, one RAS box is composed of four macroblocks * 2 macroblocks and a total of eight macroblocks MB0 to MB7. Each macroblock is divided into four blocks b0 to b3 when the luminance Y block is taken as an example.

FIG. 4 shows an example of a macroblock structure in the RAS box shown in FIG. 3, and includes four luminance (Y) blocks, one color difference (Cr) block, and one color difference (Cb) block. The luminance (Y) block consists of eight boxes (b0-0 to b0-7, b1-0 to b1-7, b2-0 to b2-7, and b3-0 to b3-7), respectively, and two color differences. The (Cr, Cb) block is composed of eight sub boxes (sb0-0 to sb0-7, sb1-0 to sb1-7, sb2-0 to sb2-7, sb3-0 to sb3-7), respectively. Then, 8 pixel data in 8 * 1 format for each box constituting the Y block, 2 pixel data in 2 * 1 format for each box constituting the Cr block, and 2 * 1 format for each box constituting the Cb block. There are two pixel data of.

3 and 4, when the open dress CA [7: 0] is examined, the position of the macro block in one RAS box is CA [7: 5] and the position of the block in the macro block. CA [4: 3], the position of the box in the block is called CA [2: 0]. In addition, a line in which the row address is changed in one frame is called a RAS line, and a line in which the open address is changed is called a CAS (Column Address Strobe) line.

FIG. 5 is a diagram illustrating the number of cases in which the predicted macroblocks are located in one frame including the RAS box shown in FIG. 3. The case a is illustrated for four blocks b0 to b3 constituting the predicted macroblocks. Is the case where the RAS line is hung in the horizontal and vertical directions, case b is the case where the CAS line is hung in the horizontal and vertical direction, case c is the case where the RAS line is hung in the vertical direction, and case d is If the CAS line is hung in the vertical direction and the RAS line is in the horizontal direction, the case e1 is hung in the horizontal direction only. If the case e2 is hung in the horizontal direction only, the case f1 is in the vertical direction. When only the RAS line is hanging, the case f2 shows the case where the CAS line is hanging only in the vertical direction.

6 is a state diagram illustrating a method for transitioning a block state when an address is generated according to the present invention. This state diagram for each case defined as shown in FIG. 5 is as follows.

First, in the virtual memory map of the frame memory 100, the RAS line and the CAS line exist, so that the actual memory map and mismatching occur. Accordingly, the start address of the current macroblock MB to be compensated for motion, that is, the slice position (slice_position) and the macroblock position (mb_position), and the position of the macroblock predicted from the motion vectors mv_v and mv_h are shown in FIG. It finds in the same frame structure and determines how the four blocks b0 to b3 are located with respect to the RAS line and the CAS line. Depending on how the RAS line and the CAS line are applied to the macroblock, when fetching pixel data in units of one macroblock, the address for fetching each block must be changed.

For example, in case a, block b0 having a row address RA_1a and an open address CA_1a is fetched, and then block b2 is fetched by changing the row address RA_1a to a row address RA_2a. Next, the block b3 is fetched by changing the row address RA_1a to the row address RA_3a, and the block b4 is fetched by changing the row address RA_3a to the row address RA_4a. That is, in case a, the row address is changed every time the block b0 is fetched in the order of blocks b2, b1, and b3.

In case b, the block b0 having the row address RA_1b and the open dress CA_1b is fetched, and then the block b2 is fetched by changing the open dress CA_1b to the open dress CA_2b. Next, the open dress CA_1b is changed to the open dress CA_3b to fetch the block b3, and then the open dress CA_3b to the open dress CA_4b to fetch the block b4. That is, in case b, the dress is changed every time the data is fetched after the block b0, and then the blocks b2, b1, and b3.

In case c, the block b0 having the row address RA_1c and the open dress CA_1c is fetched, and then the block b2 is fetched by changing the open dress CA_1c to the open dress CA_2c. Next, the block b1 is fetched by changing the row address RA_1c to the row address RA_2c, and the block b3 is fetched by changing the open dress CA_1c to the dress CA_2c.

In case d, the block b0 having the row address RA_1c and the open address CA_1c is fetched, and then the block b2 is fetched by changing the row address RA_1d to the row address RA_2d. Next, the open dress CA_1d is changed to the open dress CA_2d to fetch the block b1, and the row address RA_1d is changed to the row address RA_2d to fetch the block b3.

In the case e1, the block b0 having the row address RA_1e1 and the open address CA_1e1 is fetched, and then the block b2 is fetched by changing the row address RA_1e1 to the row address RA_2e1.

In case e2, the block b0 having the row address RA_1e2 and the open dress CA_1e2 is fetched, and then the block b2 is fetched by changing the open dress CA_1e2 to the open dress CA_2e2.

In case f1, the block b0 having the row address RA_1f1 and the open address CA_1f1 is fetched, and then the block b1 is fetched by changing the row address RA_1f1 to the row address RA_2f1.

In case f2, the block b0 having the row address RA_1f2 and the open dress CA_1f2 is fetched, and then the block b1 is fetched by changing the open dress CA_1f2 to the open dress CA_2f2.

On the other hand, the change distance of each of the row address and each of the opening dress is different depending on the structure of the RAS box or the structure of the macro block.

FIG. 7 is a block diagram illustrating an apparatus in which the block state transition method of FIG. 6 is executed, and is typically performed by the memory controller 200. That is, the memory controller 200 inputs a start address, a motion vector, and various parameters of a current macroblock in a picture to be motion compensated, and fetches a corresponding macroblock of a picture to be referred to in units of blocks or boxes. Is applied to the frame memory 100 via the address bus. In addition, various control signals for controlling write and read operations of the frame memory 100 are applied to the frame memory 100.

On the other hand, the above detailed description is intended to describe particular embodiments presented herein and is not intended to limit the present invention. Those skilled in the art may make various changes and modifications according to the structure of the RAS box and the structure of the macroblock block within the technical spirit of the present invention with reference to the above detailed description and drawings.

As described above, in the frame memory in which the first to fourth frame storage areas are implemented on one memory module, a row address and a column address are generated to read the predicted macroblock from the frame memory. In this case, the state of blocks to be read may be changed according to the predicted position of the macroblock in one frame having a predetermined RAS box structure and a predetermined macroblock structure.

Claims (3)

A frame memory comprising first to fourth frame storage areas for storing a video signal for one frame each having a predetermined RAS box structure and a predetermined macroblock structure, the luminance block b0 of the macroblock predicted by motion compensation. To the position of the block b3 with respect to the one frame, When the RAS lines are caught in the vertical and horizontal directions, fetching the block b0, and then changing the row address every time the blocks b2, b1, and b3 are fetched; If the CAS lines are hung in the vertical and horizontal directions, fetching the block b0 and then changing the dress every time it fetches in the order of blocks b2, b1, b3; When the RAS line in the vertical direction and the CAS line in the horizontal direction are hung, fetch block b0, fetch block b2 by changing the open address of the block b0, and fetch block b1 by changing the row address of the block b0. Fetching block b3 by changing the opening dress of block b1; When the CAS line in the vertical direction and the RAS line in the horizontal direction are hung, fetch block b0, fetch block b2 by changing the row address of block b0, and fetch block b1 by changing the open address of block b0. Fetching block b4 by changing the row address of block b1; Fetching the block b0 when the RAS line is hung only in the horizontal direction, and changing the row address of the block b0 to fetch the block b2; If the CAS line is hung only in the horizontal direction, fetching block b0, fetching block b2 by changing the open dress of block b0; If the RAS line is hung only in the vertical direction, fetching the block b0 and fetching the block b1 by changing the row address of the block b0; And And fetching block b0 if the CAS line is hung only in the vertical direction, and changing the open dress of the block b0 to fetch block b1. 2. The method of claim 1, wherein a change distance between each row address and each open address varies depending on the structure of the RAS box. The method of claim 1, wherein a change distance between each row address and each open address varies according to the structure of the macroblock.

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