KR100235488B1 - Apparatus for rearranging data output from a frame memory according to scanning pattern of a frame memory - Google Patents

Abstract

The present invention relates to an output data rearrangement apparatus according to a method of reading a frame memory.

Such an apparatus of the present invention is a frame memory 300 having a field structure for storing pixel data for reference in motion compensation in macroblock units, and includes a conventional frame memory in order of first block, second block, and third block. Unlike the method of reading 300, in the present invention, in order to read the second and third blocks together after reading the first block, the pixel data of the predicted macroblock is one block in which the reference point RP is located. And a data storage unit 310 which sequentially reads and stores the frame memory 300 in a box unit from two blocks in a progressing direction to the right from the next block of the block where the reference pointer is located, and the data storage unit 310. Pixel data output in units of boxes over three blocks according to the pixel address PA of the reference point RP of the predicted macroblock. By shifting by positive number, it comprises the effective pixel data corresponding to the predictive macro block with the data sorting unit 350 for extracting considering up to half a pixel. Therefore, by reading a box unit over a maximum of three blocks in accordance with the pixel address of the reference point of the predicted macroblock, and shifting left by up to seven times, it is possible to rearrange the pixel data corresponding to the predicted macroblock.

Description

Apparatus for rearranging data output from a frame memory according to scanning pattern of a frame memory

The present invention relates to a motion compensation device, and more particularly, to an apparatus for rearranging output data of a frame memory.

The motion compensation technique used in the Moving Picture Experts Group (MPEG) -2 standard is to reduce temporal redundancy by estimating and compensating for motion between two adjacent temporal pictures in macroblock units. That is, in the motion estimation and compensation process, a neighboring image is compared with the current image to detect a motion vector, which is information about an object's motion, and the current image is predicted using the motion vector.

In an MPEG-2 video encoder using such a motion compensation technique, the P picture performs forward motion compensation on the basis of the I picture or P picture of the previous picture with respect to the current picture, and the B picture performs the current picture. The best one is selected from among motion compensation blocks obtained by performing forward motion compensation, reverse motion compensation, and interpolated motion compensation based on the I picture or P picture of the previous picture and the I picture or P picture of the next picture.

The frame memory is used to store the I picture or P picture of the previous picture and the I picture or P picture of the next picture as the reference picture for motion compensation. In addition, the frame memory is used to temporarily store a decoded picture and fetch it according to the display order since the decoding order and the display order are different in the MPEG-2 video decoder.

However, the frame memory as described above has a capacity to store at least three frames of image data according to the I picture and the P picture or the distance M between the P picture and the P picture, and therefore, the price is expensive, and thus, the entire picture. In addition to raising the price of the decoder, there is a problem that the delay time from the completion of decoding to the display increases.

Accordingly, the present invention has been made to solve the above problems, and includes a region for storing reference image data, a region for storing decoded image data for display, and an encoded bitstream input to an image decoder. In a frame memory in which an area to be stored is implemented on one memory module, pixel data corresponding to a macroblock predicted by a start address and a motion vector of a current macroblock is read in box units over a maximum of three blocks. It is an object of the present invention to provide an apparatus for rearranging pixel data corresponding to a predicted macroblock.

An apparatus of the present invention for providing the above object, in the frame memory of the field structure for storing the pixel data for reference in the motion block in macroblock units, the start address and the motion vector of the current macroblock to be motion compensated The pixel data of the macroblock predicted from is sequentially read out from the frame memory in units of two blocks in the direction of progress toward the right from one block in which the reference point RP is located and the next block of the block in which the reference pointer is located. And shifting the pixel data output in the box order over the three blocks from the data storage unit by a predetermined number of times according to the pixel address PA of the reference point RP of the predicted macroblock. Half-pixel the effective pixel data corresponding to the predicted macroblock. It is characterized in that it comprises a data sorting unit to be extracted in consideration.

1 is a diagram showing the structure of a frame memory adopted in the present invention;

FIG. 2 is a diagram illustrating an example of a method for setting a RAS box for one frame in the frame memory shown in FIG. 1;

3 is a view showing an example of a macroblock structure in the RAS box shown in FIG.

4A and 4B illustrate an example of a position of a predicted macroblock;

5A and 5B illustrate output data according to a method of reading a frame memory according to the present invention.

It is a block diagram which shows the structure of a rearrangement apparatus.

＊ Explanation of symbols for main parts of drawing

200: memory controller 300: frame memory

310: data storage unit 330: FIFO

350: data sorting unit 35a to 35g: first to seventh shifting machine

F11 ~ F18, F41 ~ F64: Flip-flop L11 ~ L1, L2, L3, L41 ~ L47: Latch

M1 ~ M23: Multiplexer C1 ~ C7: Counter

300-1 to 300-4: First to fourth frame storage areas 500: Common bus

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a structure of a frame memory adopted in the present invention, in which the frame memory 100 includes a restored image data write operation, a data read operation for motion compensation, and a data read operation for display to a memory controller (not shown). Controlled by SRAM. The frame memory 100 has two memory banks, bank 1 and bank 2, bank 1 has first and second frame storage areas 100-1 and 100-2, and bank 2 stores third and fourth frames. There are regions 100-3 and 100-4. Here, the first to fourth frame storage areas 100-1, 100-2, 100-3, and 100-4 have a capacity for storing pixel data of one frame, respectively, and the first to fourth frame storage areas 100-1, 100-. 2,100-3 and 100-4 each have 1,024 row addresses, and have a column address of 256 words (where 1 word is 8 bits). One address stores eight Y pixels, two Cr pixels, two Cb pixels, and a total of 12 pixel data. Here, 1,024 row addresses mean the number of RAS boxes. And the 256-word column address comes from (8 macroblocks per RAS box * 32 boxes per macroblock = 256 boxes).

The actual physical row address of the frame memory 100 is 000 _H to 3FF _H , 400 _H to 7FF _H for the first to fourth frame storage areas 100-1 to 100-4, respectively. , 800 _H to BFF _H and C00 _H to FFF _H. However, the first to fourth frame storage regions 100-1 to 100-4 exist independently, and the second and fourth frames corresponding to the macroblocks located at predetermined row addresses of the first frame storage region 100-1 are respectively provided. The macroblocks of the third frame storage areas 100-2 and 100-3 have the same row address. As such, the row address in the first to third frame storage areas 100-1 to 100-3 is referred to as a virtual row address. Then, based on the scheduling order of the frame memory 100 as shown in FIG. 2 during motion compensation, an address used to convert a virtual row address in a corresponding storage area in which a reference image is located into a physical row address is framed. It is called the frame offset address and is called RA [11:10]. That is, if RA [11:10] is '00', the first frame storage area 100-1, if '01', the second frame storage area 100-2, and if the '10', the third frame storage area 100 -3) and '11' indicate the fourth frame storage areas 100-4, respectively.

Here, the first and second frame storage areas 100-1 and 100-2 are used to store reconstructed I-picture or motion-compensated P-picture image data for use as a reference image for motion compensation and simultaneously for display. The three-frame storage area 100-3 is used to store the motion compensated B-picture image data, and the fourth frame storage area 100-4 stores the encoded bitstream input to the image decoder in units of predetermined bits. Used to save.

FIG. 2 illustrates an example of a RAS box setting method for one frame in the frame memory 100 shown in FIG. 1. For example, when one frame includes 1,920 pixels * 1,088 pixels, 15 RAS boxes * 68 It is divided into RAS boxes, a total of 1,020 Row Address Strobe (RAS) boxes. That is, the number of the RAS box is the row address (RA) of the frame memory 100. Here, one RAS box is composed of 8 macroblocks * 1 macroblocks and a total of 8 macroblocks MB0 to MB7. Each macroblock is divided into four blocks b0 to b3 when the luminance Y block is taken as an example.

FIG. 3 shows an example of a macroblock structure in the RAS box shown in FIG. 2, with four luminance (Y) blocks b0 to b3, one color difference (Cr) block, and one color difference (Cb) block. Four luminance (Y) blocks are composed of eight boxes (b0-0 to b0-7, b1-0 to b1-7, b2-0 to b2-7, and b3-0 to b3-7), respectively. Each of the two color difference (Cr, Cb) blocks has eight sub boxes (sb0-0 to sb0-7, sb1-0 to sb1-7, sb2-0 to sb2-7, and sb3-0 to sb3-7). It consists of. 8 pixel data in 8 * 1 format is included in each box constituting the Y block, 2 pixel data in 2 * 1 format is formed in each sub box constituting the Cr block, and 2 * is in each sub box constituting the Cb block. There are two pixel data in one format.

The frame memory applied to the present invention is mapped to a field structure. FIG. 4A shows an example of the position of the predicted macroblock MBp in the upper field, and FIG. 4B shows the predicted macroblock in the lower field. As an example of the position of (MBp), the macroblock MBp predicted by the start address and the motion vector of the current macroblock to be motion compensated is divided into four macroblocks, that is, the macroblock MB7 and the macroblock. An example is shown of the symbol MB8, the macroblock MB127, and the macroblock MB128. In other words, the predicted macroblock (MBp) is located across four RAS boxes, RAS box 0, RAS box 1, RAS box 15 and RAS box 16. As shown in FIGS. 4A to 4B, six jump addresses JA0 to JA5 are required to read in two block units as a basic read scale.

5A and 5B are block diagrams illustrating an output data rearrangement apparatus according to a method of reading a frame memory according to an exemplary embodiment of the present invention. The memory control unit 200, the frame memory 300, the data storage unit 310, and the data are largely shown. It is composed of a sorting unit 350 and the common bus 500. In addition, the data storage unit 310 includes a FIFO 330 and second to third latches L2 and L3. The FIFO 330 is composed of nine box groups 33a to 33i in a pipeline form in consideration of upper and lower half pixels. Here, each of the box groups 33b to 33i except for the first box group 33a has the same configuration. For example, in the case of the box group 33b, the latch L11 and the eight flip-flops F11 to F18 are used. Is done. The data sorting unit 350 may include first to seventh shifters 35a to 35g. Here, the first to seventh shifters 35a to 35g have the same configuration in a pipeline form as shown in FIG. 5B. For example, in the case of the first shifter 35a, one latch L41 and 23 It consists of multiplexers M1-M23, one counter C1, and 24 flip-flops F41-F64.

Then, the operation and effects of the present invention will be described in detail with reference to FIGS. 1 to 5. Here, the luminance signal in the case where the motion form is the field estimation and compensation will be taken as an example.

In order to consider the worst case that may occur, the starting address of the current macroblock to be motion compensated, that is, the slice position and the macroblock position (mb-position), and the vertical and horizontal motion vectors The case in which the macroblock MBp predicted from is located as shown in FIG. 4 will be described.

In FIG. 4, pixel data corresponding to the predicted macroblock MBp is read in box units, that is, in units of 8 pixels. Therefore, when the scanning pattern is in the order as shown in FIG. 4 and the predicted macroblock MBp is read in units of two blocks, the block b3 of the macroblock MB7 in which the reference point RP is located first is read. Eight boxes are read from the box b3-2 and loaded onto the common bus 500. Subsequently, two boxes of the box b2-2 of the block b2 of the next macroblock MB8 and the box b3-2 of the block b3 of the macroblock MB8 are read, and the macroblock MB128 Two boxes are read sequentially from the box b2-0 of the block b2 of the block to the box b3-0 of the block b3 of the macroblock MB128. It is put on 500.

When pixel data is read in a box unit as described above, eight boxes should be read over a total of three blocks except that the reference point RP is placed at the start position of each macroblock. Thus, each box group 33a is read. A total of eight pixel data are read for ˜33i), and the remaining sixteen pixel data are read for the second to third latches L2 and L3. The present invention is to extract the pixel data corresponding to the predicted macroblock (MBp) from the pixel data read out in a box unit over a maximum of three blocks in the storage area of the frame memory 300 as described above.

In FIG. 5A, the memory controller 200 inputs a start address, a motion vector, and various parameters of a current macroblock to be motion compensated, and writes / reads an address and various control signals (eg, flow_en, wr1, The wr2 is supplied to the frame memory 300 and simultaneously supplied to the data storage 310. The flow enable signal flow_en and the first and second read control signals wr1 and wr2 may include a RAS box number where each block of the predicted macroblock MBp is located, a block position in a corresponding RAS box, and a corresponding block. It is determined by the reference point RP determined from the box position of and the pixel position in the box.

Taking the predicted macroblock MBp shown in FIG. 4A as an example, the flow enable signal flow_en starts from the box b3-2 of the block b3 of the macroblock MB7 in which the reference point RP is located. A signal for reading eight pixels, the first read control signal wr1 is a signal for reading eight pixels from one box b2-2 of the block b2 of the next macroblock MB8 to one block, The second read control signal wr2 is outputted from the second latch L2 and eight pixels from the box b3-2 of the block b3 of the macroblock MB8 directly output from the frame memory 300. Signal for reading data. In the present invention, it is assumed that the predicted macroblock MBp is input to the motion compensator (not shown) in units of two blocks from the frame memory 300.

The data storage unit 310 is for storing pixel data in a box unit loaded on the common bus 500 sequentially over a maximum of three blocks from the corresponding storage area of the frame memory 300.

According to the flow enable signal flow_en, the FIFO 330 transmits eight pixel data from the box b3-2 of the block b3 of the macroblock MB7 to the eight boxes, respectively, over eight boxes. Are stored sequentially in F18). The second latch L2 latches eight pixel data from the box b2-2 of the block b2 of the macroblock MB8 supplied from the common bus 500 according to the first read control signal wr1. . The third latch L3 includes eight pixel data corresponding to one box supplied from the second latch L2 and a macroblock MB8 supplied from the frame memory 300 according to the second read control signal wr2. The eight pixel data of the box b3-2 of the block b3 is latched.

In FIG. 5B, the data sorting unit 350 is applied to two blocks of the macroblock MBp predicted from pixel data (that is, 24 pixel data) over three blocks supplied from the data storage unit 310. To extract the pixel data (i.e., 16 pixel data) for each box group. To this end, the pixel address P.A for the reference point R.P of the predicted macroblock MBp is used.

In the first shifter 35a, the latch L41 latches 24 pixel data supplied from the data storage 310. The counter C1 supplies the selection control signal to the multiplexers M1 to M23 according to the pixel address P.A for the reference point R.P of the predicted macroblock MBp. The multiplexers M1 to M23 shift the pixel data left by one pixel in accordance with the selection control signal and output it. The flip-flops F41 to F63 temporarily store pixel data output from the multiplexers M1 to M23, and then supply them to the latch L42 of the second shifter 35b, and the flip-flop F64 is a latch ( The 24th pixel data is temporarily stored from L41 and then supplied to the latch L42 of the second shifter 35b. Here, the counter C1 operates as a down counter, and decreases the pixel address P.A by 1 to supply it to the counter C2.

In the second shifter 35b, the latch L42 latches 24 pixel data supplied from the first shifter 35a. The counter C2 supplies the selection control signal to the multiplexers M1 to M23 according to the pixel address by one. The multiplexers M1 to M23 shift the pixel data left by one pixel in accordance with the selection control signal and output it. The flip-flops F41 to F63 temporarily store pixel data output from the multiplexers M1 to M23, and then supply them to a latch (not shown) of a third shifter (not shown). The 24th pixel data is temporarily stored from the latch L42 and then supplied to the latch (not shown) of the third shifter (not shown). Here, the counter C2 operates as a down counter, and decreases the pixel address by one by one and supplies it to the counter (not shown) of the third shifter (not shown).

In the seventh shifter 35g, the latch L47 latches 24 pixel data supplied from the sixth shifter (not shown). The counter C7 supplies the selection control signal to the multiplexers M1 to M23 according to the pixel address reduced by one at the counter (not shown) of the sixth shifter (not shown). The multiplexers M1 to M23 shift the pixel data left by one pixel in accordance with the selection control signal and output it. The flip-flops F41 to F63 temporarily store pixel data output from the multiplexers M1 to M23, and then output them to a motion compensator (not shown), and the flip-flop F64 is a sixth shifter (not shown). The 24th pixel data is temporarily stored from the latch (not shown) and then output to the motion compensator (not shown).

In the first to seventh shifters 35a to 35g, the multiplexers M1 to M23 respectively have a first input signal on the left or a second input on the right with respect to two adjacent pixel data according to a selection control signal. Output the signal selectively. That is, when there is an address value input to the counters C1 to C7, the multiplexers M1 to M23 respectively output the second input signals by the selection control signal, so that the shifters are shifted to the left. When there is no address value input to the counters C1 to C7, the multiplexers M1 to M23 output the first input signals by the selection control signal, thereby preventing shifting. A maximum of seven shifting operations are performed according to the pixel address PA. For example, when the pixel address of the reference point RP is 011 ₂ in FIG. 4, the first to third shifters 35a to 35c may be used. Three shifting operations are performed, and the fourth to seventh shifters 35d to 35g are output as they are without shifting.

That is, the data sorting unit 350 shifts the 24 pixel data left by one pixel a predetermined number of times according to the pixel address P.A, thereby extracting 17 effective pixel data in consideration of half a pixel.

On the other hand, the above detailed description is intended to describe particular embodiments presented herein and is not intended to limit the present invention. Those skilled in the art may make various changes and modifications according to the structure of the RAS box, the structure of the macroblock block, the picture type, and the motion compensation form within the spirit of the present invention with reference to the above description and drawings.

As described above, in the apparatus of the present invention, when a macroblock predicted by a motion vector and a start address of a current macroblock to be motion compensated is read out from a corresponding storage area of a frame memory, the apparatus determines the pixel address of the predicted macroblock. Therefore, by reading in units of boxes over a maximum of three blocks and shifting left by up to seven times, the data can be rearranged into pixel data corresponding to the predicted macroblock.

Claims (4)

In the frame memory 300 having a field structure that stores pixel data for reference in motion compensation in macroblock units, The pixel data of the macroblock predicted from the start address and the motion vector of the current macroblock to be compensated for motion is one block in which the reference point RP is located and two blocks in the right direction from the next block of the block in which the reference pointer is located. A data storage unit 310 sequentially reading and storing the data from the frame memory 300 in a box unit over a block; And The predicted macro is shifted by shifting pixel data output in the box order from the data storage unit 310 over a predetermined number of times according to the pixel address PA of the reference point RP of the predicted macroblock. And a data sorting unit (350) for extracting effective pixel data corresponding to blocks up to half pixels. The method of claim 1, wherein one frame picture stored in the frame memory 300 comprises a plurality of RAS boxes, the RAS box is composed of eight macroblocks, and the macroblocks are four blocks for luminance blocks. Wherein the block has a 1 box * 8 box format, and the box has an 8 pixel * 1 pixel format. The data storage unit 310 of claim 1, wherein the data storage unit 310 comprises a FIFO 330 composed of nine box groups 33a to 33i each having a pipeline shape, and first and second read control signals wr1 and wr2. Frame consists of two latches (L2, L3) operating in accordance with each of the box group is composed of eight flip-flops (F11 ~ F18) in accordance with the flow enable signal (flow_en). Output data rearrangement device according to the reading method. The data sorting unit 350 is configured in a pipeline form, and the first to second pixel data output from the data storage unit 310 and the frame memory 300 are shifted left by one pixel. Output data rearrangement apparatus according to the reading method of the frame memory, characterized in that it comprises a seventh shifter (35a ~ 35g).

Images