KR19990024664U - Time slot input device of electronic exchange signal detection circuit - Google Patents

Abstract

In order to solve the problem of outputting wrong data when the clock is shaking due to an abnormality on the clock supply board or transmission path or the DSP itself, the exchanger signal can accurately synchronize the frame sync signal with the channel using a counter. The present invention relates to a time slot input device of a detection circuit. A frame synchronization signal and a channel clock are synchronized by using an inverted input obtained by inverting an external interrupt input from DSP 0 through an inverter and a channel division clock inputted into DSP 0. 4-bit counter for counting 16 to receive 16 data after frame sync signal generation, multiple JK flip-flops for controlling the output of the counter, and logically preventing 16 or more data from being input to the DSP Inputted to DPS 0 to Null is achieved by having an OR gate for outputting the classification clock.

Description

Time slot input device of electronic exchange signal detection circuit

The present invention relates to a signal detection circuit of an electronic exchange, and more particularly, to a time slot input device of a signal detection circuit capable of accurately synchronizing a frame synchronization signal with a channel using a counter.

A signal detection method using a conventional electronic switch signal detection circuit indicates the start of channel 0 with a frame synchronization signal of 8 KHz, as shown in FIG. 1, which is a timing diagram generated at each terminal of a digital signal processor (DSP). It operates as an external interrupt signal INT_TS of the digital signal processor (hereinafter referred to as "DSP"). In addition, by dividing the clock of 4 MHz, each time slot is displayed as 256 KHz, and the detection data is serially input to the DSP. Channels 0-15 are input to DSP 0 and 16-31 are input to DSP1, respectively.

A 4 MHz clock is divided to produce a 256 KHz clock that counts into 32 channels. The start of channel 0 is distinguished by a frame synchronization signal of 8 KHz, which operates as an external interrupt signal of DSP 0 and 1. Channels 0-15 are input to DSP 0 and channels 16-31 are input to DSP1, respectively. From the low edge of 256 KHz, the signal data is input to the DSP at the clock of 2 MHz. These data are detected by the signal detection algorithm stored in the internal buffer of DSP by interrupt during program execution. D0INT of FIG. 1 is an external interrupt signal input to DS 0, which is a low signal when it is recognized, and indicates a signal indicating that channel 0 starts. D0ILD is a channel input to DS 0. FIG. The clock, ICK, is a 2 MHz clock signal for receiving data of the corresponding channel, and the DDI is the 8-bit data that is input.

Referring to the figure, 16 clocks of D0ILD after an interrupt has occurred means a channel of 0-15, and data is input from the low edge of this clock. At this time, the data is input to the DDI of DS in accordance with the ICK of 2 MHz.

In the case of the signal detection method using the conventional signal detection circuit as described above, the 16 channels in front of the 256 KHz clock indicating the time slots have the DSP 0 and the rear only after an external interrupt signal indicating the start of channel 0 occurs. The 16 channels must be entered as DS1. However, in many cases, when the 8 KHz frame synchronization signal clock or the 4 MHz clock is unstable, channel classification is not possible and data of 16 channels or more is input to the signal detection circuit to output wrong values or to remove the internal buffer of the DSP. There is a problem that makes it unrecoverable.

The present invention was devised in view of the above-mentioned problems of the prior art, and uses counters to solve the problem of outputting wrong data or the DPS itself not being recovered when the clock is shaken due to an abnormality in the clock supply board or transmission path. An object of the present invention is to provide a time slot input device of an electronic switch signal detection circuit capable of accurately synchronizing a frame synchronization signal with a channel.

1 is a timing diagram generated at each terminal of a conventional digital signal processor,

2 is a block diagram of a time slot input device of an electronic switch signal detection circuit according to the present invention;

3 is a timing diagram generated at each terminal of the digital signal processor of the present invention.

*** Explanation of symbols for main parts of drawing ***

21: counter 22,23,24: J-K flip flop

25: logical sum gate 26,27: inverter

Time slot input device of the electronic switch signal detection circuit according to the present invention for achieving the above object, the channel division clock is input to the inverting input and the DSP 0 inverted the external interrupt input from the DS 0 through the inverter A 4-bit counter for counting 16 to receive 16 data after the frame sync signal is generated by synchronizing the frame sync signal with the channel clock, a plurality of JK flip-flops for controlling the output of the counter, and 16 In order to logically prevent more than one data from being input to the DS, a logical sum gate for outputting a channel division clock input to the DS 0 is characterized in that it is made.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to the time slot input device of the electronic switch signal detection circuit according to the present invention with reference to the block diagram of Figure 2, the inverted input and the inverted input inverted through the inverter 26 the external interrupt signal (D0INT) input from DSP 0 A 4-bit counter 21 for counting 16 to receive 16 data after the frame synchronization signal is generated by synchronizing the frame synchronization signal with the channel clock using the channel division clock D0ILD_IN inputted to the DSP 0, and the counter Three JK flip-flops 22, 23, and 24 for controlling the output of (21), and 16 or more data counted by the counter 21 to the DPS 0 to logically prevent input to the DS. It is composed of a logic sum gate 25 that outputs an output channel division clock D0ILD_OUT.

Referring to the operation of the timeslot input device of the electronic switch signal detection circuit according to the present invention of the above-described configuration, first, the counter starts counting by the frame synchronization signal. When counted up to 15 at the counter, the ripple carry output is in a "high level" state. This signal is delayed by two JK flip-flops 22 and 23, indicating that the count up to 16 is completed, and this signal is inputted to the JK flip-flop 24 again, and then by the next frame sync signal. It will remain in the "high level" state until cleared. This "high level" signal is input to the OR gate to prevent further clock input into the DSP. When the next frame synchronization signal is input, the output Q of the flip-flop is all at the "level", and the 256 KHz ILD channel division clock signal is input to the DSP as it is through the buffer.

As shown in FIG. 3, when the channel division clock D0ILD inputted to the DS 0 is generated with 16 or more clocks, a carry occurs at the 15th counter carry stage. This is delayed by the J-K flip-flop, which is kept "high level" by the J-K flip-flop to prevent the clock from entering the DSP.

According to the present invention as described above, when the clock is shaken due to an abnormality on the clock supply board or transmission path, there is an effect of preventing the problem that the wrong data is output or the DS itself is not recovered.

Claims (1)

Synchronize the frame sync signal with the channel clock by using the inverted input which inverted the external interrupt input from DSP 0 through the inverter and the channel division clock input to DSP 0 to receive 16 data after the frame sync signal is generated. 4-bit counter for counting 16, multiple JK flip-flops for controlling the output of the counter, and channel division clock input to DS0 to logically prevent the 16 or more data from being entered into the DS. And a logic sum gate for outputting the time slot input apparatus of the electronic switch signal detection circuit.