KR19990004778A - Thin-film optical path to prevent initial tilting of actuator - Google Patents

Abstract

A method of manufacturing a thin film type optical path control device capable of preventing initial tilting of an actuator is disclosed. The method includes forming M × N (M, N is an integer) MOS transistors on a substrate; Forming a first metal layer having a drain pad extending from the drain on top of the transistor; And i) forming a support layer in parallel with the substrate through one side of the first metal layer, the one side of which is in contact with a portion where the step compensation member is formed, and the other side of the first metal layer, through the air gap; Forming a strained layer on the lower electrode, iii) forming an upper electrode on the strained layer, and iii) forming a via contact connecting the drain pad and the lower electrode. Forming an actuator having a forming step. According to the above method, by forming a step compensating member under the support part of the actuator using polysilicon constituting the gate in the manufacture of the transistor embedded in the substrate, the support part is formed high and the support part among the thin films constituting the actuator. Stress imbalance between the remaining portions can be resolved to prevent the actuator from initially tilting.

Description

Method for manufacturing a thin film type optical path control device that can prevent the initial tilt of the actuator

The present invention relates to a method for manufacturing AMA (Actuated Mirror Arrays), which is a thin film type optical path control device, and more particularly, a step compensation member is formed by using a polysilicon constituting a gate when manufacturing a transistor embedded in a substrate. The present invention relates to a method for manufacturing a thin film type optical path control apparatus capable of preventing the initial tilting of an actuator by reducing the step difference of thin films subsequently formed thereon.

In general, an optical path adjusting device capable of forming an image by adjusting a light beam is classified into two types. One type is a direct view type image display device, such as a CRT (Cathode Ray Tube), and the other type is a projection type image display device, such as a liquid crystal display (LCD), a deformable mirror device (DMD), or an AMA. This corresponds to this. Although the CRT device has excellent image quality, the weight and volume of the device increases as the screen is enlarged, and the manufacturing cost thereof increases. In contrast, a liquid crystal display (LCD) has an advantage in that its optical structure is simple and can be formed thin, thereby reducing its weight and volume. However, the liquid crystal display (LCD) has a problem that the efficiency is lowered to have a light efficiency of 1 to 2% due to the polarized light incident, there is a problem that the response speed of the liquid crystal material is slow and the inside is easily overheated.

Accordingly, in order to solve the above problems, an image display device such as a DMD or an AMA has been developed. Currently, AMA devices can achieve 10% or more light efficiency, while DMD devices have about 5% light efficiency. In addition, the AMA device improves the contrast of the image projected on the screen to produce a brighter and clearer image, and is not affected by the polarity of the incident light and does not affect the polarity of the reflected light.

The optical path control device AMA is largely divided into bulk (bulk) and thin film (thin film). The bulk optical path control device is disclosed in US Pat. No. 5,085,497 (issued to Gregory Um, et ai.). The bulk optical path control device cuts a thin layer of multilayer ceramic, mounts a ceramic wafer having a metal electrode therein on an active matrix in which a transistor is built, and then processes it by sawing. This is done by installing a mirror. However, the bulk optical path control device has a problem in that high precision is required in design and manufacture and the response speed of the deformable part is slow. Accordingly, a thin film type optical path control apparatus that can be manufactured using a semiconductor process has been developed.

The thin film type optical path adjusting device is disclosed in patent application No. 97-11058 (name of the invention: a manufacturing method of the thin film type optical path adjusting device) filed by the present applicant.

Figure 1 shows a cross-sectional view of the thin film type optical path control device described in the preceding application.

Referring to FIG. 1, the thin film type optical path adjusting device includes an active matrix 10 and an actuator 40 formed on the active matrix 10.

The active matrix 10 may include a first metal layer 15 and a first metal layer stacked on top of an active matrix 10 in which M × N (M and N are integers) MOS transistors (not shown). 15, the second protective layer 20 stacked on the first protective layer 20, the second metal layer 25 stacked on the first protective layer 20, and the second protective layer stacked on the second metal layer 25 ( 30) and an etch stop layer 35 stacked on the second passivation layer 30. The first metal layer 15 includes a drain pad for transmitting a first signal (image signal). The second metal layer 25 includes a first layer 25a made of titanium (Ti) and a second layer 25b made of titanium nitride (TiN).

The actuator 40 has a support layer 45 having a cross section formed in parallel with the etch stop layer 35 through an air gap 80 on one side of the etch stop layer 35 and having a drain pad formed at the bottom thereof. ), The lower electrode 50 stacked on the support layer 45, the strained layer 55 stacked on the lower electrode 50, the upper electrode 60 stacked on the strained layer 55, and The first metal layer 15 is formed from one side of the strained layer 55 through the lower electrode 50, the support layer 45, the etch stop layer 35, the second protective layer 30, and the first protective layer 20. And a via contact 75 formed to connect the lower electrode 50 and the drain pad in the via hole 70 vertically up to the drain pad of the drain pad.

A stripe 65 is formed on one side of the upper electrode 60 to uniformly operate the upper electrode 60 to prevent diffuse reflection of light incident from the light source.

Hereinafter, a method of manufacturing the thin film type optical path control device will be described with reference to FIGS. 2A to 2D. 2A to 2D, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 2A, a first metal layer 15 is formed on an active matrix 10 having M × N MOS transistors (not shown). Subsequently, the first metal layer 15 is patterned to expose a portion of the gate 11 of the MOS transistor below it. Thus, the first metal layer 15 is connected to the drain 12 and the source 13 of the MOS transistor. The active matrix 10 is made of a semiconductor such as silicon or an insulating material such as glass or alumina (Al ₂ O ₃ ). The first metal layer 15 is made of tungsten (W) and includes a drain pad extending from the drain 12 of the transistor to one side of the supporting layer 45 formed later.

Subsequently, the first protective layer 20 is formed on the first metal layer 15 to protect the active matrix 10 having the transistor embedded therein. The first protective layer 20 is formed by depositing Phosphor-Silicate Glass (PSG) to a thickness of about 8000 kPa using a Chemical Vapor Deposition (CVD) method. The first protective layer 20 prevents damage to the transistor embedded in the active matrix 10 during subsequent processing.

The second metal layer 25 is formed on the first protective layer 20. In order to form the second metal layer 25, first, the first layer 25a is formed by sputtering titanium (Ti) to a thickness of about 300 μs. Subsequently, a second layer 25b having a thickness of about 1200 GPa is formed on the first layer 25a by using titanium nitride (TiN) physical vapor deposition (PVD). Since the light incident from the light source is incident not only on the upper electrode 60, which is a reflective layer, but also on a portion other than the portion where the upper electrode 60 is formed, the second metal layer 25 has a photo current in the active matrix 10. To prevent it from flowing. Subsequently, a portion of the second metal layer 25 in which the via contact 75 is to be formed is etched and patterned in a subsequent process.

The second protective layer 30 is stacked on the second metal layer 25. The second protective layer 30 is formed to a thickness of about 2000 GPa using phosphorus silicate glass (PSG). The second protective layer 30 also prevents the transistor embedded in the active matrix 10 from being damaged during subsequent processing.

An etch stop layer 35 is stacked on the second passivation layer 30. The etch stop layer 35 is formed by depositing nitride to a thickness of about 1000 to 2000 kPa using a low pressure chemical vapor deposition (LPCVD) method. The etch stop layer 35 prevents the active matrix 10 and the second passivation layer 30 from being etched due to a subsequent etching process.

The sacrificial layer 37 is stacked on the etch stop layer 35. The sacrificial layer 37 is formed by depositing a phosphorus silicate glass (PSG) to a thickness of about 2.0 to 3.2 μm by an Atmospheric Pressure Vapor Deposition (APCVD) method. In this case, since the sacrificial layer 37 covers the upper portion of the active matrix 10 in which the transistor is embedded, the surface flatness is very poor. Accordingly, the sacrificial layer 37 may have a thickness of about 1 .6 μm by using spin on glass (SOG) or chemical mechanical polishing (CMP). 37) is planarized by polishing the surface. Subsequently, a portion of the sacrificial layer 37 in which the drain pad of the first metal layer 15 is formed is etched to expose a portion of the etch stop layer 35.

Referring to FIG. 2B, the support layer 45 is stacked on the exposed etch stop layer 35 and on the sacrificial layer 37. The support layer 45 is formed by depositing nitride to a thickness of about 1000 to 3000 kPa using a low pressure chemical vapor deposition (LPCVD) method. Subsequently, a lower electrode 50 is stacked on the support layer 45. The lower electrode 50 is formed so as to have a thickness of about 2000 to 4000 microns by sputtering a metal having electrical conductivity such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta). Subsequently, the lower electrode 50 is iso-cutted to apply an independent signal for each pixel. A first signal (image signal) is applied to the lower electrode 50 through the transistor embedded in the active matrix 10 and the drain pad of the first metal layer 15 from the outside.

A deformation layer 55 made of a piezoelectric material such as PZT or PLZT is stacked on the lower electrode 50. The strained layer 55 is formed to have a thickness of 4000 to 6000 kPa, preferably 4000 kPa using a sol-gel method, a sputtering method, or a chemical vapor deposition method. In addition, the strained layer 55 is thermally transformed by rapid thermal annealing (RTA). The strained layer 55 is deformed by an electric field generated between the upper electrode 60 and the lower electrode 50.

The upper electrode 60 is stacked on the deformation layer 55. The upper electrode 60 is formed to have a thickness of about 2000 to 6000 microns by sputtering a metal having electrical conductivity and reflectivity such as aluminum (Al), silver (Ag), or platinum (Pt). A second signal (bias signal) is applied to the upper electrode 60 through a common electrode line (not shown) from the outside. Since the upper electrode 60 has excellent electrical conductivity and reflectivity, the upper electrode 60 functions not only as a bias electrode but also as a mirror reflecting light incident from a light source.

Subsequently, the upper electrode 60, the strain layer 55, and the lower electrode 50 are sequentially patterned into a predetermined pixel shape from the top of the upper electrode 60. At this time, a stripe 65 is formed at the center of the upper electrode 60 to uniformly operate the upper electrode 60 to prevent diffuse reflection of light incident from the light source.

Referring to FIG. 2C, the strained layer 55, the lower electrode 50, the support layer 45, the etch stop layer 35, the second protective layer 30, and the first protective layer from one side of the strained layer 55. The via holes 20 are sequentially etched to form via holes 70. The via hole 70 is vertically formed from one side of the strained layer 55 to the drain pad of the first metal layer 15. Subsequently, a metal having excellent electrical conductivity such as tungsten (W), aluminum (Al), or titanium (Ti) is deposited using a sputtering method to form a via contact 75. The via contact 75 electrically connects the drain pad and the lower electrode 50 of the first metal layer 15. Therefore, the first signal (image signal) applied from the outside is applied to the lower electrode 50 through the transistor, the drain pad, and the via contact 75 embedded in the active matrix 10. Subsequently, the support layer 45 is patterned into a predetermined pixel shape.

Referring to FIG. 2D, the sacrificial layer 37 is etched using hydrogen fluoride (HF) vapor to form an air gap 80, and then rinsed and dry to perform an AMA device. Complete

In the above-described thin film type optical path adjusting device, the first signal applied from the outside is applied to the lower electrode 50 through the transistor, the drain pad, and the via contact 75 embedded in the active matrix 10. In addition, a second signal is applied to the upper electrode 60 from the outside through the common electrode line to generate an electric field between the upper electrode 60 and the lower electrode 50. By this electric field, the strain layer 55 laminated between the upper electrode 60 and the lower electrode 50 causes deformation. The strained layer 55 contracts in a direction perpendicular to the electric field, and the actuator 40 including the strained layer 55 is bent in a direction opposite to the direction in which the support layer 45 is formed. Therefore, the upper electrode 60 on the actuator 40 also inclines in the same direction. Light incident from the light source is reflected by the upper electrode 60 at a predetermined angle, and then is projected onto the screen to form an image.

However, in the above-described thin film type optical path control device, since the thin films are continuously stacked on top of the transistors starting from the top of the transistor embedded in the active matrix, the thin film constituting the actuator is shown in FIG. 3. The support part (part A of FIG. 3) is formed thicker than the rest part, so stress is concentrated toward the support part A, and the actuator is initially inclined at an angle of θ. That is, since the thin films on the side of the supporting portion A are formed on the drain pad having a lower height than the gate side of the transistor, the thin films on the drain pad side are formed thicker than the remaining portions in the process of stacking the thin films. As a result, the angle of reflection of the upper electrode that reflects light is not constant and the image quality of the image projected on the screen is lowered.

Accordingly, an object of the present invention is to provide a method of manufacturing a thin film type optical path control apparatus capable of preventing the initial tilt of an actuator by relieving stress in the thin films constituting the actuator by forming a step compensating member under the drain pad. There is.

1 is a cross-sectional view of a thin film type optical path control device previously applied by the present applicant.

2A to 2D are manufacturing process diagrams of the apparatus shown in FIG. 1.

3 is a cross-sectional view for explaining the initial tilt of the actuator of the apparatus shown in FIG.

4 is a plan view of a thin film type optical path control apparatus according to the present invention.

FIG. 5 is a cross-sectional view taken along line A′A ′ of the apparatus shown in FIG. 4.

5A to 5E are manufacturing process diagrams of the apparatus shown in FIG. 4.

<Explanation of symbols for main parts of drawing>

100 semiconductor substrate 105 drain

110: source 115: gate

117 step difference compensation member 120 primary oxide film

125: secondary oxide film 155: first metal layer

160: first protective layer 165: second metal layer

170: second protective layer 175: etch stop layer

185: support layer 190: lower electrode

195 strain layer 200 upper electrode

205 Actuator 210 Beer Hole

215: Beer contact 220: Stripe

In order to achieve the above object, the present invention provides a method of forming an M × N (M, N is integer) MOS transistor on a substrate, and forming a first metal layer having a drain pad extending from a drain on top of the transistor. It provides a method of manufacturing a thin film type optical path control device comprising the step and forming an actuator on the first metal layer and the substrate. The forming of the transistor may include forming a first oxide layer on a substrate to separate an active region and a field region, forming a gate on the active region, and a step compensation member on one side of the field region. Forming a source and forming a source and a drain at both sides of the gate. The forming of the actuator may include: i) forming a support layer parallel to the substrate through one side of the first metal layer, the one side of which is in contact with a portion where the step compensation member is formed, and the other side of the first metal layer; Forming a lower electrode on top of the support layer, iii) forming a strained layer on top of the lower electrode, iii) forming an upper electrode on top of the strained layer, and iii) from one side of the strained layer And forming a via contact connecting the drain pad and the lower electrode to the drain pad of the first metal layer.

In the above-described thin film type optical path control apparatus according to the present invention, the first signal (image signal) transmitted from the outside is applied to the lower electrode through the transistor embedded in the substrate, the drain pad of the first metal layer, and the via contact. At the same time, a second signal (bias signal) is applied to the upper electrode through the common electrode line from the outside to generate an electric field between the upper electrode and the lower electrode. Due to this electric field, the strain layer formed between the upper electrode and the lower electrode causes deformation. The strained layer contracts in a direction perpendicular to the electric field, and the actuator including the strained layer is bent at a predetermined angle. The upper electrode, which also functions as a mirror that reflects light, is formed on the actuator and is inclined with the actuator. Accordingly, the upper electrode reflects the light incident from the light source at a predetermined angle, and the reflected light passes through the slit to form an image on the screen.

According to the manufacturing method of the thin film type optical path control apparatus according to the present invention, by using a polysilicon constituting a gate when manufacturing a transistor embedded in a substrate to form a step compensation member under the support of the actuator, the support portion is formed high The stress imbalance between the support and the remaining portions of the thin films constituting the actuator can be eliminated to prevent the actuator from initially inclining. Accordingly, the image quality of the image projected on the screen can be improved by making the reflection angle of the upper electrode reflecting the light incident from the light source uniform.

Hereinafter, a manufacturing method of a thin film type optical path control apparatus according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view of a thin film type optical path control device according to the present invention, Figure 5 is a cross-sectional view taken along the line AA 'of the device shown in FIG.

4 and 5, the thin film type optical path control apparatus includes a substrate 100 and an actuator 205 formed on the substrate 100.

The substrate 100 may include a first oxide layer 120 for dividing the substrate 100 into an active region and a field region, and a gate 115 and a source 110 in the active region. And M × N MOS transistors formed with a drain 105. In addition, the substrate 100 may include a first metal layer 155 stacked on the MOS transistor, a first protective layer 160 stacked on the first metal layer, and a first protective layer stacked on the first metal layer. The second metal layer 165 includes a second protective layer 170 stacked on the second metal layer, and an etch stop layer 175 stacked on the second protective layer.

The first metal layer 155 extends from the drain 105 of the transistor and includes a drain pad for transmitting a first signal (image signal), and the transistor is disposed below the drain pad of the first metal layer 155. A step compensation member 117 made of polysilicon, which is the same material as the gate 115, is formed. The second metal layer 165 includes a first layer 165a stacked using titanium (Ti) metal and a second layer 165b stacked using titanium nitride (TiN).

The actuator 205 contacts one side of the etch stop layer 175 where the drain pad of the first metal layer 155 is formed and the other side is formed in parallel with the substrate 100 via the air gap 225. A support layer 185 having a cross section, a lower electrode 190 stacked on top of the support layer 185, a strained layer 195 stacked on top of the lower electrode 190, and an upper portion of the strained layer 195. The stacked upper electrode 200 and the strained layer 195, the lower electrode 190, the support layer 185, the etch stop layer 175, the second passivation layer 170, and the first side from one side of the strained layer 195. 1 The via contact 215 formed to electrically connect the lower electrode 190 and the drain pad to the via hole 210 formed perpendicularly to the drain pad of the first metal layer 155 through the protective layer 160. It includes.

The support layer 185 functions as a membrane supporting the actuator of the thin film type optical path adjusting device described in the previous application. One side of the upper electrode 200 is formed with a stripe 220 to uniformly operate the upper electrode 200 to prevent diffuse reflection of the incident light beam.

In addition, referring to FIG. 4, one side of the plane of the support layer 185 has a concave portion having a rectangular shape at its center, and the concave portion is formed in a shape that is stepped toward both edges. The other side of the plane of the support layer 185 has a rectangular protrusion that narrows stepwise toward the central portion corresponding to the concave portion. Therefore, the concave portion of the support layer of the actuator adjacent to the concave portion of the support layer 185 is fitted, and the rectangular projection is fitted into the concave portion of the support layer of the adjacent actuator.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the drawings.

6A to 6E are manufacturing process diagrams of the apparatus shown in FIG. 6A to 6E, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 6A, after preparing a substrate 100, which is a substrate made of a semiconductor such as silicon (Si) or made of an insulating material such as glass or alumina (Al ₂ O ₃ ), conventional device isolation is performed. A first oxide film 120 is formed on the substrate 100 to distinguish between an active region and a field region using a process, for example, a local oxidation of silicon (LOCOS) method. Subsequently, a gate 115 made of a conductive material such as polysilicon doped with impurities is formed on the active region. At the same time, a polysilicon film is deposited on one side of the field region in which the primary oxide film 120 is formed by using a chemical vapor deposition method, and then the polysilicon film is patterned to simultaneously form the step compensation member 117. The step compensating member 117 is formed to be spaced apart from the portion where the drain 105 of the transistor is to be formed in consideration of the position where the support portion of the actuator 205 to be formed later is formed. Subsequently, the source 110 and the drain 105 are formed by the ion implantation process, thereby forming M × N (M, N is an integer) MOS transistors. Subsequently, after the secondary oxide film 125 is formed on the transistor and on the step compensation member 117 by a conventional method, the second oxide film 125 is patterned to form the gate 115 and the source. Openings exposing the top of one side of the 110 and the drain 105, respectively. Subsequently, after the first metal layer 155 is formed on the resultant product in which the openings are formed, the first metal layer 155 is patterned to expose portions of the gate 115 of the MOS transistor below it. Accordingly, the first metal layer 155 is connected to the drain 105 and the source 110 of the MOS transistor and extends over the second oxide film 125. The first metal layer 155 is formed of tungsten, titanium, or the like, and includes a drain pad extending from the drain 105 of the transistor to the top of the step compensation member 117. The first signal (image signal) applied from the outside is transferred to the lower electrode 190 through the MOS transistor embedded in the substrate 100 and the drain pad of the first metal layer 155.

When the secondary oxide film 125 is formed as described above, a portion of the secondary oxide film 125 in which the step compensation member 117 is formed at the lower portion thereof protrudes slightly upward. In the above, the step compensating member 117 is formed using the same material as that of the constituent material of the gate 115 to shorten the manufacturing process, but the step compensating member 117 is formed of a rigid material such as metal or nitride. It can be formed using a material.

Subsequently, referring to FIG. 6B, the first protective layer 160 is formed on the first metal layer 155 to protect the substrate 100 in which the MOS transistor is embedded.

The first passivation layer 160 is formed to have a thickness of about 8000 GPa by using a vapor deposition method (CVD) of phosphorus silicate glass (PSG). A portion of the first passivation layer 160 in which the step compensation member 117 is formed may protrude slightly upward in the same manner as the second oxide film 125. The first protective layer 160 prevents damage to the transistor embedded in the substrate 100 under the influence of a subsequent process.

The second metal layer 165 is formed on the first passivation layer 160. The second metal layer 165 is formed by sputtering titanium to form a first layer 165a having a thickness of about 300 kPa, and then using titanium nitride on the first layer 165a by using a physical vapor deposition method (PVD). This is completed by forming the second layer 165b having a thickness of about 1200 GPa. The second metal layer 165 blocks light incident from the light source from being incident on not only the upper electrode 200, which is a reflective layer, but also a portion other than the portion where the upper electrode 200 is formed, so that photocurrent flows to the substrate 100. Prevent the device from malfunctioning. Subsequently, an opening is formed in the second metal layer 165 by patterning a portion of the second metal layer 165 where the via contact 215 is to be formed in a subsequent process.

The second passivation layer 170 is stacked on the second metal layer 165. The second protective layer 170 is formed to have a thickness of about 2000 GPa using in-silicate glass (PSG). The second protective layer 170 prevents damage to the transistors embedded in the substrate 100 and the results formed on the substrate 100 during subsequent processing.

An etch stop layer 175 is stacked on the second passivation layer 170. The etch stop layer 175 prevents the substrate 100 and the second passivation layer 170 from being etched due to the subsequent etching process. The etch stop layer 175 is formed by depositing nitride (Si ₃ N ₄ ) by a low pressure chemical vapor deposition (LPCVD) method to have a thickness of about 1000 ~ 2000Å.

The sacrificial layer 180 is stacked on the etch stop layer 175. The sacrificial layer 180 is formed by depositing phosphorus silicate glass (PSG) to a thickness of about 2.0 to 3.2 μm by an atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 180 covers the upper portion of the substrate 100 in which the transistor is embedded, the flatness of the surface thereof is very poor. Therefore, by using a spin on glass (SOG) method or a chemical mechanical polishing (CMP) method by polishing the surface of the sacrificial layer 180 so that the sacrificial layer 180 to a thickness of about 1.6㎛ Planarize. Subsequently, a portion of the sacrificial layer 180 in which the opening of the second metal layer 165 is formed is etched to expose a portion of the etch stop layer 175. Since the step compensation member 117 is formed under the exposed portion of the etch stop layer 175, the step may be significantly reduced compared to a conventional apparatus.

Referring to FIG. 6C, the support layer 185 is stacked on the exposed etch stop layer 175 and on the sacrificial layer 180. The support layer 185 is formed to have a thickness of about 0.1 to 1.0 μm using low pressure chemical vapor deposition (LPCVD). Subsequently, a lower electrode 190 is stacked on the support layer 185. The lower electrode 190 is formed to have a thickness of about 0.01 to 1.0 μm by sputtering a metal having electrical conductivity such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta). do. Subsequently, in order to apply an independent first signal for each pixel, the lower electrode 190 is iso-cutted in a direction parallel to the direction in which the actuator 205 is formed. A first signal (image signal) is applied to the lower electrode 190 through a transistor embedded in the substrate 100 and a drain pad of the first metal layer 155 from the outside.

A deformation layer 195 made of a piezoelectric material of ZnO, PZT, or PLZT is stacked on the lower electrode 190. The strained layer 195 is formed to have a thickness of about 0.1 to 1.0 탆, preferably about 4000 kPa, using a sol-gel method, a sputtering method, or a chemical vapor deposition method. In addition, the piezoelectric material constituting the strained layer 190 is subjected to heat treatment by rapid thermal annealing (RTA) to phase change and then polarize. The deformation layer 190 causes deformation in a direction perpendicular to the electric field by an electric field generated between the upper electrode 200 and the lower electrode 190.

The upper electrode 200 is formed on the deformation layer 190. The upper electrode 200 is formed to have a thickness of about 0.01 to 1.0 μm by sputtering a metal having electrical conductivity and reflectivity such as aluminum (Al), silver (Ag), or platinum (Pt). A second signal (bias signal) is applied to the upper electrode 200 through a common electrode line (not shown) from the outside. Since the upper electrode 200 has excellent electrical conductivity and reflectivity, the upper electrode 200 reflects light incident from a light source (not shown) as well as a function of a bias electrode generating an electric field between the upper electrode 200 and the lower electrode 190. It also functions as a mirror.

Subsequently, the upper electrode 200, the strain layer 195, and the lower electrode 190 are patterned to have a predetermined pixel shape sequentially from the top of the upper electrode 200. At this time, a stripe 220 is formed on one side of the upper electrode 200 to uniformly operate the upper electrode 200 to prevent diffuse reflection of light incident from the light source.

Referring to FIG. 6D, the strained layer 195, the lower electrode 190, the support layer 185, the etch stop layer 175, the second protective layer 170, and the first protective layer are formed from one side of the strained layer 195. The via holes are sequentially etched to form the via holes 210. Therefore, the via hole 210 is vertically formed from one side of the strained layer 195 to the drain pad of the first metal layer 155 through the opening of the second metal layer 165. Subsequently, a metal having electrical conductivity such as tungsten (W), aluminum (Al), or titanium (Ti) is deposited using a sputtering method to form a via contact 215. The via contact 215 electrically connects the drain pad of the first metal layer 155 and the lower electrode 190. Therefore, the first signal applied from the outside is applied to the lower electrode 190 through the transistor embedded in the substrate 100, the drain pad of the first metal layer 155, and the via contact 215. The support layer 185 is patterned to have a predetermined pixel shape.

Referring to FIG. 6E, the sacrificial layer 180 is etched using hydrogen fluoride (HF) vapor to form an air gap 225 at the position of the sacrificial layer 180, followed by rinse and dry. ) To complete the thin film type AMA device.

After completing the M × N thin film type AMA devices as described above, the substrate 100 may be sputtered or evaporated using a metal such as chromium (Cr), nickel (Ni), or gold (Au). It is deposited at the bottom of the to form an ohmic contact (not shown). Then, photolithography is provided in preparation for bonding a Tape Carrier Package (TCP) (not shown) for applying a second signal to a subsequent upper electrode 200 and a first signal to the lower electrode 190. The substrate 100 is cut to a predetermined thickness using a method. Subsequently, a photoresist layer (not shown) is formed on the pad of the AMA panel so that the pad of the AMA panel (not shown) has a sufficient height during TCP bonding. Subsequently, a portion of the photoresist layer on which the pad is formed is patterned to expose the pad of the AMA panel. Subsequently, the photoresist layer is etched using a dry etching method or a wet etching method, and the substrate 100 is completely cut into a predetermined shape, and then the pad of the AMA panel and the TCP pad are cut into an anisotropic conductive film (ACF) ( (Not shown) to complete the manufacture of the thin film AMA module.

In the above-described thin film type optical path control device according to the present invention, the first signal (image signal) transmitted through the pad of TCP and the pad of AMA panel is a transistor embedded in the substrate 100 and the drain of the first metal layer 155. The pad and via contact 215 is applied to the lower electrode 190. At the same time, a second signal (bias signal) is applied to the upper electrode 200 through the common electrode line from the outside, thereby generating an electric field between the upper electrode 200 and the lower electrode 190. Due to this electric field, the deformation layer 195 formed between the upper electrode 200 and the lower electrode 190 causes deformation. The strained layer 195 contracts in a direction perpendicular to the electric field, whereby the actuator 205 including the strained layer 195 is bent at a predetermined angle. The upper electrode 200, which also functions as a mirror that reflects light, is formed on the actuator 205 and is inclined together with the actuator 205. Accordingly, the upper electrode 200 reflects the light incident from the light source at a predetermined angle, and the reflected light passes through the slit to form an image on the screen.

According to the manufacturing method of the thin film type optical path control apparatus according to the present invention, by using the polysilicon constituting the gate when manufacturing the transistor embedded in the substrate to form a step compensation member in the lower portion of the support of the actuator, the support portion is formed high The stress imbalance between the support and the remaining portions of the thin films constituting the actuator can be eliminated to prevent the actuator from initially inclining. Accordingly, the image quality of the image projected on the screen can be improved by making the reflection angle of the upper electrode reflecting the light incident from the light source uniform.

Although the preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not limited thereto and may be improved or modified by those skilled in the art within the scope of the technical idea of the present invention.

Claims (4)

Forming a primary oxide film on the substrate to separate the active region and the field region, forming a gate on the active region, and forming a step compensation member on one side of the field region, and the gate Forming M × N (M, N is an integer) MOS transistors including forming a source and a drain on both sides of the substrate; Forming a first metal layer having a drain pad extending from the drain on top of the transistor; And i) forming a support layer parallel to the substrate with one side contacting a portion of the first metal layer on which the step compensation member is formed and the other side through an air gap; ii) forming a lower electrode on the support layer Iii) forming a strained layer on top of the lower electrode, iii) forming an upper electrode on top of the strained layer, and iii) the drain pad of the first metal layer from one side of the strained layer. Forming an actuator having a step of forming a via contact connecting the drain pad and the lower electrode until the method of manufacturing a thin film type optical path control device. The method of claim 1, wherein the forming of the gate on the upper portion of the active region and the forming of the step compensating member on the upper side of the field region are performed using the same material. Way. 3. The method of claim 2, wherein the forming of the gate on the upper portion of the active region and the forming of the step compensation member on the upper portion of the field region are performed using polysilicon. 4. Way. The method of claim 1, wherein the forming of the gate on the upper portion of the active region and the forming of the step compensating member on the upper portion of the field region are performed at the same time.