KR19990003915A - Cylindrical Charge Storage Electrode Formation Method of Semiconductor Device - Google Patents
Cylindrical Charge Storage Electrode Formation Method of Semiconductor Device Download PDFInfo
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- KR19990003915A KR19990003915A KR1019970027878A KR19970027878A KR19990003915A KR 19990003915 A KR19990003915 A KR 19990003915A KR 1019970027878 A KR1019970027878 A KR 1019970027878A KR 19970027878 A KR19970027878 A KR 19970027878A KR 19990003915 A KR19990003915 A KR 19990003915A
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- forming
- charge storage
- storage electrode
- sacrificial oxide
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 230000015572 biosynthetic process Effects 0.000 title claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 125000006850 spacer group Chemical group 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000002161 passivation Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Semiconductor Memories (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
본 발명은 반도체 제조 분야에 관한 것임.The present invention relates to the field of semiconductor manufacturing.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
본 발명은 측벽 스페이서 형성시 그 끝 부분이 취약애지지 않는 반도체 장치의 전하저장 전극 형성방법을 제공하고자 함.An object of the present invention is to provide a method for forming a charge storage electrode of a semiconductor device, the end portion of which is not weak when forming sidewall spacers.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
본 발명은 희생 산화막의 선택적 식각시 CF계 가스를 사용하여 식각된 측벽의 패시베이션이 강화되는 조건을 형성하여 85° 이하의 경사를 가지는 패턴을 형성하고, 이 패턴 측벽에 폴리실리콘막 스페이서를 형성함으로써 스페이서 끝 부분의 취약 부위를 제거함.The present invention forms a pattern having an inclination of 85 ° or less by forming a condition that the passivation of the sidewall etched using CF-based gas is enhanced during selective etching of the sacrificial oxide film, and forming a polysilicon film spacer on the pattern sidewall. Removes weak spots on spacer ends.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 장치의 실린더형 전하저장 전극 형성에 이용됨.Used to form cylindrical charge storage electrodes in semiconductor devices.
Description
본 발명은 반도체 제조 분야에 관한 것으로, 특히 64M DRAM급 이상의 반도체 메모리 장치에 적용되는 실린더 구조의 전하저장 전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method of forming a charge storage electrode having a cylindrical structure applied to a semiconductor memory device of 64M DRAM or higher.
이하, 첨부된 도면 도 1a 내지 도 1e를 참조하여 종래 기술 및 그 문제점을 살펴본다.Hereinafter, with reference to the accompanying drawings, Figures 1a to 1e looks at the prior art and its problems.
먼저, 도 1a에 도시된 바와 같이 소정의 하부층 공정을 마치고 콘택홀을 가진 층간 절연막(11)이 형성된 실리콘 기판(10) 상에 폴리실리콘막(12) 및 희생 산화막(13)을 차례로 증착한다. 계속하여, 그 상부에 전하저장 전극 패턴 형성을 위한 포토레지스트 패턴(14)을 형성한다.First, as shown in FIG. 1A, a polysilicon film 12 and a sacrificial oxide film 13 are sequentially deposited on a silicon substrate 10 on which an interlayer insulating film 11 having contact holes is formed after completing a predetermined lower layer process. Subsequently, a photoresist pattern 14 for forming a charge storage electrode pattern is formed thereon.
이어서, 도 1b에 도시된 바와 같이 포토레지스트 패턴(14)를 식각 장벽으로하여 희생 산화막(13) 및 폴리실리콘막(12)을 선택적 식각한 다음, 포토레지스트 패턴(14)을 제거한다.Subsequently, as illustrated in FIG. 1B, the sacrificial oxide film 13 and the polysilicon film 12 are selectively etched using the photoresist pattern 14 as an etch barrier, and then the photoresist pattern 14 is removed.
계속하여, 도 1c에 도시된 바와 같이 전체구조 상부에 다시 측벽 스페이서 형성을 위한 폴리실리콘막(15)을 증착한다.Subsequently, as shown in FIG. 1C, a polysilicon film 15 for forming sidewall spacers is again deposited on the entire structure.
다음으로, 도 1d에 도시된 바와 같이 폴리실리콘막(15)을 전면성 식각하여 폴리실리콘막 스페이서(15a)를 형성한다. 여기서, 전면성 식각은 과도 식각을 필요로 하므로 폴리실리콘막 스페이서(15a)의 끝 부분이 취약하게 형성된다. 이러한 취약 부위(A)는 폴리실리콘막 스페이서(15a)의 끝 부분에서 이온 타격 성향이 약하기 때문에 형성된 것이며, 이후 캐패시터의 붕괴 전압을 떨어뜨림으로써 반도체 장치의 신뢰도를 저하시킨다.Next, as illustrated in FIG. 1D, the polysilicon film 15 is etched entirely to form the polysilicon film spacer 15a. In this case, since the front side etching requires excessive etching, the end portion of the polysilicon layer spacer 15a is weakly formed. The weak spots A are formed because the ion bombardment tends to be weak at the ends of the polysilicon film spacers 15a, thereby lowering the collapse voltage of the capacitor, thereby lowering the reliability of the semiconductor device.
끝으로, 도 1e에 도시된 바와 같이 희생 산화막(13)을 습식 식각 방식으로 제거한다. 이때, 폴리실리콘막 스페이서(15a)의 끝 부분의 취약 부위가 부러지게 되어 파티클의 원인이 되거나, 캐패시터의 정전용량을 저하시키는 요인이 된다.Finally, as shown in FIG. 1E, the sacrificial oxide layer 13 is removed by a wet etching method. At this time, the fragile portion of the end portion of the polysilicon film spacer 15a is broken, which may cause particles or reduce the capacitance of the capacitor.
본 발명은 측벽 스페이서 형성시 그 끝부분이 취약해 지지 않는 반도체 장치의 전하저장 전극 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a charge storage electrode of a semiconductor device in which end portions thereof are not weak when forming sidewall spacers.
도 1a 내지 도 1e는 종래 기술에 따른 실린더형 전하저장 전극 형성 공정도.1a to 1e is a process diagram of forming a cylindrical charge storage electrode according to the prior art.
도 2a 내지 도 2e는 본 발명의 일실시예에 따른 실린더형 전하저장 전극 형성 공정도.2a to 2e is a flow chart of forming a cylindrical charge storage electrode according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
20 : 실리콘 기판 21 : 층간 절연막20 silicon substrate 21 interlayer insulating film
22,25 : 폴리실리콘막 23 : 희생 산화막22,25 polysilicon film 23 sacrificial oxide film
24 : 포토레지스트 패턴 25a : 폴리실리콘막 스페이서24 photoresist pattern 25a polysilicon film spacer
상기와 같은 목적을 달성하기 위하여 본 발명의 전하저장 전극 형성방법은 소정의 하부층 및 층간 절연막이 형성된 전체구조 상부에 반도체 기판에 콘택되는 폴리실리콘막 및 희생 산화막을 차례로 형성하는 제1 단계, 전하저장 전극 형성을 위한 식각 마스크를 사용하여 상기 희생 산화막 및 상기 폴리실리콘막을 선택적 식각하되, 식각된 측벽의 경사가 85°를 넘지 않도록 하는 제2 단계, 상기 측벽 부위에 폴리실리콘막 스페이서를 형성하는 제3 단계 및 상기 희생 산화막을 제거하는 제4 단계를 포함하여 이루어진다.In order to achieve the above object, the charge storage electrode forming method of the present invention includes a first step of sequentially forming a polysilicon film and a sacrificial oxide film contacted to a semiconductor substrate on an entire structure on which a predetermined lower layer and an interlayer insulating film are formed. A second step of selectively etching the sacrificial oxide layer and the polysilicon layer using an etching mask for forming an electrode, so that the inclination of the etched sidewall does not exceed 85 °, and a third layer of forming the polysilicon layer spacer on the sidewall part And a fourth step of removing the sacrificial oxide film.
이하, 첨부된 도면 도 2a 내지 도 2e를 참조하여 본 발명의 일실시예를 상술한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings, FIGS. 2A to 2E.
먼저, 도 2a에 도시된 바와 같이 소정의 하부층 공정을 마치고 콘택홀을 가진 층간 절연막(21)이 형성된 실리콘 기판(20) 상에 폴리실리콘막(22) 및 희생 산화막(23)을 차례로 증착한다. 계속하여, 그 상부에 전하저장 전극 패턴 형성을 위한 포토레지스트 패턴(24)을 형성한다.First, as shown in FIG. 2A, the polysilicon layer 22 and the sacrificial oxide layer 23 are sequentially deposited on the silicon substrate 20 on which the interlayer insulating layer 21 having contact holes is formed after completing a predetermined lower layer process. Subsequently, a photoresist pattern 24 for forming a charge storage electrode pattern is formed thereon.
다음으로, 도 2b에 도시된 바와 같이 포토레지스트 패턴(24)를 식각 장벽으로하여 희생 산화막(23) 및 폴리실리콘막(22)을 차레로 선택적 식각한 다음, 포토레지스트 패턴(24)을 제거한다. 이때, 상기한 선택적 식각은 CF4, CHF3, CH2F2, CH3F, C2F6, C3H, C4F8등의 CF계 가스를 주 식각 가스로하여 측벽의 패시베이션이 강화되는 조건으로 희생 산화막(23)을 식각하여 85° 이하의 완만한 경사면을 확보하고, 계속하여 폴리실리콘막(22)을 식각한다. 상기한 선택적 식각은 상기한 주 식각 가스 외에 Ar 가스를 더 첨가하여 사용할 수도 있다.Next, as shown in FIG. 2B, the sacrificial oxide layer 23 and the polysilicon layer 22 are selectively etched sequentially using the photoresist pattern 24 as an etch barrier, and then the photoresist pattern 24 is removed. . At this time, the selective etching is CF 4 , CHF 3 , CH 2 F 2 , CH 3 F, C 2 F 6 , C 3 H, C 4 F 8 and the like as the main etching gas, the sidewall passivation is enhanced The sacrificial oxide film 23 is etched under such a condition that a gentle slope of 85 ° or less is secured, and then the polysilicon film 22 is etched. The selective etching may be used by further adding Ar gas in addition to the main etching gas.
이어서, 도 2c에 도시된 바와 같이 전체구조 상부에 다시 측벽 스페이서 형성을 위한 폴리실리콘막(25)을 증착한다.Subsequently, as shown in FIG. 2C, a polysilicon film 25 for forming sidewall spacers is deposited on the entire structure again.
다음으로, 도 2d에 도시된 바와 같이 폴리실리콘막(25)을 전면성 식각하여 폴리실리콘막 스페이서(25a)를 형성한다. 이때, 완만한 경사의 측벽 프러파일(profile)에 의해 충분한 이온 타격(ion bombardment)이 폴리실리콘막 스페이서(25a)의 끝 부분에 전달되어 종래 경우와 달리 취약 부위가 발생하지 않게 된다.Next, as shown in FIG. 2D, the polysilicon film 25 is etched entirely to form the polysilicon film spacer 25a. At this time, sufficient ion bombardment is transmitted to the end portion of the polysilicon membrane spacer 25a by the gentle inclined sidewall profile so that no weak spots occur.
계속하여, 도 2e에 도시된 바와 같이 희생 산화막(13)을 습식 식각 방식으로 제거한다Subsequently, as shown in FIG. 2E, the sacrificial oxide film 13 is removed by a wet etching method.
상기한 바와 같이 본 발명은 종래의 공정 단계를 크게 변경시키지 않으면서 측벽 스페이서의 첨점을 발생시키지 않는 실린더형 전하저장 전극을 형성할 수 있다.As described above, the present invention can form a cylindrical charge storage electrode that does not generate a peak of the sidewall spacer without significantly changing the conventional process steps.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기한 바와 같이 본 발명은 종래의 공정 단계를 크게 변경시키지 않으면서 측벽 스페이서의 끝 부분에서 취약 부위가 발생되지 않는 실린더형 전하저장 전극을 형성할 수 있다. 또한, 취약 부위를 방지함으로써 반도체 장치의 신뢰도 및 제조 수율의 향상을 기대할 수 있다.As described above, the present invention can form a cylindrical charge storage electrode in which a weak portion does not occur at the end of the sidewall spacer without significantly changing the conventional process steps. In addition, it is expected to improve the reliability and manufacturing yield of the semiconductor device by preventing the weak spots.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019970027878A KR100482739B1 (en) | 1997-06-26 | 1997-06-26 | Method of forming cylinder type charge storage electrode of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019970027878A KR100482739B1 (en) | 1997-06-26 | 1997-06-26 | Method of forming cylinder type charge storage electrode of semiconductor device |
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| KR19990003915A true KR19990003915A (en) | 1999-01-15 |
| KR100482739B1 KR100482739B1 (en) | 2006-05-12 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100466982B1 (en) * | 2002-03-11 | 2005-01-24 | 삼성전자주식회사 | Semiconductor device having capacitors and method of fabricating the same |
| KR100557646B1 (en) * | 1999-12-31 | 2006-03-10 | 주식회사 하이닉스반도체 | A method for forming a storage node of semiconductor device |
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1997
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100557646B1 (en) * | 1999-12-31 | 2006-03-10 | 주식회사 하이닉스반도체 | A method for forming a storage node of semiconductor device |
| KR100466982B1 (en) * | 2002-03-11 | 2005-01-24 | 삼성전자주식회사 | Semiconductor device having capacitors and method of fabricating the same |
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| Publication number | Publication date |
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| KR100482739B1 (en) | 2006-05-12 |
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