KR19980055960A - Bit line formation method of semiconductor device - Google Patents
Bit line formation method of semiconductor device Download PDFInfo
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- KR19980055960A KR19980055960A KR1019960075197A KR19960075197A KR19980055960A KR 19980055960 A KR19980055960 A KR 19980055960A KR 1019960075197 A KR1019960075197 A KR 1019960075197A KR 19960075197 A KR19960075197 A KR 19960075197A KR 19980055960 A KR19980055960 A KR 19980055960A
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 title description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 35
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 230000008569 process Effects 0.000 claims description 14
- 229910052721 tungsten Inorganic materials 0.000 claims description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 10
- 239000010937 tungsten Substances 0.000 claims description 10
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 8
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 229910006774 Si—W Inorganic materials 0.000 abstract 1
- 230000003993 interaction Effects 0.000 abstract 1
- 239000010936 titanium Substances 0.000 description 14
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- AWXLLPFZAKTUCQ-UHFFFAOYSA-N [Sn].[W] Chemical compound [Sn].[W] AWXLLPFZAKTUCQ-UHFFFAOYSA-N 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 종래의 Si/Ti/제 1 TiN/W/제 2 TiN 적층 구조의 비트 라인에서 제 1 TiN층 위에 WSiX층을 미리 첨가함으로써 Si와 W간의 상호 확산에 의해 발생하는 열처리로 인한 접합(junction) 파괴나 누설 전류 등의 신뢰성 저하를 방지할 수 있는 반도체 소자의 비트 라인 형성 방법이 제시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a Si-W interaction is achieved by adding a WSi X layer on a first TiN layer in advance in a bit line of a conventional Si / Ti / first TiN / W / second TiN stacked structure. Disclosed is a method of forming a bit line of a semiconductor device, which can prevent a decrease in reliability such as a junction breakdown or leakage current due to heat treatment caused by diffusion.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 비트 라인(bit line) 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a bit line of a semiconductor device.
종래의 반도체 소자의 비트 라인 형성 방법에서의 문제점을 도 1 을 이용하여 설명하면 다음과 같다. 도 1 은 종래의 반도체 소자의 비트 라인 형성 방법을 설명하기 위해 도시한 소자의 단면도이다. 도시된 바와 같이 반도체 기판(11)의 상부에 절연막(12)을 형성하고, 콘택 영역을 확정한 후 절연막(12)의 선택된 영역을 식각하여 콘택 홀을 형성한다. 형성된 콘택 홀을 포함한 전체 구조 상부에 Ti층(13), 제 1 TiN층(14)을 순차적으로 형성한 후 그 상부에 텅스텐(W)(15) 및 반사 억제층인 제 2 TiN층(16)을 증착한다. 그리고, 제 2 TiN층(16), 텅스텐(15), 제 1 TiN층(14) 및 Ti층(13)의 선택된 영역을 순차적으로 제거하여 비트 라인을 형성한다.Problems in the conventional method for forming a bit line of a semiconductor device will be described below with reference to FIG. 1. 1 is a cross-sectional view showing a device for explaining a bit line forming method of a conventional semiconductor device. As shown in the drawing, an insulating film 12 is formed on the semiconductor substrate 11, a contact region is determined, and then a selected region of the insulating film 12 is etched to form a contact hole. The Ti layer 13 and the first TiN layer 14 are sequentially formed on the entire structure including the formed contact hole, and then the tungsten (W) 15 and the second TiN layer 16, which is a reflection suppression layer, are formed thereon. Deposit. The selected regions of the second TiN layer 16, tungsten 15, first TiN layer 14, and Ti layer 13 are sequentially removed to form a bit line.
이와 같이 종래의 비트 라인은 Si/Ti/제 1 TiN/W/제 2 TiN의 적층 구조로 이루어져 있다. 텅스텐을 이용한 비트 라인은 텅스텐 폴리사이드(W-polycide) 비트 라인에 비하여 낮은 면저항 특성과 n+, p+지역의 오옴익 콘택 형성의 용이성 등의 장점이 있으나 콘택 형성 후 반복되는 고온 열처리로 인하여 도판트(dopant)의 재배열 및 티타늄 실리사이드(TiSi)층의 뭉침(agglomeration) 현상 등이 발생하여 Si과 W이 상호 확산하여 콘택 저항의 증가와 접합(junction) 파괴 가능성이 존재하게 된다.As such, the conventional bit line has a stacked structure of Si / Ti / first TiN / W / second TiN. Bit line using tungsten has advantages such as low sheet resistance and ease of ohmic contact formation in n + and p + areas compared to tungsten polycide bit line, but due to repeated high temperature heat treatment after contact formation, The rearrangement of the dopant and the agglomeration of the titanium silicide (TiSi) layer occur, which causes Si and W to diffuse to each other, thereby increasing the contact resistance and the possibility of junction breakdown.
따라서, 본 발명은 종래의 Si/Ti/제 1 TiN/W/제 2 TiN의 적층 구조에서 발생하는 Si과 W과의 상호 확산 가능성을 미연에 방지할 수 있는 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method capable of preventing the possibility of mutual diffusion between Si and W occurring in a conventional laminated structure of Si / Ti / first TiN / W / second TiN.
상술한 목적을 달성하기 위한 본 발명은 반도체 기판 상부에 절연막을 형성하고 콘택 영역을 확정한 후 절연막의 선택된 영역을 식각하여 콘택 홀을 형성하는 단계와, 상기 콘택 홀을 포함한 전체 구조 상부에 Ti층 및 제 1 TiN층을 순차적으로 형성하는 단계와, 상기 Ti층 및 제 1 TiN층을 증착한 후 열처리 공정을 실시하는 단계와, 상기 열처리 공정을 수행한 후 제 1 TiN층의 상부에 텅스텐 실리사이드를 증착하는 단계와, 상기 텅스텐 실리사이드 상부에 텅스텐 및 제 2 TiN층을 증착한 후 평탄화 공정을 수행하는 단계와, 상기 평탄화 공정을 수행한 후 제 2 TiN층, 텅스텐, 텅스텐 실리사이드, 제 1 TiN층 및 Ti층의 선택된 영역을 순차적으로 제거하여 비트 라인을 형성하는 단계로 이루어진 것을 특징으로 한다.The present invention for achieving the above object is to form an insulating film on the semiconductor substrate, and to determine the contact region and to form a contact hole by etching the selected region of the insulating film, and the Ti layer on the entire structure including the contact hole And sequentially forming a first TiN layer, depositing the Ti layer and the first TiN layer, and then performing a heat treatment process, and performing tungsten silicide on the first TiN layer after performing the heat treatment process. Depositing, depositing a tungsten and a second TiN layer on the tungsten silicide, and then performing a planarization process; And sequentially removing selected regions of the Ti layer to form bit lines.
도 1 은 종래의 반도체 소자의 비트 라인 형성 방법을 설명하기 위해 고시한 소자의 단면도.BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a sectional view of a device disclosed for explaining a bit line forming method of a conventional semiconductor device.
도 2 는 본 발명에 따른 반도체 소자의 비트 라인 형성 방법을 설명하기 위해 도시한 소자의 단면도.2 is a cross-sectional view of a device for explaining the method of forming a bit line of a semiconductor device according to the present invention;
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11, 21 : 반도체 기판12, 22 : 절연막11, 21: semiconductor substrate 12, 22: insulating film
13, 23 : Ti층14, 24 : 제 1 TiN층13, 23: Ti layer 14, 24: first TiN layer
15, 26 : 텅스텐25 : WSiX 15, 26: tungsten 25: WSi X
16, 27 : 제 2 TiN층16, 27: second TiN layer
본 발명에서는 종래의 Si/Ti/제 1 TiN/W/제 2 TiN의 적층 구조를 텅스텐의 Si 포화 고용도, 즉 텅스텐 실리사이드(WSiX)를 미리 첨가하여 Si/Ti/제 1 TiN/WSiX/W/제 2 TiN의 적층 구조로 변형하므로써 후속 고온 열처리 공정에 의하여 발생할 수 있는 Si와 W의 상호 확산(interdiffusion) 가능성을 배제한다.In the present invention, the conventional Si / Ti / claim 1 TiN / W / claim FIG Si saturated employment of a multilayer structure of 2 TiN tungsten, or tungsten silicide by the (WSi X) pre-addition of Si / Ti / claim 1 TiN / WSi X Modification to a laminated structure of / W / second TiN eliminates the possibility of interdiffusion of Si and W that may occur by subsequent high temperature heat treatment processes.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2 는 본 발명에 따른 반도체 소자의 비트 라인 형성 방법을 설명하기 위해 도시한 소자의 단면도이다. 도시된 바와 같이 반도체 기판(21)의 상부에 절연막(22)을 형성하고, 콘택 영역을 확정한 후 절연막(22)의 선택된 영역을 식각하여 콘택 홀을 형성한다. 형성된 콘택 홀을 포함한 전체 구조 상부에 스퍼터링(sputtering) 방법으로 Ti층(23)을 200~500Å의 두께로 증착하며, 반응성 스퍼터링(sputtering) 방법으로 제 1 TiN층(24)을 400~700Å의 두께로 증착한다. Ti층(23) 및 제 1 TiN(24)를 증착한 후 콘택 저항(contact resistance)과 장벽(barrier) 특성을 향상시키기 위하여 급속 열처리(Rapid Thermal Processing; RTP) 공정이나 반응로에서의 열처리(Furnace Annealing; F/A)공정으로 열처리 공정을 실시한다. 이 열처리 공정은 N2혹은 N2와 H2의 혼합 가스 분위기에서 실시하며, RTP 공정은 5~15초, F/A 공정은 5~15분 정도 실시한다. 또한, F/A 공정은 저압용(Low Pressure Type) 반응로에서 실시한다. 그리고, 제 1 TiN층(24)의 상부에 CVD 방법으로 WSiX(25)를 50Å 이하의 두께를 증착한다. 350~500℃의 증착 온도에서 CVD 방법으로 텅스텐(W)(26)을 600~1000Å의 두께로 증착하고 제 2 TiN층(27)을 200~300Å의 두께로 증착한 후 평탄화 공정을 수행한다. 그 후 제 2 TiN층(27), 텅스텐(26), WSiX(25), 제 1 TiN층(24) 및 Ti층(23)의 선택된 영역을 순차적으로 제거하여 비트 라인을 형성한다.2 is a cross-sectional view of a device for explaining a method of forming a bit line of a semiconductor device according to the present invention. As illustrated, an insulating film 22 is formed on the semiconductor substrate 21, the contact area is determined, and then a selected region of the insulating film 22 is etched to form a contact hole. The Ti layer 23 is deposited to a thickness of 200 to 500 kPa over the entire structure including the formed contact hole by the sputtering method, and the thickness of the first TiN layer 24 to 400 to 700 kPa by the reactive sputtering method. To be deposited. After the Ti layer 23 and the first TiN 24 are deposited, a rapid thermal processing (RTP) process or a heat treatment in a reactor to improve contact resistance and barrier properties. Annealing (F / A) process to perform heat treatment process. This heat treatment step is performed in N 2 or a mixed gas atmosphere of N 2 and H 2 , the RTP step is performed for 5 to 15 seconds, and the F / A step is performed for about 5 to 15 minutes. In addition, F / A process is performed in a low pressure type reactor. The WSi X 25 is deposited on the first TiN layer 24 by a CVD method with a thickness of 50 kPa or less. Tungsten (W) 26 is deposited to a thickness of 600 to 1000 mW by the CVD method at a deposition temperature of 350 to 500 ° C., and the second TiN layer 27 is deposited to a thickness of 200 to 300 mW, followed by a planarization process. Thereafter, selected regions of the second TiN layer 27, tungsten 26, WSi X 25, first TiN layer 24, and Ti layer 23 are sequentially removed to form a bit line.
상술한 바와 같이 본 발명에 의하면 종래의 Si/Ti/제 1 TiN/W/제 2 TiN 적층 구조의 비트 라인에서 제 1 TiN층 위에 WSiX층을 미리 첨가함으로써 Si와 W간이 상호 확산에 의해 발생하는 열처리로 인한 접합(junction) 파괴나 누설 전류 등의 신뢰성 저하를 방지할 수 있는 훌륭한 효과가 있다.As described above, according to the present invention, the Si and W are caused by mutual diffusion by adding the WSi X layer on the first TiN layer in advance in the bit line of the conventional Si / Ti / first TiN / W / second TiN stacked structure. There is an excellent effect that can prevent the deterioration of the reliability, such as junction breakage or leakage current due to heat treatment.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960075197A KR19980055960A (en) | 1996-12-28 | 1996-12-28 | Bit line formation method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960075197A KR19980055960A (en) | 1996-12-28 | 1996-12-28 | Bit line formation method of semiconductor device |
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| KR19980055960A true KR19980055960A (en) | 1998-09-25 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100799119B1 (en) * | 2005-08-29 | 2008-01-29 | 주식회사 하이닉스반도체 | Method for forming semiconductor memory device |
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1996
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100799119B1 (en) * | 2005-08-29 | 2008-01-29 | 주식회사 하이닉스반도체 | Method for forming semiconductor memory device |
| US7994558B2 (en) | 2005-08-29 | 2011-08-09 | Hynix Semiconductor Inc. | Method for forming barrier metal layer of bit line in semiconductor memory device |
| US20110256388A1 (en) * | 2005-08-29 | 2011-10-20 | Kwan-Yong Lim | Method for fabricating semiconductor memory device |
| US8395266B2 (en) * | 2005-08-29 | 2013-03-12 | Hynix Semiconductor Inc. | Semiconductor memory device |
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