KR19980054506A - Capacitor Formation Method of Semiconductor Device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Semiconductor device manufacturing method.

2. The technical problem to be solved by the invention

To provide a method of forming a capacitor of a semiconductor device to increase the capacity of the charge storage electrode by maximizing the effective surface area of the capacitor in a limited area.

3. Summary of Solution to Invention

A first capacitor of the first charge storage electrode and the first plate electrode is formed before the bit line is formed, and a predetermined size is larger than the second charge storage electrode and the first plate electrode connected to the first charge storage electrode after the bit line is formed. After forming the second plate electrode as small as the second capacitor to form a second capacitor, the metal contact hole for connecting the first and the second capacitor is formed in the region around the cell region in the subsequent metal wiring formation process, the metal for metal wiring It is an object of the present invention to provide a method for forming a capacitor, which comprises forming a film.

4. Important uses of the invention

Used in capacitor shape process of semiconductor device manufacturing process.

Description

Capacitor Formation Method of Semiconductor Device

The present invention relates to a method of forming a capacitor during a semiconductor device manufacturing process, and more particularly, to a method of forming a charge storage electrode for securing a capacitor capacity.

In general, the area in which charge storage electrodes are formed per unit cell is decreasing as general-purpose semiconductor devices, including DRAMs, are being reduced. Thus, the shapes of the charge storage electrodes are cylindrical, fin, Alternatively, it is formed by various types of three-dimensional electrode structures such as cavity type or by applying metastable polysilicon (MPS: Metatable Polysilicon) to the various types of three-dimensional electrodes as described above, thereby maximizing the surface area. Technology for securing telephone storage capacity is currently being researched and developed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a capacitor of a semiconductor device for increasing the capacity of a charge storage electrode by maximizing the effective surface area of a capacitor in a limited area.

1A to 1E are cross-sectional views of a capacitor forming process of a semiconductor device according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2: Field oxide film

3: gate oxide film 4: gate electrode and word line

5, 11, 14: oxide film spacer 6, 10, 13, 18: interlayer insulating film

7: first charge storage electrode 8, 16: dielectric film

9: first plate electrode 12: bit line

15: second charge storage electrode 17: second plate electrode

19: metal film

In order to achieve the above object, the present invention comprises the steps of: forming a first charge storage electrode contacting a semiconductor substrate at a predetermined portion through a first interlayer insulating film on a semiconductor substrate having a conventional transistor; Forming a first conductive film for the first dielectric film plate electrode on the entire structure, and forming the first plate electrode by an etching process using a mask for the plate electrode; Forming a second interlayer insulating film on the entire structure; Forming a bit line penetrating the first and second interlayer insulating layers and contacting the semiconductor substrate at a predetermined portion; Forming a third interlayer insulating film over the entire structure; Forming a second charge storage electrode penetrating the first dielectric layer, the first plate electrode, the second and third interlayer insulating layers and contacting the first charge storage electrode at a predetermined portion; A second dielectric film and a conductive film for the second plate electrode are formed on the entire structure, and the polysilicon film and the second dielectric film for the second plate electrode are selectively etched by using a mask smaller than the mask for the plate electrode by a predetermined size. Forming a plate electrode; Forming a fourth interlayer insulating film over the entire structure; Selective etching of the second to fourth interlayer insulating films in the cell periphery area by an etching process using a predetermined mask to selectively etch the first metal contact hole and the fourth interlayer insulating film exposing the first plate electrode at a predetermined portion Forming a second metal contact hole through which the second plate electrode of the site is exposed; And forming a metal film on the entire structure.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1A to 1E are cross-sectional views of a capacitor forming process of a semiconductor device according to an embodiment of the present invention.

First, FIG. 1A shows the field oxide film 2 formed on the semiconductor substrate 1 to realize inter-device isolation, and forms the entire structure gate oxide film 3 and the gate electrode and the polysilicon film for the word line. And sequentially etching the gate electrode, the polysilicon film for the word line, and the gate oxide film 3 by an etching process using a mask for forming a word line to form the gate electrode and the word line 4, and then the source / A drain region (not shown) is formed, and a first interlayer insulating film 6 is formed over the entire structure.

Subsequently, before the bit line contact hole forming process, the first interlayer insulating layer 6 is selectively etched using the contact hole mask for the charge storage electrode to expose the first charge storage electrode contact to expose the semiconductor substrate 1 at a predetermined portion. After the hole is formed, the first polysilicon film for the charge storage electrode is deposited on the entire structure, and the first polysilicon film for the charge storage electrode is etched using the mask for forming the charge storage electrode to form the first charge storage electrode ( 7) is shown. Reference numeral 5 denotes a first oxide film spacer.

In this case, a hemispherical polysilicon film may be deposited on the first polysilicon film for the charge storage electrode to maximize the surface area of the charge storage electrode.

Subsequently, FIG. 1B shows a first dielectric film 8 composed of a nitride film / oxide film and a first polysilicon film for plate electrodes formed over the entire structure, and the first poly for plate electrodes is formed by an etching process using a mask for plate electrodes. The first capacitor is formed by etching the silicon film and the first dielectric film 8 in order to form the first plate electrode 9.

1C shows a second interlayer insulating film 10 formed over the entire structure, and selectively etches the second interlayer insulating film 10 using a bit line contact hole mask to form a semiconductor substrate 1 at a predetermined position. After the exposed bit line contact hole is formed, a second oxide spacer 11 is formed on the sidewall of the bit line contact hole to insulate the first capacitor and the word line, and the polysilicon for the bit line is formed over the entire structure. After the film is deposited, the bit line polysilicon film is etched using the bit line forming mask to form the bit line 12.

1D shows a third interlayer insulating film 13 formed over the entire structure, and the third interlayer insulating film 13, the second interlayer insulating film 10, and the first plate are formed by using a contact hole mask for charge storage electrode. The electrode 9 and the first dielectric layer 8 are selectively etched to form a second charge storage electrode contact hole exposing the first charge storage electrode 7 at a predetermined portion, and thereafter, for the charge storage electrode on the entire structure. Etching process using a mask for depositing a second polysilicon film and a sacrificial oxide film (not shown) and forming a charge storage electrode; and a third polysilicon film for the charge storage electrode and a third for charge storage electrode on the sidewalls of the sacrificial oxide film. The second charge storage electrode 15 is formed by a series of processes, such as forming a polysilicon film spacer and removing a sacrificial oxide film, wherein the second and third charge storage electrodes are formed. On top of the polysilicon film By depositing a hemispherical polysilicon film it is possible to maximize the surface area of the charge storage electrode.

On the other hand, the second charge storage electrode may form a stacked charge storage electrode rather than the cylindrical type as described above.

Lastly, FIG. 1E shows a second dielectric film 16 composed of a nitride film / oxide film and a second polysilicon film for plate electrodes formed over the entire structure, and is more predetermined than a mask for plate electrodes for forming the first plate electrode 17. The second polysilicon film and the second dielectric film 16 are sequentially etched by the etching process using a mask as small as the size to form the second plate electrode 17, thereby forming a second capacitor. The fourth interlayer insulating film 18 is formed on the entire structure, and the metal wiring forming mask is modified by using the modified metal wiring forming mask to connect the first and second plate electrodes 9 and 17 in the subsequent metal wiring forming process. The first plate electrode 9 is selectively etched by selectively etching the second, third and fourth interlayer insulating films 10, 13, and 18 on the cell region boundary region other than the region where the first and second capacitors are formed. Selectively etching the exposed first metal contact hole and the fourth interlayer insulating layer 18 to form a second metal contact hole through which the second plate electrode 17 is exposed, and then forming a metal layer on the entire structure. FIG. 19 shows the formation of metallization by the deposition and etching process.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

According to the present invention made as described above, a stack connected to the first charge storage electrode in a state in which the first capacitor of the first charge storage electrode and the first plate electrode is formed in advance according to the existing stacked capacitor manufacturing process before forming the bit line. A second capacitor formed by forming a second charge storage electrode of a type or cylinder shape and a smaller size than the first plate electrode to form a second capacitor to maximize the effective surface area of the charge storage electrode, and then forming metal wiring thereafter. In the process, a metal contact hole for connecting the first and second capacitors is formed in a region around the cell region, and a metal film for metal wiring is formed to electrically connect the first and second capacitors so that the charge storage electrode has a limited area. The effective surface area can be maximized to increase the capacity of the charge storage electrode.

Claims (6)

Forming a first charge storage electrode penetrating the first interlayer insulating film on a semiconductor substrate on which a conventional transistor is already formed and contacting the semiconductor substrate at a predetermined portion; Forming a first dielectric film and a first conductive film for a plate electrode on the entire structure, and forming a first plate electrode by an etching process using a mask for a plate electrode; Forming a second interlayer insulating film on the entire structure; Forming a bit line penetrating the first and second interlayer insulating layers and contacting the semiconductor substrate at a predetermined portion; Forming a third interlayer insulating film over the entire structure; Forming a second charge storage electrode penetrating the first dielectric layer, the first plate electrode, the second and third interlayer insulating layers and contacting the first charge storage electrode at a predetermined portion; A second conductive film for the second dielectric film and the plate electrode is formed on the entire structure, and the second conductive film for the plate electrode and the second dielectric film are selectively etched by using a mask smaller than the mask for the plate electrode by a predetermined size, thereby forming the second plate. Forming an electrode; Forming a fourth interlayer insulating film over the entire structure; Selective etching of the second to fourth interlayer insulating films in the cell periphery area by an etching process using a predetermined mask to selectively etch the first metal contact hole and the fourth interlayer insulating film exposing the first plate electrode at a predetermined portion Forming a second metal contact hole through which the second plate electrode of the site is exposed; And A method of forming a capacitor in a semiconductor device comprising the step of forming a metal film on top of the entire structure. The method of claim 1, Forming a second charge storage electrode contacting the first charge storage electrode at a predetermined portion through the first dielectric layer, the first plate electrode, and the second and third interlayer insulating layers Forming a charge storage electrode contact hole through which the third interlayer insulating film, the second interlayer insulating film, the first plate electrode, and the first dielectric film are selectively etched using the charge storage electrode contact mask to expose the first charge storage electrode at a predetermined portion. step; And Forming a conductive film for the charge storage electrode on the entire structure, and etching the same. The method of claim 1, Forming a second charge storage electrode contacting the first charge storage electrode at a predetermined portion through the first dielectric layer, the first plate electrode, and the second and third interlayer insulating layers Forming a charge storage electrode contact hole through which the third interlayer insulating film, the second interlayer insulating film, the first plate electrode, and the first dielectric film are selectively etched using the charge storage electrode contact mask to expose the first charge storage electrode at a predetermined portion. step; Forming a first conductive film and a sacrificial oxide film for the charge storage electrode on the entire structure; Forming the sacrificial oxide pattern and the first conductive film pattern for the charge storage electrode by an etching process using a charge storage electrode mask; Forming a second polysilicon film spacer for the charge storage electrode on sidewalls of the first conductive film pattern for the charge storage electrode and the sacrificial oxide pattern; And And removing the sacrificial oxide film pattern. The method of claim 1, And the first and second charge storage electrodes are formed using a polysilicon film. The method of claim 1, And the first and second charge storage electrodes are formed of a film in which a polysilicon film and a hemispherical polysilicon film are sequentially stacked. The method of claim 1, And the first and second dielectric films are films in which a nitride film and an oxide film are sequentially stacked.