KR19980054331A - Wiring formation method - Google Patents
Wiring formation method Download PDFInfo
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- KR19980054331A KR19980054331A KR1019960073479A KR19960073479A KR19980054331A KR 19980054331 A KR19980054331 A KR 19980054331A KR 1019960073479 A KR1019960073479 A KR 1019960073479A KR 19960073479 A KR19960073479 A KR 19960073479A KR 19980054331 A KR19980054331 A KR 19980054331A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 배선 형성 방법에 관한 것으로, 특히 전면이 평탄한 배선을 형성하는 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method, and more particularly, to a wiring forming method for forming a wiring having a flat front surface.
이를 위한 본 발명의 배선 형성 방법은 단차를 갖는 기판상에 제1절연막을 형성하는 단계, 상기 제1절연막을 패터닝하여 상기 기판의 단차에 의해 높은 부위에 트렌치를 형성하는 단계와 상기 트렌치 상측을 포함하여 제1절연막상의 소정 부위에 평탄한 배선들을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The wiring forming method of the present invention comprises the steps of forming a first insulating film on a substrate having a step, patterning the first insulating film to form a trench in a high region by the step of the substrate and the trench upper side And forming flat lines on a predetermined portion of the first insulating layer.
Description
본 발명은 배선 형성 방법에 관한 것으로, 특히 전면이 평탄한 배선을 형성하는 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method, and more particularly, to a wiring forming method for forming a wiring having a flat front surface.
이하 첨부된 도면을 참조하여 배선 형성 방법을 설명하면 다음과 같다.Hereinafter, a wiring forming method will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래 기술에 따른 배선 형성 방법을 나타낸 공정 단면도이다.1A to 1C are cross-sectional views illustrating a wire forming method according to the related art.
도 1a에서와 같이, 단차를 갖는 반도체 기판(11)상에 ILD(Inter Layer Dielectric)막(12)과 제1감광막을 차례로 형성한 다음, 상기 제1감광막을 상기 ILD막(12)상의 소정 부위만 제거되도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제1감광막을 마스크로 이용하여 상기 ILD막(12)을 선택적 식각함으로 콘택홀을 형성하고, 상기 제1감광막을 제거한다.As shown in FIG. 1A, an ILD (Inter Layer Dielectric) film 12 and a first photosensitive film are sequentially formed on a semiconductor substrate 11 having a step, and then the first photosensitive film is formed on a predetermined portion on the ILD film 12. After selectively exposing and developing to remove only, the contact hole is formed by selectively etching the ILD film 12 using the selectively exposed and developed first photoresist film as a mask, and the first photoresist film is removed.
도 1b에서와 같이, 상기 콘택홀을 포함한 전면에 텅스텐층을 형성한 후, 상기 텅스텐층을 상기 콘택홀 내에만 남도록 에치백하여 텅스텐 플러그(13)를 형성한다. 이어 상기 텅스텐 플러그(13)를 포함한 ILD막(12)상에 제1금속층(14)과 제2감광막을 차례로 형성하고, 상기 제2감광막을 배선이 형성될 부위만 제거되도록 선택적으로 노광 및 현상한 다음, 상기 선택적으로 노광 및 현상된 제2감광막을 마스크로 이용하여 상기 제1금속층(14)을 선택적 식각함으로서 배선들을 형성한 후, 상기 제2감광막을 제거한다. 그리고 상기 제1금속층(14)을 포함한 전면에 제1TEOS(Tetra Ethyl Orthorhombic Silicate)층(15)을 형성한다.As shown in FIG. 1B, after forming a tungsten layer on the entire surface including the contact hole, the tungsten layer is etched back so as to remain only in the contact hole to form a tungsten plug 13. Subsequently, the first metal layer 14 and the second photoresist film are sequentially formed on the ILD film 12 including the tungsten plug 13, and the second photoresist film is selectively exposed and developed to remove only the portion where the wiring is to be formed. Next, wirings are formed by selectively etching the first metal layer 14 using the selectively exposed and developed second photosensitive film as a mask, and then the second photosensitive film is removed. In addition, a first TEOS (Tetra Ethyl Orthorhombic Silicate) layer 15 is formed on the entire surface including the first metal layer 14.
도 1c에서와 같이, 상기 제1TEOS층(15)상에 SOG(Spin On Glass)층(16)을 형성한 후, 상기 SOG층(16)을 에치백한다. 이어 상기 SOG층(16)을 포함한 제1TEOS층(15)상에 제2TEOS층(17)을 형성한다.As shown in FIG. 1C, after the SOG (Spin On Glass) layer 16 is formed on the first TEOS layer 15, the SOG layer 16 is etched back. Next, a second TEOS layer 17 is formed on the first TEOS layer 15 including the SOG layer 16.
종래의 배선 형성 방법은 단차를 갖는 반도체 기판상에 배선 형성시 단차에 의해 전면이 평탄하지 못하는 문제점이 있었다.Conventional wiring forming method has a problem that the entire surface is not flat due to the step when forming the wiring on the semiconductor substrate having a step.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 높은 부위의 배선을 형성하기 전에 배선이 형성될 부위에 트렌치를 형성하고 배선들을 형성하여 전면을 평탄화시키는 배선 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a wiring forming method for forming a trench in a portion where a wiring is to be formed and forming wirings to planarize the entire surface before forming the wiring in a high portion.
도 1a 내지 도 1c는 종래 기술에 따른 배선 형성 방법을 나타낸 공정 단면도.1A to 1C are cross-sectional views illustrating a wiring forming method according to the prior art.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 배선 형성 방법을 나타낸 공정 단면도.2A to 2E are cross-sectional views illustrating a wiring forming method according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
31:반도체 기판32:ILD막31: semiconductor substrate 32: ILD film
34:제1티타늄층35:제1질화 티타늄층34: first titanium layer 35: first titanium nitride layer
36:텅스텐 플러그37:알루미늄층36: tungsten plug 37: aluminum layer
38:제2티타늄층39:제2질화 티타늄층38: second titanium layer 39: second titanium nitride layer
40:제1TEOS층41:SOG층40: first TEOS layer 41: SOG layer
42:제2TEOS층42: the second TEOS layer
본 발명의 배선 형성 방법은 단차를 갖는 기판상에 제1절연막을 형성하는 단계, 상기 제1절연막을 패터닝하여 상기 기판의 단차에 의해 높은 부위에 트렌치를 형성하는 단계와 상기 트렌치 상측을 포함하여 제1절연막상의 소정 부위에 평탄한 배선들을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The wiring forming method of the present invention includes the steps of forming a first insulating film on a substrate having a step, patterning the first insulating film to form a trench in a high region by the step of the substrate, and including the upper side of the trench. And forming flat wires in a predetermined portion on the insulating film.
상기와 같은 본 발명에 따른 배선 형성 방법의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the wiring forming method according to the present invention as follows.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 배선 형성 방법을 나타낸 공정 단면도이다.2A to 2E are cross-sectional views illustrating a wiring forming method according to an exemplary embodiment of the present invention.
도 2a에서와 같이, 단차를 갖는 반도체 기판(31)상에 ILD막(32)과 제1감광막을 차례로 형성한 다음, 상기 제1감광막을 상기 ILD막(32)상의 소정 부위만 제거되도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제1감광막을 마스크로 이용하여 상기 ILD막(32)을 선택적 식각함으로 콘택홀을 형성하고, 상기 제1감광막을 제거한다.As shown in FIG. 2A, an ILD film 32 and a first photoresist film are sequentially formed on the semiconductor substrate 31 having a step, and then the first photoresist film is selectively removed so that only a predetermined portion on the ILD film 32 is removed. After exposure and development, a contact hole is formed by selectively etching the ILD film 32 using the selectively exposed and developed first photoresist film as a mask to remove the first photoresist film.
도 2b에서와 같이, 상기 콘택홀을 포함한 전면에 제2감광막(33)을 도포하고, 상기 제2감광막(33)을 상기 단차를 갖는 반도체 기판(31)에 의해 높은 부위의 배선들이 형성될 부위만 제거되도록 선택적으로 노광 및 현상한 후, 노출된 상기 ILD막(32)을 소정 깊이로 식각하여 트렌치들을 형성한다. 여기서 상기 트렌치들은 상기 단차의 차이 만큼의 깊이로 형성한다.As shown in FIG. 2B, the second photoresist layer 33 is coated on the entire surface including the contact hole, and the second photoresist layer 33 is formed on the semiconductor substrate 31 having the stepped portion, in which the wirings of the high portion are to be formed. After selectively exposing and developing to remove only, the exposed ILD film 32 is etched to a predetermined depth to form trenches. The trenches may be formed to a depth equal to the difference between the steps.
도 2c에서와 같이, 상기 제2감광막(33)을 제거하고, 상기 트렌치들을 포함한 전면에 제1티타늄층(34)과 제1질화 티타늄층(35)을 차례로 형성한 다음, 상기 제1질화 티타늄층(35)상에 제3감광막(도면에는 도시되지 않음)을 도포한다. 이어 상기 제3감광막을 상기 콘택홀을 중심으로 너비가 콘택홀 보다 더 넓은 부위의 상측에만 제거되도록 선택적으로 노광 및 현상한 다음, 전면에 텅스텐층을 형성한 후, 상기 텅스텐층을 에치백하여 상기 콘택홀내에 텅스텐 플러그(36)를 형성하고, 상기 제3감광막을 제거한다.As shown in FIG. 2C, the second photoresist layer 33 is removed, a first titanium layer 34 and a first titanium nitride layer 35 are sequentially formed on the entire surface including the trenches, and then the first titanium nitride layer is formed. A third photoresist film (not shown in the drawing) is applied on the layer 35. Subsequently, the third photoresist film is selectively exposed and developed to be removed only on an upper side of a portion having a width wider than that of the contact hole, and then a tungsten layer is formed on the front surface, and the tungsten layer is etched back. A tungsten plug 36 is formed in the contact hole, and the third photosensitive film is removed.
도 2d에서와 같이, 상기 텅스텐 플러그(36)를 포함한 제1질화 티타늄층(35)상에 알루미늄층(37), 제2티타늄층(38), 제2질화 티타늄층(39)과 제4감광막(도면에는 도시되지 않음)을 차례로 형성하고, 상기 제4감광막을 상기 콘택홀 상측을 포함한 배선들이 형성될 부위만 남도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제4감광막을 마스크로 이용하여 상기 제2질화 티타늄층(39), 제2티타늄층(38), 알루미늄층(37), 제1질화 티타늄층(35)과 제1티타늄층(34)을 선택적 식각함으로 배선들을 형성하고, 상기 제4감광막을 제거한다.As shown in FIG. 2D, the aluminum layer 37, the second titanium layer 38, the second titanium nitride layer 39 and the fourth photoresist film are formed on the first titanium nitride layer 35 including the tungsten plug 36. (Not shown in the drawing) are sequentially formed, and the fourth photoresist film is selectively exposed and developed so that only portions where wirings including the upper side of the contact hole are to be formed remain, and then the selectively exposed and developed fourth photoresist film is masked. Wirings are formed by selectively etching the second titanium nitride layer 39, the second titanium layer 38, the aluminum layer 37, the first titanium nitride layer 35, and the first titanium layer 34 by using a. Then, the fourth photosensitive film is removed.
도 2e에서와 같이, 상기 배선들을 포함한 전면에 제1TEOS층(40)과 SOG층(41)을 차례로 형성한 후, 상기 SOG층(41)을 에치백한다. 이어 상기 SOG층(41)을 포함한 제1TEOS층(40)상에 제2TEOS층(42)을 형성한다.As shown in FIG. 2E, the first TEOS layer 40 and the SOG layer 41 are sequentially formed on the entire surface including the interconnections, and then the SOG layer 41 is etched back. Subsequently, a second TEOS layer 42 is formed on the first TEOS layer 40 including the SOG layer 41.
본 발명의 배선 형성 방법은 높은 부위의 배선을 형성하기 전에 배선이 형성될 부위에 트렌치를 형성하고 배선들을 형성함으로써 전면을 평탄화시키는 효과가 있다.The wiring forming method of the present invention has the effect of planarizing the entire surface by forming trenches and forming wirings in the portion where the wiring is to be formed before forming the wiring of the high portion.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960073479A KR100223938B1 (en) | 1996-12-27 | 1996-12-27 | Interconnecting method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960073479A KR100223938B1 (en) | 1996-12-27 | 1996-12-27 | Interconnecting method |
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|---|---|
| KR19980054331A true KR19980054331A (en) | 1998-09-25 |
| KR100223938B1 KR100223938B1 (en) | 1999-10-15 |
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| KR1019960073479A KR100223938B1 (en) | 1996-12-27 | 1996-12-27 | Interconnecting method |
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