KR19980018456U - Bottom gate mold die for semiconductor package molding process - Google Patents
Bottom gate mold die for semiconductor package molding process Download PDFInfo
- Publication number
- KR19980018456U KR19980018456U KR2019960031868U KR19960031868U KR19980018456U KR 19980018456 U KR19980018456 U KR 19980018456U KR 2019960031868 U KR2019960031868 U KR 2019960031868U KR 19960031868 U KR19960031868 U KR 19960031868U KR 19980018456 U KR19980018456 U KR 19980018456U
- Authority
- KR
- South Korea
- Prior art keywords
- molding
- semiconductor package
- cavity
- molding process
- molding resin
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
본 고안은 반도체 패키지 몰딩 공정시 본딩된 와이어의 휩쓸림(sweeping) 현상을 방지할 수 있도록 하여 반도체 패키지 공정의 수율을 향상시킬 수 있도록 한 것이다.The present invention is to prevent the sweeping of the bonded wire during the semiconductor package molding process to improve the yield of the semiconductor package process.
이를 위해, 본 고안은 반도체소자(1)를 몰딩하는 몰딩 공정시 상·하부 다이(2a)(2b)에 의해 형성되는 캐비티(3) 저면에 몰딩 수지(4)를 주입하기 위한 주입구인 게이트(5)가 형성되고 상기 게이트(5)에는 몰딩 수지(4) 유동로인 런너(6)가 연결되는 반도체 패키지 몰딩 공정용 바텀 게이트형 몰드 다이이다.To this end, the present invention provides a gate, which is an injection hole for injecting the molding resin 4 into the bottom surface of the cavity 3 formed by the upper and lower dies 2a and 2b during the molding process of molding the semiconductor device 1. 5 is a bottom gate mold die for a semiconductor package molding process in which a runner 6, which is a flow path of a molding resin 4, is connected to the gate 5.
Description
본 고안은 반도체 패키지 몰딩 공정용 바텀 게이트형 몰드 다이에 관한 것으로서, 더욱 상세하게는 반도체 패키지 몰딩 공정시 본딩된 와이어의 휩쓸림(sweeping) 현상을 방지할 수 있도록 한 것이다.The present invention relates to a bottom gate type die for a semiconductor package molding process, and more particularly, to prevent sweeping of bonded wires during a semiconductor package molding process.
일반적으로, 반도체소자 패키지 공정시에는 먼저 웨이퍼에 집적회로를 형성하는 FAB공정(Fabrication Process)을 완료한 후, 웨이퍼 상에 만들어진 각 칩을 분리하는 다이싱(Dicing), 분리된 각 칩을 리드 프레임의 패들(paddle)에 안착시키는 칩 본딩(Chip Bonding), 칩 위의 본딩 패드(Bonding pad)와 리드 프레임의 인너 리드(Inner Lead)를 전기적으로 접속시키는 와이어 본딩(Wire Bonding)을 순차적으로 수행하고 회로를 보호하기 위해 몰딩(Molding)을 수행하게 된다.In general, in the semiconductor device package process, after completing a FAB process (fabrication process) for forming an integrated circuit on a wafer, dicing and separating each chip made on the wafer, each separated chip is subjected to a lead frame. Chip bonding to be seated on a paddle of the chip, and wire bonding to electrically connect the bonding pad on the chip and the inner lead of the lead frame are sequentially performed. Molding is performed to protect the circuit.
또한, 몰딩을 수행한 후에는 리드 프레임의 써포트 바(Support Bar) 및 댐 바(Dam Bar)를 자르는 트리밍(Trimming) 및 아웃 리드(Out Lead)를 소정의 형상으로 굽혀 주는 포밍(Forming) 을 동시에 수행하고 난 후, 최종적으로 솔더링(Sodering)을 실시하므로써 패키지 공정을 완료하게 된다.In addition, after molding, the trimming to cut the support bar and the dam bar of the lead frame and the forming to bend the out lead to a predetermined shape are simultaneously performed. After the execution, the soldering process is finally performed to complete the package process.
한편, 종래에는 몰딩 공정 수행시 다음과 같은 과정을 거쳐 몰딩이 수행된다.Meanwhile, in the related art, molding is performed through the following process when the molding process is performed.
즉, 도 1 내지 도 3에 나타낸 바와 같이 상·하부 다이(2c),(2d)에 의해 캐비티(3a)가 형성된 후, 타블렛(tablet) 형태의 몰딩 수지(4)가 포트에 삽입된 상태에서 트랜스퍼 플런저(8)가 상승하여 몰딩 수지(4)를 가압함에 따라, 몰딩 다이로부터 열을 전달받아 용융된 몰딩 수지(4)가 몰딩 다이 내의 유동로인 런너(6a) 및 캐비티(3a) 입구인 게이트(5a)를 지나 캐비티(3a)의 공간 내에 충진되며, 그 후 일정 시간이 지나면 몰딩 수지(4)가 경화되므로써 리드 프레임(11) 상의 반도체소자(1)에 대한 몰딩이 완료된다.That is, as shown in Figs. 1 to 3, after the cavity 3a is formed by the upper and lower dies 2c and 2d, the molding resin 4 in the form of a tablet is inserted into the pot. As the transfer plunger 8 rises to pressurize the molding resin 4, the molten molding resin 4 receives heat from the molding die, and the molten molding resin 4 is a flow path in the molding die. After the gate 5a is filled in the space of the cavity 3a, after a predetermined time, the molding resin 4 is cured, thereby completing molding of the semiconductor device 1 on the lead frame 11.
이 때, 상기 트랜스퍼 플런저(8)를 상승시키는 바텀 플레이트(9a)는 톱 플레이트(9b) 저면에 결합된 가이드 포스트(10)의 축방향을 따라 상승하게 된다.At this time, the bottom plate 9a for raising the transfer plunger 8 rises along the axial direction of the guide post 10 coupled to the bottom of the top plate 9b.
또한, 몰딩 수지(4)의 주입시, 캐비티(3a)내에 있던 공기는 에어 벤트(Air Vent)(7a)를 통해 밖으로 배출된다.In addition, at the time of injecting the molding resin 4, the air in the cavity 3a is discharged out through the air vent 7a.
한편, 상기 캐비티(3a)내에 충진되는 몰딩 수지(4)는 열경화성 수지이므로 물리적 특성상 고온, 고압에서 경화하는 시간을 필요로 하며 한번 경화하면 다시 가열해도 연화되지 않는다.On the other hand, since the molding resin 4 filled in the cavity 3a is a thermosetting resin, it requires time to cure at high temperature and high pressure due to physical properties, and once cured, the molding resin 4 does not soften when heated again.
그러나, 이와 같은 종래에는 캐비티(3a) 내로 주입되는 몰딩 수지(4)가 캐비티(3a)의 일측면으로부터 주입되므로 인해, 본딩된 와이어(12)가 몰딩 수지(4)에 휩쓸려 쓰러지는 현상(sweeping)이 발생할 우려가 많이 있었다.However, in the related art, since the molding resin 4 injected into the cavity 3a is injected from one side of the cavity 3a, the bonded wire 12 is swept away by the molding resin 4. There was a lot of concern about this.
즉, 와이어(12)가 몰딩 수지(4)에 휩쓸려 넘어지면서 서로 단락되어 반도체 패키지의 불량을 초래하므로써 결국 반도체 패키지 공정의 수율을 저하시키게 되는 등 많은 문제점이 있었다.In other words, the wires 12 are swept away by the molding resin 4 and short-circuited with each other, resulting in defects in the semiconductor package, thereby lowering the yield of the semiconductor package process.
본 고안은 상기한 제반 문제점을 해결하기 위한 것으로서, 반도체 패키지 몰딩 공정시 본딩된 와이어의 휩쓸림(sweeping)현상을 방지할 수 있도록 하여 반도체 패키지 공정이 수율을 향상시킬 수 있도록 한 반도체 패키지 몰딩 공정용 바텀 게이트형 몰드 다이를 제공하는데 그 목적이 있다.The present invention is to solve the above problems, the semiconductor package molding process to improve the yield of the semiconductor package process to prevent the sweeping of the bonded wire during the semiconductor package molding process The object is to provide a bottom gated mold die.
상기한 목적을 달성하기 위해, 본 고안은 반도체소자를 몰딩하는 몰딩 공정시 상·하부 다이에 의해 형성되는 캐비티 저면에 몰딩 수지를 주입하기 위한 주입구인 게이트가 형성되고 상기 게이트에는 몰딩 수지 유동로인 런너가 연결되는 반도체 패키지 몰딩 공정용 바텀 게이트형 몰드 다이이다.In order to achieve the above object, the present invention is a gate which is an injection hole for injecting molding resin into the bottom of the cavity formed by the upper and lower die during the molding process for molding a semiconductor device is formed in the molding resin flow path A bottom gate mold die for a semiconductor package molding process to which a runner is connected.
도 1은 종래의 트랜스퍼 몰드 다이를 나타낸 종단면도1 is a longitudinal cross-sectional view showing a conventional transfer mold die.
도 2는 종래의 칩 본딩된 리드 프레임을 나타낸 평면도2 is a plan view showing a conventional chip bonded lead frame
도 3은 종래의 몰딩 수지에 의해 몰딩되는 과정을 나타낸 평면도3 is a plan view showing a process of molding by a conventional molding resin
도 4는 본 고안의 트랜스퍼 몰드 다이를 나타낸 종단면도Figure 4 is a longitudinal cross-sectional view showing a transfer mold die of the present invention
도 5는 본 고안에 따른 몰딩 과정을 나타낸 평면도5 is a plan view showing a molding process according to the present invention
도 6은 본 고안의 다른 실시예를 나타낸 요부 종단면도Figure 6 is a longitudinal cross-sectional view showing the main portion of another embodiment of the present invention
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1 : 반도체 소자2a,2b : 상·하부 다이DESCRIPTION OF SYMBOLS 1: Semiconductor element 2a, 2b: Upper and lower die
3 : 캐비티4 : 몰딩 수지3: cavity 4: molding resin
5 : 게이트6 : 런너5: gate 6: runner
7 : 에어 벤트7: air vent
이하, 본 고안의 일 실시예를 첨부도면 도 4 및 도 5를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 4 and 5.
도 4는 본 고안의 트랜스퍼 몰드 다이를 나타낸 종단면도이고, 도 5는 본 고안에 따른 몰딩 과정을 나타낸 평면도로서, 본 고안은 반도체소자(1)를 몰딩하는 몰딩 공정시 상·하부 다이(2a),(2b)에 의해 형성되는 캐비티(3) 저면에 몰딩 수지(4)를 주입하기 위한 주입구인 게이트(5)가 형성되고 상기 게이트(5)에는 으로 몰딩 수지(4)를 주입하기 위한 주입구인 게이트(5) 및 몰딩 수지(4) 유동로인 런너(6)가 연결되어 구성된다.Figure 4 is a longitudinal cross-sectional view showing a transfer mold die of the present invention, Figure 5 is a plan view showing a molding process according to the present invention, the present invention is the upper and lower die (2a) during the molding process for molding the semiconductor device (1) A gate 5, which is an injection hole for injecting the molding resin 4, is formed in the bottom surface of the cavity 3 formed by (2b) and an injection hole for injecting the molding resin 4 into the gate 5. The gate 5 and the runner 6 which is the flow path of the molding resin 4 are connected and comprised.
이 때, 상기 캐비티(3) 양측 또는 네모서리에는 몰딩 수지(4) 주입시 캐비티(3) 내의 공기를 외부로 배출시키기 위한 에어 벤트(7)가 형성되어 구성된다.At this time, an air vent 7 for discharging air in the cavity 3 to the outside is formed at both sides or the corners of the cavity 3 when the molding resin 4 is injected.
이와 같이 구성된 본 고안의 작용은 다음가 같다.The operation of the present invention configured as described above is as follows.
먼저, 상·하부 다이(2a)(2b)가 결합하여 캐비티(3)가 형성되고 타블렛 형태의 몰딩 수지(4)가 포트에 삽입된 상태에서 트랜스퍼 플런저(8)가 상승하여 몰딩 수지(4)를 가압하게 된다.First, the upper and lower dies 2a and 2b are joined to form a cavity 3, and the transfer plunger 8 is raised while the tablet-type molding resin 4 is inserted into the pot so that the molding resin 4 Will be pressed.
이 때, 상기 트랜스퍼 플런저(8)를 상승시키는 바텀 플레이트(9a)는 톱 플레이트(9b) 저면에 결합된 가이드 포스트(10)의 축방향을 따라 상승하게 되는데, 트랜스퍼 플런저(8)가 하강함에 따라 몰딩 수지(4)가 캐비티(3)내로 주입되는 구조로 설계하여도 무방하다.At this time, the bottom plate 9a for raising the transfer plunger 8 rises along the axial direction of the guide post 10 coupled to the bottom of the top plate 9b, and as the transfer plunger 8 descends, The molding resin 4 may be designed in such a manner that the molding resin 4 is injected into the cavity 3.
즉, 상기한 바와 같이 트랜스퍼 플런저(8)의 상승시, 몰딩 다이로부터 열을 전달받아 용융된 몰딩 수지(4)는 하부 다이 내에 형성된 유동로인 런너(6) 및 캐비티(3) 저면에 형성된 주입구인 게이트(5)를 지나 캐비티(3)의 공간 내에 충진되며, 일정 시간이 지남에 따라 경화되므로써 리드프레임(11) 상의 반도체소자(1)에 대한 몰딩이 완료된다.That is, as described above, when the transfer plunger 8 is raised, the molten molding resin 4 receives heat from the molding die, and an injection hole formed in the bottom surface of the runner 6 and the cavity 3, which is a flow path formed in the lower die, is formed. The filling of the semiconductor device 1 on the lead frame 11 is completed by filling in the space of the cavity 3 through the in-gate 5 and curing over time.
이와 같이 몰딩 공정의 진행시, 본 고안에서는 몰딩 수지(4)가 종래와 달리 캐비티(3) 저면으로부터 주입되므로 인해 캐비티(3) 내의 공기를 외부로 배출시키기 위한 에어 벤트(7)를 캐비티(3) 양측 또는 네모서리에 형성할 수가 있어 몰딩 수지(4)의 주입에 따라 발생하는 와이어(12)의 휩쓸림(sweeping) 현상을 저감시킬 수 있게 된다.As such, when the molding process proceeds, in the present invention, since the molding resin 4 is injected from the bottom of the cavity 3 unlike the conventional art, the air vent 7 for discharging the air in the cavity 3 to the outside is provided in the cavity 3. ) It can be formed on both sides or the corners, it is possible to reduce the sweeping phenomenon of the wire 12 generated by the injection of the molding resin (4).
한편, 도 6은 본 고안의 다른 실시예를 나타낸 요부 종단면도로서, 상기 상·하부 다이(2a)(2b)에 의해 형성되는 캐비티(3) 저면에 복수개의 게이트(5) 및 복수개의 런너(6)를 연결하여 한꺼번에 많은 수의 패키지 몰딩을 수행할 수 있게 된다.On the other hand, Figure 6 is a longitudinal section of the main portion showing another embodiment of the present invention, a plurality of gates (5) and a plurality of runner ( By connecting 6), a large number of package moldings can be performed at one time.
이와 같이, 본 고안은 반도체 패키지 공정시 상·하부 다이(2a)(2b)에 의해 형성된 캐비티(3)내로 주입되는 몰딩 수지(4)가 캐비티(3)의 측면이 아닌 저면으로부터 주입되도록 하여 몰딩 수지(4) 주입시, 본딩된 와이어(12)에 가해지는 유동 압력을 최소화하여 와이어(12)의 휩쓸림현상을 효과적으로 방지할 수 있게 된다.As described above, the present invention allows the molding resin 4 to be injected into the cavity 3 formed by the upper and lower dies 2a and 2b during the semiconductor package process so that the molding resin 4 is injected from the bottom of the cavity 3 rather than from the side surface of the cavity 3. When the resin 4 is injected, the flow pressure applied to the bonded wire 12 can be minimized, thereby effectively preventing the wire 12 from being swept.
이상에서와 같이, 본 고안은 반도체 패키지 몰딩 공정시, 본딩된 와이어(12)의 휩쓸림(sweeping) 현상을 방지하여 반도체 패키지 공정의 수율을 향상시킬 수 있도록 한 매우 유용한 고안이다.As described above, the present invention is a very useful design to improve the yield of the semiconductor package process by preventing the sweeping phenomenon of the bonded wire 12 during the semiconductor package molding process.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019960031868U KR200146686Y1 (en) | 1996-09-30 | 1996-09-30 | Bottom gate type mold die for semiconductor package molding process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019960031868U KR200146686Y1 (en) | 1996-09-30 | 1996-09-30 | Bottom gate type mold die for semiconductor package molding process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980018456U true KR19980018456U (en) | 1998-07-06 |
| KR200146686Y1 KR200146686Y1 (en) | 1999-06-15 |
Family
ID=19468365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019960031868U KR200146686Y1 (en) | 1996-09-30 | 1996-09-30 | Bottom gate type mold die for semiconductor package molding process |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR200146686Y1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102071561B1 (en) * | 2019-09-30 | 2020-03-02 | 이정우 | Molding apparatus for semiconductor package |
-
1996
- 1996-09-30 KR KR2019960031868U patent/KR200146686Y1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102071561B1 (en) * | 2019-09-30 | 2020-03-02 | 이정우 | Molding apparatus for semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| KR200146686Y1 (en) | 1999-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR200309906Y1 (en) | lead frame for fabricating semiconductor package | |
| KR100241175B1 (en) | Transfer molding apparatus provided with a cull-block having projection part | |
| JPH01192154A (en) | Lead frame | |
| KR100591718B1 (en) | Resin-sealed semiconductor device | |
| JP3727446B2 (en) | Resin sealing mold for semiconductor devices | |
| JPH06302633A (en) | Manufacture of semiconductor device | |
| KR200146686Y1 (en) | Bottom gate type mold die for semiconductor package molding process | |
| JP2000003923A (en) | Resin sealing of semiconductor device and resin-sealing device for that | |
| JPS609131A (en) | Method for resin sealing of semiconductor device and apparatus thereof | |
| KR200202053Y1 (en) | Cull block structure of molding die for semiconductor device package | |
| KR20070035725A (en) | Molding die having double gate structure | |
| KR200232738Y1 (en) | Mold Die for semiconductor packaging | |
| JP2533475B2 (en) | Method for manufacturing semiconductor device | |
| JP2973901B2 (en) | Mold for semiconductor resin sealing | |
| JP2778332B2 (en) | Method for manufacturing semiconductor device | |
| KR0163553B1 (en) | Method of arrangement for plastic packaged mold gate | |
| KR100531423B1 (en) | lead frame for fabrication semiconductor and mold die therefor, and device for fabricating semiconductor using the same | |
| KR100983304B1 (en) | Lead frame, semiconductor package manufactured by applying same, and manufacturing method of semiconductor package | |
| JPH09115937A (en) | Manufacture of semiconductor, mold device, and lead frame | |
| JPH1058478A (en) | Transfer molding machine and manufacture of semiconductor device using it | |
| JPH0691118B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3293105B2 (en) | Semiconductor intermediate structure and resin molding device therefor | |
| KR100729025B1 (en) | Mold for semiconductor package and molding method | |
| KR950004210Y1 (en) | Package mold structure | |
| JP2004087672A (en) | Resin-sealed type semiconductor device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| REGI | Registration of establishment | ||
| FPAY | Annual fee payment |
Payment date: 20050221 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |