KR102950577B1 - 어드레스 오류들을 검출하기 위한 시스템들, 방법들, 및 장치 - Google Patents

어드레스 오류들을 검출하기 위한 시스템들, 방법들, 및 장치

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Publication number
KR102950577B1
KR102950577B1 KR1020217013421A KR20217013421A KR102950577B1 KR 102950577 B1 KR102950577 B1 KR 102950577B1 KR 1020217013421 A KR1020217013421 A KR 1020217013421A KR 20217013421 A KR20217013421 A KR 20217013421A KR 102950577 B1 KR102950577 B1 KR 102950577B1
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South Korea
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parity
address
address information
data
storage array
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KR1020217013421A
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English (en)
Korean (ko)
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KR20210058982A (ko
Inventor
데이비드 피터 폴리
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텍사스 인스트루먼츠 인코포레이티드
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/024—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
KR1020217013421A 2018-10-05 2019-10-04 어드레스 오류들을 검출하기 위한 시스템들, 방법들, 및 장치 Active KR102950577B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/153,546 2018-10-05
US16/153,546 US11055172B2 (en) 2018-10-05 2018-10-05 Systems, methods, and apparatus to detect address faults
PCT/US2019/054784 WO2020072952A1 (en) 2018-10-05 2019-10-04 Systems, methods, and apparatus to detect address faults

Publications (2)

Publication Number Publication Date
KR20210058982A KR20210058982A (ko) 2021-05-24
KR102950577B1 true KR102950577B1 (ko) 2026-04-10

Family

ID=70051106

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020217013421A Active KR102950577B1 (ko) 2018-10-05 2019-10-04 어드레스 오류들을 검출하기 위한 시스템들, 방법들, 및 장치

Country Status (6)

Country Link
US (1) US11055172B2 (enExample)
EP (1) EP3861446B1 (enExample)
JP (1) JP7387725B2 (enExample)
KR (1) KR102950577B1 (enExample)
CN (1) CN112867992A (enExample)
WO (1) WO2020072952A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2548407A (en) * 2016-03-18 2017-09-20 Memoscale As Coding technique
US12321236B2 (en) 2020-05-11 2025-06-03 Samsung Electronics Co., Ltd. Systems, methods, and devices for fault resilient storage
US12298853B2 (en) 2020-05-11 2025-05-13 Samsung Electronics Co., Ltd. Systems, methods, and devices for data recovery with spare storage device and fault resilient storage device
US12306717B2 (en) * 2020-05-11 2025-05-20 Samsung Electronics Co., Ltd. Systems, methods, and devices for data recovery using parity space as recovery space
JP2022043635A (ja) * 2020-09-04 2022-03-16 キオクシア株式会社 メモリシステム
KR102317788B1 (ko) 2021-05-14 2021-10-26 삼성전자주식회사 스토리지 장치 및 스토리지 컨트롤러의 동작 방법
US11769567B2 (en) * 2021-07-19 2023-09-26 Nxp Usa, Inc. Devices and methods for preventing errors and detecting faults within a memory device
US11606099B1 (en) * 2021-09-23 2023-03-14 Texas Instruments Incorporated Fault detection within an analog-to-digital converter
US11853157B2 (en) * 2021-11-17 2023-12-26 Nxp B.V. Address fault detection system
WO2023091172A1 (en) * 2021-11-22 2023-05-25 Silicon Storage Technology, Inc. Address fault detection in a memory system
US11928021B2 (en) * 2022-03-31 2024-03-12 Micron Technology, Inc. Systems and methods for address fault detection
US12562213B2 (en) * 2023-07-24 2026-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Memory devices configured with adaptive word line pulse adjustment and methods for operating the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120030531A1 (en) * 2010-07-30 2012-02-02 Infineon Technologies Ag Safe Memory Storage By Internal Operation Verification

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5392302A (en) * 1991-03-13 1995-02-21 Quantum Corp. Address error detection technique for increasing the reliability of a storage subsystem
US5345582A (en) 1991-12-20 1994-09-06 Unisys Corporation Failure detection for instruction processor associative cache memories
JPH05225797A (ja) * 1992-02-14 1993-09-03 Hitachi Ltd 半導体メモリ回路
US5537425A (en) * 1992-09-29 1996-07-16 International Business Machines Corporation Parity-based error detection in a memory controller
US5453999A (en) * 1994-04-26 1995-09-26 Unisys Corporation Address verification system using parity for transmitting and receiving circuits
GB0322597D0 (en) * 2003-09-26 2003-10-29 Texas Instruments Ltd Soft error correction
DE102010029345A1 (de) * 2010-05-27 2011-12-08 Robert Bosch Gmbh Verfahren zum Erkennen eines Fehlers in einem AD-Wandler durch Paritätsvorhersagen
JP2013073653A (ja) 2011-09-28 2013-04-22 Elpida Memory Inc 半導体装置
US9075741B2 (en) * 2011-12-16 2015-07-07 Intel Corporation Dynamic error handling using parity and redundant rows
US8806316B2 (en) * 2012-01-11 2014-08-12 Micron Technology, Inc. Circuits, integrated circuits, and methods for interleaved parity computation
US10541044B2 (en) * 2016-10-31 2020-01-21 Qualcomm Incorporated Providing efficient handling of memory array failures in processor-based systems
KR102766341B1 (ko) * 2016-11-30 2025-02-12 삼성전자주식회사 메모리 모듈, 이를 포함하는 메모리 시스템 및 메모리 시스템의 동작 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120030531A1 (en) * 2010-07-30 2012-02-02 Infineon Technologies Ag Safe Memory Storage By Internal Operation Verification

Also Published As

Publication number Publication date
US20200110659A1 (en) 2020-04-09
EP3861446B1 (en) 2025-05-14
US11055172B2 (en) 2021-07-06
KR20210058982A (ko) 2021-05-24
EP3861446A4 (en) 2021-12-15
EP3861446A1 (en) 2021-08-11
JP7387725B2 (ja) 2023-11-28
WO2020072952A1 (en) 2020-04-09
CN112867992A (zh) 2021-05-28
JP2022504328A (ja) 2022-01-13

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