KR102936129B1 - 반도체 소자의 제조 방법 및 반도체 소자 - Google Patents

반도체 소자의 제조 방법 및 반도체 소자

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Publication number
KR102936129B1
KR102936129B1 KR1020257023267A KR20257023267A KR102936129B1 KR 102936129 B1 KR102936129 B1 KR 102936129B1 KR 1020257023267 A KR1020257023267 A KR 1020257023267A KR 20257023267 A KR20257023267 A KR 20257023267A KR 102936129 B1 KR102936129 B1 KR 102936129B1
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KR
South Korea
Prior art keywords
film
semiconductor device
manufacturing
amorphous silicon
silicide
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KR1020257023267A
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English (en)
Korean (ko)
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KR20250111390A (ko
Inventor
나오코 마츠이
유토 요시다
도시카즈 이리사와
Original Assignee
캐논 아네르바 가부시키가이샤
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0225—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using crystallisation-promoting species, e.g. using a Ni catalyst
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H10P14/3806—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation-enhancing elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Non-Volatile Memory (AREA)
KR1020257023267A 2023-07-14 2024-04-08 반도체 소자의 제조 방법 및 반도체 소자 Active KR102936129B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2023115732 2023-07-14
JPJP-P-2023-115732 2023-07-14
PCT/JP2024/014280 WO2025017981A1 (ja) 2023-07-14 2024-04-08 半導体素子の製造方法及び半導体素子
KR1020247028711A KR102835288B1 (ko) 2023-07-14 2024-04-08 반도체 소자의 제조 방법 및 반도체 소자

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1020247028711A Division KR102835288B1 (ko) 2023-07-14 2024-04-08 반도체 소자의 제조 방법 및 반도체 소자

Publications (2)

Publication Number Publication Date
KR20250111390A KR20250111390A (ko) 2025-07-22
KR102936129B1 true KR102936129B1 (ko) 2026-03-09

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KR1020247028711A Active KR102835288B1 (ko) 2023-07-14 2024-04-08 반도체 소자의 제조 방법 및 반도체 소자

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Country Status (7)

Country Link
US (1) US20250081500A1 (https=)
EP (1) EP4521878A4 (https=)
JP (1) JP7659708B1 (https=)
KR (2) KR102936129B1 (https=)
CN (1) CN119654979A (https=)
TW (1) TWI910617B (https=)
WO (1) WO2025017981A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN120711792B (zh) * 2025-08-12 2025-12-16 合肥晶合集成电路股份有限公司 半导体器件及其制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019165178A (ja) 2018-03-20 2019-09-26 東芝メモリ株式会社 半導体記憶装置
CN112786614A (zh) 2021-03-22 2021-05-11 长江存储科技有限责任公司 制备三维存储器的方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100390523B1 (ko) * 2001-01-20 2003-07-04 주승기 실리콘 박막 결정화 방법
KR100611744B1 (ko) 2003-11-22 2006-08-10 삼성에스디아이 주식회사 금속 유도 측면 결정화 방법을 이용한 박막 트랜지스터 및그의 제조 방법
KR100623228B1 (ko) * 2003-11-27 2006-09-18 삼성에스디아이 주식회사 박막트랜지스터, 상기 박막트랜지스터를 구비하는유기전계발광표시장치 및 상기 박막트랜지스터의 제조방법
JP2007251030A (ja) * 2006-03-17 2007-09-27 Renesas Technology Corp 半導体装置の製造方法および半導体装置
TWI392092B (zh) * 2008-11-10 2013-04-01 國立中山大學 具π型半導體導通層之半導體裝置及其製造方法
CN102709184B (zh) * 2011-05-13 2016-08-17 京东方科技集团股份有限公司 含有多晶硅有源层的薄膜晶体管、其制造方法及阵列基板
JP2014175348A (ja) 2013-03-06 2014-09-22 Toshiba Corp 不揮発性半導体記憶装置
JP2014179465A (ja) * 2013-03-14 2014-09-25 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
CN105244414B (zh) * 2015-10-20 2017-04-12 华中科技大学 一种二硫化钼/ 硅异质结太阳能电池及其制备方法
US9780103B2 (en) * 2015-11-16 2017-10-03 Micron Technology, Inc. Methods of forming integrated structures
JP2017174860A (ja) * 2016-03-18 2017-09-28 東芝メモリ株式会社 半導体記憶装置及びその製造方法
CN108022934A (zh) * 2016-11-01 2018-05-11 沈阳硅基科技有限公司 一种薄膜的制备方法
KR102403102B1 (ko) * 2016-12-15 2022-05-26 에이에스엠 아이피 홀딩 비.브이. 반도체 처리 장치
JP2018157069A (ja) * 2017-03-17 2018-10-04 東芝メモリ株式会社 半導体記憶装置
JP7371507B2 (ja) * 2020-01-22 2023-10-31 富士電機株式会社 炭化珪素半導体装置の製造方法
FR3106932B1 (fr) * 2020-02-04 2023-10-27 Commissariat Energie Atomique Procede de fabrication d’un substrat structure
CN115548140A (zh) * 2022-10-20 2022-12-30 中建材浚鑫科技有限公司 一种金属化异质结电池及其制备方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019165178A (ja) 2018-03-20 2019-09-26 東芝メモリ株式会社 半導体記憶装置
CN112786614A (zh) 2021-03-22 2021-05-11 长江存储科技有限责任公司 制备三维存储器的方法

Also Published As

Publication number Publication date
KR20250111390A (ko) 2025-07-22
JP7659708B1 (ja) 2025-04-09
KR20250013142A (ko) 2025-01-31
JPWO2025017981A1 (https=) 2025-01-23
TW202519029A (zh) 2025-05-01
WO2025017981A1 (ja) 2025-01-23
EP4521878A1 (en) 2025-03-12
KR102835288B1 (ko) 2025-07-18
CN119654979A (zh) 2025-03-18
US20250081500A1 (en) 2025-03-06
EP4521878A4 (en) 2026-04-29
TWI910617B (zh) 2026-01-01

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