KR102812585B1 - 반도체 다이 패키지의 신뢰성을 평가하기 위한 시스템 및 방법 - Google Patents
반도체 다이 패키지의 신뢰성을 평가하기 위한 시스템 및 방법 Download PDFInfo
- Publication number
- KR102812585B1 KR102812585B1 KR1020237031120A KR20237031120A KR102812585B1 KR 102812585 B1 KR102812585 B1 KR 102812585B1 KR 1020237031120 A KR1020237031120 A KR 1020237031120A KR 20237031120 A KR20237031120 A KR 20237031120A KR 102812585 B1 KR102812585 B1 KR 102812585B1
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor die
- semiconductor
- reliability
- risk
- pat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H01L22/20—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
- H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2868—Complete testing stations; systems; procedures; software aspects
- G01R31/287—Procedures; Software aspects
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2894—Aspects of quality control [QC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2896—Testing of IC packages; Test features related to IC packages
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Program-control systems
- G05B19/02—Program-control systems electric
- G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
- G05B19/4184—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by fault tolerance, reliability of production system
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
- H10P74/27—Structural arrangements therefor
- H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Environmental & Geological Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Automation & Control Theory (AREA)
- Quality & Reliability (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202163149367P | 2021-02-15 | 2021-02-15 | |
| US63/149,367 | 2021-02-15 | ||
| US17/212,877 | 2021-03-25 | ||
| US17/212,877 US11656274B2 (en) | 2021-02-15 | 2021-03-25 | Systems and methods for evaluating the reliability of semiconductor die packages |
| PCT/US2022/015561 WO2022173712A1 (en) | 2021-02-15 | 2022-02-08 | Systems and methods for evaluating the reliability of semiconductor die packages |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20230145420A KR20230145420A (ko) | 2023-10-17 |
| KR102812585B1 true KR102812585B1 (ko) | 2025-05-26 |
Family
ID=82800286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020237031120A Active KR102812585B1 (ko) | 2021-02-15 | 2022-02-08 | 반도체 다이 패키지의 신뢰성을 평가하기 위한 시스템 및 방법 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US11656274B2 (https=) |
| EP (1) | EP4281998A4 (https=) |
| JP (1) | JP7664405B2 (https=) |
| KR (1) | KR102812585B1 (https=) |
| CN (1) | CN116686076B (https=) |
| IL (1) | IL304264A (https=) |
| TW (1) | TWI888691B (https=) |
| WO (1) | WO2022173712A1 (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11754625B2 (en) * | 2020-01-30 | 2023-09-12 | Kla Corporation | System and method for identifying latent reliability defects in semiconductor devices |
| US12487282B2 (en) * | 2021-12-28 | 2025-12-02 | Advanced Micro Devices Products (China) Co., Ltd. | On-chip distribution of test data for multiple dies |
| US20240371822A1 (en) * | 2023-05-02 | 2024-11-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit package and method |
| CN118380354B (zh) * | 2024-06-26 | 2024-10-29 | 南通华隆微电子股份有限公司 | 一种半导体封装绷片压力自适应调节系统 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017171863A1 (en) | 2016-04-01 | 2017-10-05 | Intel Corporation | Techniques for die stacking and associated configurations |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7485548B2 (en) * | 2006-03-10 | 2009-02-03 | Micron Technology, Inc. | Die loss estimation using universal in-line metric (UILM) |
| JP2009147015A (ja) | 2007-12-12 | 2009-07-02 | Hitachi Ulsi Systems Co Ltd | 半導体装置の検査方法、検査システム及び製造方法 |
| JP2009302246A (ja) | 2008-06-12 | 2009-12-24 | Fujitsu Microelectronics Ltd | 半導体装置の選別方法 |
| US20140303912A1 (en) | 2013-04-07 | 2014-10-09 | Kla-Tencor Corporation | System and method for the automatic determination of critical parametric electrical test parameters for inline yield monitoring |
| JP6166120B2 (ja) | 2013-08-01 | 2017-07-19 | ラピスセミコンダクタ株式会社 | データ処理装置、測定装置、選別装置、データ処理方法およびプログラム |
| TWI538156B (zh) * | 2014-01-07 | 2016-06-11 | 甯樹樑 | 晶片間無微接觸點之晶圓級晶片堆疊結構及其製造方法 |
| US9653184B2 (en) | 2014-06-16 | 2017-05-16 | Sandisk Technologies Llc | Non-volatile memory module with physical-to-physical address remapping |
| KR102521159B1 (ko) | 2014-11-25 | 2023-04-13 | 피디에프 솔루션즈, 인코포레이티드 | 반도체 제조 공정을 위한 개선된 공정 제어 기술 |
| US10127651B2 (en) * | 2016-01-15 | 2018-11-13 | Kla-Tencor Corporation | Defect sensitivity of semiconductor wafer inspectors using design data with wafer image data |
| US10761128B2 (en) | 2017-03-23 | 2020-09-01 | Kla-Tencor Corporation | Methods and systems for inline parts average testing and latent reliability defect detection |
| US10726038B2 (en) * | 2017-05-24 | 2020-07-28 | MphasiS Limited | System and method for optimizing aggregation and analysis of data across multiple data sources |
| US10585049B2 (en) * | 2018-03-10 | 2020-03-10 | Kla-Tencor Corporation | Process-induced excursion characterization |
| US10867877B2 (en) * | 2018-03-20 | 2020-12-15 | Kla Corporation | Targeted recall of semiconductor devices based on manufacturing data |
| CN110596566B (zh) | 2018-06-12 | 2022-03-04 | 北京华峰测控技术股份有限公司 | 一种用于ate系统的dpat测试方法 |
| CN109830447B (zh) * | 2019-01-17 | 2020-11-27 | 深圳赛意法微电子有限公司 | 半导体晶圆芯片分选方法、半导体产品的封装方法及系统 |
| KR101991757B1 (ko) | 2019-04-10 | 2019-09-30 | (주)에이피텍 | 웨이퍼 레벨 패키징을 수행하는 자동화 시스템 |
| US11293970B2 (en) | 2020-01-12 | 2022-04-05 | Kla Corporation | Advanced in-line part average testing |
| US11754625B2 (en) | 2020-01-30 | 2023-09-12 | Kla Corporation | System and method for identifying latent reliability defects in semiconductor devices |
-
2021
- 2021-03-25 US US17/212,877 patent/US11656274B2/en active Active
-
2022
- 2022-01-10 TW TW111100921A patent/TWI888691B/zh active
- 2022-02-08 JP JP2023546059A patent/JP7664405B2/ja active Active
- 2022-02-08 KR KR1020237031120A patent/KR102812585B1/ko active Active
- 2022-02-08 EP EP22753191.0A patent/EP4281998A4/en active Pending
- 2022-02-08 CN CN202280008416.0A patent/CN116686076B/zh active Active
- 2022-02-08 WO PCT/US2022/015561 patent/WO2022173712A1/en not_active Ceased
-
2023
- 2023-07-05 IL IL304264A patent/IL304264A/en unknown
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017171863A1 (en) | 2016-04-01 | 2017-10-05 | Intel Corporation | Techniques for die stacking and associated configurations |
Non-Patent Citations (2)
| Title |
|---|
| 비특허문헌1 |
| 비특허문헌2 |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI888691B (zh) | 2025-07-01 |
| US11656274B2 (en) | 2023-05-23 |
| CN116686076B (zh) | 2024-12-24 |
| US20220260632A1 (en) | 2022-08-18 |
| KR20230145420A (ko) | 2023-10-17 |
| EP4281998A1 (en) | 2023-11-29 |
| JP2024509684A (ja) | 2024-03-05 |
| TW202246787A (zh) | 2022-12-01 |
| CN116686076A (zh) | 2023-09-01 |
| IL304264A (en) | 2023-09-01 |
| WO2022173712A1 (en) | 2022-08-18 |
| JP7664405B2 (ja) | 2025-04-17 |
| EP4281998A4 (en) | 2025-01-01 |
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