KR102667799B1 - Solar cell and method for manufacturing the same - Google Patents

Abstract

A solar cell according to an embodiment of the present invention includes a semiconductor substrate, a first structure formed on one side of the semiconductor substrate to generate and collect first carriers, and a first structure formed separately from the first structure on one side of the semiconductor substrate. and includes a second structure that generates and collects the second carrier. The first structure and the second structure have different bonding structures.

Description

Solar cell and method of manufacturing the same {SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME}

The present invention relates to a solar cell and a method of manufacturing the same, and more specifically, to a solar cell with an improved structure and a method of manufacturing the same.

Solar cells that use a doped region formed by doping a portion of a semiconductor substrate doped at a low doping concentration as a conductive region have the advantage of excellent bonding characteristics, but are susceptible to damage to the semiconductor substrate and carrier recombination due to doping of the dopant. There were problems such as deterioration of passivation characteristics due to

Accordingly, a solar cell has been proposed that forms a semiconductor layer separately from the semiconductor substrate on a semiconductor substrate doped at a low doping concentration and uses this as a conductive region. In such solar cells, first and second semiconductor layers with opposite conductivity types (n-type and p-type) must be provided to generate and transfer carriers (electrons and holes) of opposite polarities for photoelectric conversion. . In a conventional solar cell, the first and second semiconductor layers have the same semiconductor material and the same crystal structure except that they are provided with different dopants for opposite conductivity types. And in a structure where the first and second semiconductor layers are formed on the same surface, the intermediate layers and electrodes related thereto have the same materials and the same stacked structure.

In this way, if the first and second semiconductor layers, and the intermediate layers and electrodes related thereto, have the same characteristics, the manufacturing process can be simplified, but by providing dopants of different conductivity types, they have different characteristics with respect to the semiconductor substrate. Each of the first and second semiconductor layers, which should have , did not have a structure capable of maximizing the efficiency of the solar cell.

For example, among the first and second semiconductor layers, the semiconductor layer having a dopant that is easily bulk doped into the semiconductor substrate may have difficulty implementing desired characteristics, desired doping profile, etc., because the dopant excessively penetrates into the semiconductor substrate. . Additionally, if the first and second semiconductor layers include a semiconductor layer that does not make excellent contact with the electrode, the resistance may increase and the electrical characteristics may deteriorate.

The present invention seeks to provide a solar cell with excellent efficiency and a method of manufacturing the solar cell that can improve the productivity of such solar cell.

More specifically, a solar cell and method of manufacturing the same that can maximize efficiency by varying the materials and structures of the first and second conductive regions and the first and second intermediate layers or first and second electrodes related thereto. We would like to provide.

In particular, in a structure in which the first and second conductivity type regions are provided together on one side separately from the semiconductor substrate, the first intermediate layer is located between the semiconductor substrate and the first conductivity type region and the first intermediate layer is located between the semiconductor substrate and the second conductivity type region. Efficiency is increased by varying the material, structure, thickness, etc. of the second intermediate layer, and making the materials, structures, etc. of the first electrode connected to the first conductive region and the second electrode connected to the second conductive region different from each other. The goal is to provide a solar cell that can maximize solar energy and a method of manufacturing the same.

In the solar cell according to an embodiment of the present invention, the bonding structures of the first and second structures having different conductivity types are different from each other. Alternatively, the junction structures of the first and second photoelectric conversion parts that have different conductivity types and function as an emitter region and an electric field region, respectively, are different. Alternatively, the bonding structures in which the first and second conductivity type regions having different conductivity types are bonded to the semiconductor substrate are different from each other.

A solar cell according to an embodiment of the present invention includes a semiconductor substrate, a first structure formed on one side of the semiconductor substrate to generate and collect first carriers, and a first structure formed separately from the first structure on one side of the semiconductor substrate. and includes a second structure that generates and collects the second carrier. The first structure and the second structure have different bonding structures.

The first structure may include a first conductive type region having a first conductivity type, and a first electrode connected to the first conductive type region. The second structure may include a second conductivity type region having a second conductivity type opposite to the first conductivity type, and a second electrode connected to the second conductivity type region. Here, the first conductivity type region and the second conductivity type region may include the same semiconductor material, but may have different crystal structures.

The first structure further includes a first intermediate layer located between the semiconductor substrate and the first conductive type region, and the second structure includes a second intermediate layer located between the semiconductor substrate and the second conductive type region. More may be included. The first intermediate layer and the second intermediate layer may differ from each other in at least one of material and thickness.

The connection structure of the first conductive region and the first electrode and the connection structure of the second conductive region and the second electrode are different from each other, or the stacked structure of the first electrode and the stacked structure of the second electrode are different from each other. They may be different from each other, or the materials of the first electrode and the materials of the second electrode may be different from each other.

For example, the first structure may have a tunnel junction structure, and the second structure may have a heterojunction structure including an amorphous semiconductor material. In this case, the first conductivity type region may be composed of a polycrystalline semiconductor layer having a polycrystalline structure, and the second conductivity type region may be composed of an amorphous semiconductor layer having an amorphous structure.

A thickness of the first conductive type region may be greater than a thickness of the second conductive type region.

It further includes at least one of a passivation layer covering one side of the semiconductor substrate between the first structure and the second structure and an anti-reflection layer covering the other side of the semiconductor substrate, and the thickness of the first conductivity type region is It may be larger than the passivation layer or the anti-reflection layer, and the thickness of the second conductive region may be smaller than that of the passivation layer or the anti-reflection layer.

The first electrode includes a first metal electrode layer in direct contact with the first conductivity type region, and the second electrode includes a transparent electrode layer made of a transparent conductive oxide in direct contact with the second conductivity type region, and on the transparent electrode layer. It may include a second metal electrode layer located thereon.

A portion of the first metal electrode layer may be in direct contact with a portion of the first conductive region, and another portion may be positioned on at least one of a passivation layer and another transparent electrode layer.

The transparent electrode layer may be entirely in direct contact with the second conductive region, and the second metal electrode layer may be entirely in direct contact with the transparent electrode layer.

The first intermediate layer may be composed of an oxide film, and the second intermediate layer may be composed of an intrinsic amorphous silicon layer.

The first intermediate layer and the first conductive region may have the same planar shape, and the second intermediate layer and the second conductive region may have the same planar shape.

The thickness of the second intermediate layer may be equal to or greater than the thickness of the first intermediate layer.

The semiconductor substrate may have a second conductivity type, the area of the first conductivity type region may be larger than the area of the second conductivity type region, the first conductivity type may be p-type, and the second conductivity type may be n-type. there is.

The first conductive region and the second conductive region may be spaced apart from each other, so that a trench or empty space may be located between them. An additional electric field forming layer that does not contain a dopant may be provided in a portion of the semiconductor substrate where the first and second structures are not located.

A method of manufacturing a solar cell according to an embodiment of the present invention provides a method of manufacturing the above-described solar cell. In the method of manufacturing a solar cell according to an embodiment of the present invention, a first structure for generating and collecting first carriers on one surface of a semiconductor substrate and a second structure formed separately from the first structure for generating and collecting second carriers A structure is formed, and the first structure and the second structure may have different bonding structures.

The first structure may have a tunnel junction structure, and the second structure may have a heterojunction structure including an amorphous semiconductor material.

In this case, the method of manufacturing a solar cell according to an embodiment of the present invention includes forming a first intermediate layer and a first conductive region on one surface of the semiconductor substrate, a second intermediate layer and a first conductive region on one surface of the semiconductor substrate. forming a second conductive type region, and forming a transparent conductive film on one surface of the semiconductor substrate to entirely cover the first intermediate layer and the first conductive type region, the second intermediate layer, and the second conductive type region. ; forming an opening by removing a portion of the transparent conductive film to expose at least a portion of the first conductive region, the first intermediate layer, the first conductive region, and the second intermediate layer on one surface of the semiconductor substrate; , forming a metal film to entirely cover the second conductive region and the transparent conductive film, and patterning the transparent conductive film and the metal film to form a first electrode and a second electrode. To form the first structure including the first intermediate layer, the first conductive region and the first electrode, and the second structure including the second intermediate layer, the second conductive region and the second electrode. You can.

In this embodiment, the first structure including the first conductivity type region and the second structure including the second conductivity type region have different bonding structures, thereby effectively improving the efficiency and characteristics of the solar cell.

In particular, the first structure, which has a relatively large area and includes a first conductivity type region constituting an emitter region directly involved in photoelectric conversion, has a tunnel junction structure and can effectively improve electrical characteristics and open-circuit voltage. In addition, the second structure, which has a relatively small area and includes a second conductive region forming a rear electric field region, has a heterojunction structure including an amorphous semiconductor material, which can greatly improve passivation characteristics. In this way, the efficiency of the solar cell can be maximized by specifically limiting the bonding structure of the first and second structures, taking into account the functions, roles, and characteristics of the first and second structures.

Meanwhile, according to the solar cell manufacturing method according to this embodiment, solar cells with excellent characteristics and efficiency can be manufactured with high productivity.

1 is a cross-sectional view schematically showing a solar cell according to an embodiment of the present invention.
FIG. 2 is a partial rear plan view schematically showing the solar cell shown in FIG. 1.
3A to 3H are cross-sectional views showing a method of manufacturing a solar cell according to an embodiment of the present invention.
Figure 4 is a cross-sectional view showing a solar cell according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, it goes without saying that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, in order to clearly and briefly explain the present invention, parts not related to the description are omitted, and identical or extremely similar parts are denoted by the same drawing reference numerals throughout the specification. In addition, in the drawings, the thickness, area, etc. are enlarged or reduced in order to make the explanation more clear, so the thickness, area, etc. of the present invention are not limited to what is shown in the drawings.

And when a part is said to “include” another part throughout the specification, it does not exclude other parts and may further include other parts, unless specifically stated to the contrary. Additionally, when a part of a layer, membrane, region, plate, etc. is said to be “on” another part, this includes not only cases where it is “directly above” the other part, but also cases where other parts are located in between. When a part of a layer, membrane, region, plate, etc. is said to be "directly on top" of another part, it means that the other part is not located in the middle.

Hereinafter, a solar cell according to an embodiment of the present invention will be described in detail with reference to the attached drawings.

FIG. 1 is a cross-sectional view schematically showing a solar cell according to an embodiment of the present invention, and FIG. 2 is a partial rear plan view schematically showing the solar cell shown in FIG. 1.

Referring to FIGS. 1 and 2 , the solar cell 100 according to this embodiment is formed on a semiconductor substrate 10 and one surface (for example, the rear surface) of the semiconductor substrate 10 to generate and generate a first carrier. A first structure 20 that collects, and a second structure 30 that is formed on one side of the semiconductor substrate 10 separately from the first structure 20 (for example, formed apart) and generates and collects the second carrier. can be provided. Here, the first structure 20 includes a first conductive type region 22 having a first conductivity type, and a first electrode 24 connected to the first conductive type region 22. And the second structure 30 has a second conductivity type opposite to the first conductivity type and is formed separately from the first conductivity type region 22 (for example, formed apart from the second conductivity type region 32). , and a second electrode 34 connected to the second conductive region 32 and spaced apart from the first electrode 32. In this embodiment, the first structure 20 and the second structure 30 have different bonding structures. This will be explained in more detail.

The semiconductor substrate 10 may include a base region 110 having a first or second conductivity type by including a dopant of the first or second conductivity type at a relatively low doping concentration. As an example, the base region 110 may have a second conductivity type. The base region 110 may be made of a crystalline semiconductor (eg, single crystal or polycrystalline semiconductor, for example, single crystal or polycrystalline silicon, particularly single crystalline silicon) containing a first or second conductivity type dopant. In this way, the solar cell 100 based on the base region 110 or semiconductor substrate 10 with high crystallinity and few defects has excellent electrical characteristics.

At this time, the front surface of the semiconductor substrate 10 may be provided with a texturing structure or an anti-reflection structure having irregularities in the shape of a pyramid or the like to minimize reflection. These irregularities may have a specific crystal plane (for example, (111) plane) of a semiconductor as the outer surface. In addition, the rear surface of the semiconductor substrate 10 can be made into a relatively smooth and flat surface with a lower surface roughness than the front surface by mirror polishing or the like. As a result, the passivation characteristics of the rear surface where the first and second conductive regions 22 and 32 are located can be improved. In addition, the rear surface of the semiconductor substrate 10 can be made into a relatively smooth and flat surface with a lower surface roughness than the front surface by mirror polishing or the like.

The first structure 20 is located on the rear surface of the semiconductor substrate 10 and includes a first conductive type region 22 having a first conductivity type and a first electrode 24 connected thereto. It may further include a first intermediate layer 22a located between the first conductive region 22 and the first conductive region 22 . And the second structure 30 is located on the rear surface of the semiconductor substrate 10 and spaced apart from the first conductive type region 22 and includes a second conductive region 32 having a second conductivity type and a second electrode connected thereto ( 34), and may further include a second intermediate layer 32a located between the semiconductor substrate 10 and the second conductive region 32.

In this embodiment, the first structure 20 and the second structure 30 are positioned spaced apart from each other, and a kind of empty space, trench, etc. may be provided between them. Accordingly, while configuring these, the first intermediate layer 22a and the second intermediate layer 32a, the first conductive region 22 and the second conductive region 32, and the first electrode 24 and the second intermediate layer correspond to each other. The electrodes 34 are also positioned spaced apart from each other, and a kind of empty space, trench, etc. is provided between them. In this embodiment, the first structure 20 and the second structure 30, and the first intermediate layer 22a and the second intermediate layer 32a, the first conductive region 22, and the second intermediate layer configuring them, respectively, correspond to each other. Since the conductive region 32 and the first electrode 24 and the second electrode 34 have different materials, structures, thicknesses, etc., they are formed spaced apart to secure a process margin and ensure structural and electrical stability. Stability can be improved. However, the present invention is not limited to this. For example, the first intermediate layer 22a and the second intermediate layer 32a may be connected to each other or overlap each other because electrical characteristics are not affected even if connected to each other. In addition, various modifications are possible.

The first structure 20 and the second structure 30 are fundamentally different from each other in the conductivity types of the first and second conductivity type regions 22 and 32 and the carriers that are generated and transmitted. In addition, in this embodiment, the first structure 20 and the second structure 30 have different bonding structures. That is, in this embodiment, the first structure 20 and the second structure 30 have first and second conductive regions 22 and 32 each composed of a semiconductor layer formed separately from the semiconductor substrate 10. In a structure (particularly, a structure in which the first and second structures 20 and 30 are formed together on one surface of the semiconductor substrate 10), the bonding structures of the first and second structures 20 and 30 are different from each other.

Here, the fact that the junction structures are different means that the first conductive region 22 and the second conductive region 32 have different crystal structures, stacked structures, semiconductor materials, etc., so the principles of carrier generation or movement are different. It can mean. In addition, the fact that the bonding structures are different means that the first intermediate layer 22a and the second intermediate layer 32a differ in at least one of the materials and thickness due to the difference between the first and second conductive regions 22 and 32. can do. At this time, the first intermediate layer 22a is formed to smoothly generate and transmit the first carrier in the first conductive region 22 in consideration of the crystal structure of the first conductive region 22, and the second intermediate layer ( 32a) may be formed to smoothly generate and transmit second carriers in the second conductive region 32 by considering the crystal structure of the second conductive region 32, etc. In addition, the fact that the bonding structures are different means that the connection structure between the first conductive region 22 and the first electrode 24 or the first electrode ( The stacked structure of 24) is different from the connection structure of the second conductive region 32 and the second electrode 34 or the stacked structure of the second electrode 34, or the material of the first electrode 24 and the second electrode The substances in (34) may mean different things. Here, the fact that the material of the first electrode 24 and the material of the second electrode 34 are different from each other means that one of the first electrode 24 and the second electrode 34 includes a material that is not included in the other. It can mean doing.

For example, the first structure 20 may have a tunnel junction structure, and the second structure 30 may have a heterojunction structure including an amorphous semiconductor material. In this specification, the tunnel junction structure does not necessarily mean only the case where carriers move by tunneling, and may mean all cases where the carriers do not move through a semiconductor material but through an insulating film or dielectric film. A heterojunction structure including an amorphous semiconductor material may mean that the second intermediate layer 32a and/or the second conductive region 32 include an amorphous semiconductor material.

In this embodiment, the semiconductor substrate 10 may have a second conductivity type, and the first conductivity type region 22 included in the first structure 20 is connected to the semiconductor substrate 10 and a pn junction (for example, It may be an emitter region that is directly involved in photoelectric conversion by forming a pn tunnel junction. And the second conductive region 32 included in the second structure 30 is a back surface field that forms a back surface field that prevents carrier loss due to recombination on the back surface of the semiconductor substrate 10. It can be.

At this time, the area of the first conductive type region 22 may be larger than the area of the second conductive type region 32. For example, the areas of the first conductive region 22 and the second conductive region 32 can be adjusted by varying their widths. That is, the width W1 of the first conductive region 22 may be larger than the width W2 of the second conductive region 32. Then, a sufficient area of the emitter region directly involved in the photoelectric conversion region can be secured so that the photoelectric conversion can occur effectively. In addition, the first structure 20 of the tunnel junction structure is formed wider than the second structure 30 of the heterojunction structure, so that the electrical characteristics such as carrier mobility, contact characteristics with the first electrode 24, and open-circuit voltage can be improved effectively. This will be described in more detail after the first and second structures 20 and 30 are described in detail.

Here, the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the emitter area with a large area can effectively collect holes with relatively slow moving speeds, thereby contributing to improving photoelectric conversion efficiency. However, the present invention is not limited to this. However, the present invention is not limited to this, and the second conductivity type may be p-type and the first conductivity type may be n-type. Additionally, the semiconductor substrate 10 may have a conductivity type that is the same as that of the second conductivity type region 30 and opposite to that of the first conductivity type region 20 . At this time, various materials that can be n-type or p-type can be used as the first or second conductivity type dopant. Group 3 elements such as boron (B), aluminum (Al), gallium (Ga), and indium (In) can be used as p-type dopants. In the case of n-type, group 5 elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) can be used. For example, the p-type dopant may be boron (B) and the n-type dopant may be phosphorus (P).

First, the first structure 20 including the first intermediate layer 22a, the first conductive type region 22, and the first electrode 24 will be described in detail, and the second intermediate layer 32a and the second conductive type region 24 will be described in detail. The second structure 30 including the region 32 and the second electrode 34 will be described in detail.

A first intermediate layer 22a may be formed in a partial area corresponding to the first structure 20 on the rear surface of the semiconductor substrate 10, and a first conductive region 22 may be formed thereon. For example, the first intermediate layer 22a may contact the rear surface of the semiconductor substrate 10, and the first conductive region 22 may contact the first intermediate layer 22a. As an example, the first intermediate layer 22a and the first conductive region 22 are patterned together by the same patterning process to have the same planar shape, the same size at the same location, or a continuous lateral shape. You can. However, the present invention is not limited to this, and the first intermediate layer 22a and the first conductive region 22 are patterned by separate patterning processes to have different planar shapes, different sizes, or discontinuous side shapes. You can have it.

The first conductive region 22 included in the first structure 20 may be composed of a polycrystalline semiconductor layer having a polycrystalline structure. More specifically, the first conductivity type region 22 may be a polycrystalline semiconductor layer (eg, a polycrystalline silicon layer) doped with a first conductivity type dopant. If the first conductive region 22 is formed of a polycrystalline semiconductor layer, the first conductive region 22, which is formed separately from the semiconductor substrate 10, can be formed with an easy and simple structure without being greatly affected by temperature, etc. do. For example, the first conductive region 22 can be easily formed by a method using deposition or the like.

In this way, when the first conductive region 22 is composed of a polycrystalline semiconductor layer, it can have high carrier mobility and have excellent contact characteristics with the first electrode 24. For example, since the first conductive region 22 is an emitter region, carrier mobility and contact characteristics with the first electrode 24 are important factors that greatly affect the efficiency of the solar cell 100. Considering this, in this embodiment, the first conductive region 22 is composed of a polycrystalline semiconductor layer.

And the first intermediate layer 22a located between the semiconductor substrate 10 and the first conductive region 22 is a first conductive region 22 composed of a polycrystalline semiconductor layer and is to have characteristics that allow carriers to easily move. You can.

For example, the first intermediate layer 22a may be a dielectric film or an insulating film containing a dielectric material that has a dielectric constant above a certain level and allows carrier movement. If the dielectric constant is at a certain level, a polarization phenomenon occurs when an electric field is applied, allowing carriers to easily move or pass. For example, the first intermediate layer 22a may include oxide, nitride, semiconductor, conductive polymer, etc.

More specifically, the first intermediate layer 22a may be made of an oxide film, a dielectric film or insulating film containing silicon, a nitride oxide film, or a carbonation oxide film. For example, the first intermediate layer 22a may be made of a metal oxide film, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, a metal nitride oxide film, a silicon carbide oxide film, or the like. At this time, the metal included in the metal oxide film or metal nitride oxide film may be aluminum, titanium, hafnium, or the like. When containing metal in this way, the first intermediate layer 22a may be made of an aluminum oxide film, a titanium oxide film, a hafnium oxide film, an aluminum nitride oxide film, a titanium nitride oxide film, or a hafnium nitride oxide film.

For example, the first intermediate layer 22a may be a silicon oxide film containing silicon oxide. This is because the silicon oxide film has excellent passivation properties and facilitates the transfer of carriers. Additionally, a silicon oxide film can be easily formed on the surface of the semiconductor substrate 10 through various processes.

And the first electrode 24 connected to (for example, contacting) the first conductive region 22 is a first metal electrode layer 242 connected to (for example, contacting) the first conductive region 22. Includes. Since the first conductive region 22 has excellent carrier mobility and excellent contact characteristics with the first metal electrode layer 242, the first conductive region 22 does not pass through another electrode layer (for example, a transparent electrode layer). ) can be formed by contacting the first metal electrode layer 242. At this time, the first electrode 24 may include a first transparent electrode layer 240. This is because, depending on the manufacturing process, a portion of the transparent conductive film (reference numeral 440 in FIG. 3E) located on the first conductive region 22 may remain to form the first transparent electrode layer 240. However, even in this case, at least a part of the first metal electrode layer 242 is in direct contact with the first conductive region 22, and the other part is located on the rear passivation layer 40 and the first transparent electrode layer 240. This forms a second opening 404 in a portion of the rear passivation layer 40 and the first transparent electrode layer 240 located on the first conductive region 22, and forms the first metal electrode layer 242 through this. This is because it is formed to contact the mold area 22. According to this, the rear passivation layer 40 remains, so passivation characteristics can be improved, and the first transparent electrode layer 240 remains, so resistance can be further reduced. However, the present invention is not limited to this, and only one of the rear passivation layer 40 and the first transparent electrode layer 240 can remain between the first metal electrode layer 242 and the first conductive region 22, The location and size of the second opening 404 in the rear passivation layer 40 and the first transparent electrode layer 240 may be different. The first transparent electrode layer 240 is formed in the same process as the second transparent electrode layer 340 of the second electrode 34, and may have the same material and thickness as the second transparent electrode layer 340. Accordingly, the description of the material of the second transparent electrode layer 340, etc., which will be described later, can be directly applied to the first transparent electrode layer 240.

A second intermediate layer 32a may be formed in another portion of the rear surface of the semiconductor substrate 10 corresponding to the second structure 30, and a second conductive region 32 may be formed thereon. For example, the second intermediate layer 32a may contact the rear surface of the semiconductor substrate 10, and the second conductive region 32 may contact the second intermediate layer 32a. As an example, the second intermediate layer 32a and the second conductive region 32 are patterned together by the same patterning process to have the same planar shape, the same size at the same location, or a continuous lateral shape. You can. However, the present invention is not limited to this, and the second intermediate layer 32a and the second conductive region 32 are patterned by separate patterning processes to have different planar shapes, different sizes, or discontinuous side shapes. You can have it.

The second conductive region 32 included in the second structure 30 may be composed of an amorphous semiconductor layer having an amorphous structure. In this way, if the second conductive region 32 is composed of an amorphous semiconductor layer, the second conductive region 32, which is formed separately from the semiconductor substrate 10, can be formed with an easy and simple structure. For example, the second conductive region 32 can be easily formed by a method using deposition or the like.

More specifically, the second conductivity type region 32 may be an amorphous semiconductor layer doped with a second conductivity type dopant. For example, the second conductive region 32 is composed of an amorphous silicon (a-Si) layer, an amorphous silicon oxide (a-SiOx) layer, and an amorphous silicon carbide (a-SiCx) layer doped with a second conductive dopant. It can be done. As an example, the second conductive region 32 may include an amorphous silicon layer. According to this, the second conductive region 32 may include the same semiconductor material (i.e., silicon) as the semiconductor substrate 10 and have similar characteristics to the semiconductor substrate 10. As a result, the carrier can be moved more effectively and a stable structure can be implemented. At this time, the doping concentration of the second conductivity type dopant in the second conductivity type region 32 may be greater than the doping concentration of the second conductivity type dopant in the semiconductor substrate 10 . Then, the back electric field can be effectively formed by the back electric field area.

If the second conductivity type region 32 is formed of an amorphous semiconductor layer, it can be easily formed through a low temperature process and diffusion of the second conductivity type dopant into the semiconductor substrate 10 can be prevented. In particular, the second conductivity type region 32 is formed by doping a second conductivity type dopant having the same conductivity type as the semiconductor substrate 10, so that the second conductivity type dopant can easily diffuse into the semiconductor substrate 10. there is. And the second conductive region 32 forms a rear electric field region on the back of the semiconductor substrate 10 and serves to prevent surface recombination. The second conductive dopant included in the second conductive region 32 is If it undesirably diffuses excessively into the semiconductor substrate 10, the passivation characteristics of the semiconductor substrate 10 may deteriorate, making it difficult to sufficiently perform the role of preventing surface recombination. Accordingly, in this embodiment, the second conductivity type region 32 is made of an amorphous semiconductor layer to effectively prevent diffusion of the second conductivity type dopant.

In addition, the second intermediate layer 32a located between the semiconductor substrate 10 and the second conductive region 32 is to have characteristics that allow carriers to be easily transmitted to the second conductive region 32 composed of an amorphous semiconductor layer. You can. When the second conductivity type region 32 is composed of an amorphous semiconductor layer, the lower the surface passivation characteristic of the semiconductor substrate 10, the more difficult it is for carriers to move, and the carrier mobility may be relatively low due to the crystal structure. Accordingly, in this embodiment, the second intermediate layer 32a is composed of an intrinsic amorphous semiconductor layer (for example, an intrinsic amorphous silicon layer) to improve the surface passivation characteristics of the semiconductor substrate 10 and to stably transmit carriers due to the semiconductor material. make it possible However, the present invention is not limited to this.

And the second electrode 34 connected to (for example, contacting) the second conductive region 32 is a second electrode 34 made of a transparent conductive oxide connected to (for example, direct contact with) the second conductive region 32. It may include a transparent electrode layer 340 and a second metal electrode layer 342 positioned on the transparent electrode layer 340 (for example, in direct contact).

Here, the second transparent electrode layer 340 may be entirely formed (eg, in contact with) the second conductive region 32 . Being formed entirely may include not only covering the entire second conductive region 32 without empty space or empty areas, but also cases where some parts are inevitably not formed. In this way, when the second transparent electrode layer 340 is entirely formed on the second conductive region 32, the carrier can easily reach the second metal electrode layer 342 through the second transparent electrode layer 340, thereby allowing the carrier to easily reach the second metal electrode layer 342 in the horizontal direction. resistance can be reduced. Since the crystallinity of the second conductive region 32 composed of an amorphous semiconductor layer, etc. may have relatively low carrier mobility, the second transparent electrode layer 340 is provided as a whole to provide resistance when carriers move in the horizontal direction. is to deteriorate.

As an example, the second transparent electrode layer 340 and the second metal electrode layer 342 are patterned together by the same patterning process and have the same planar shape, the same size at the same location, or a continuous lateral shape. You can. More specifically, the intermediate layer 32a, the second conductive region 32, the second transparent electrode layer 340, and the second metal electrode layer 342 are patterned together by the same patterning process to have the same planar shape or the same shape. It may have the same size in position, or it may have a continuous lateral shape. However, the present invention is not limited to this, and the second intermediate layer 32a, the second conductive region 32, the second transparent electrode layer 340, and the second metal electrode layer 342 are patterned by separate patterning processes. may have different planar shapes, different sizes, or discontinuous side shapes.

In this way, since the second transparent electrode layer 340 is formed entirely on the second conductive region 32, it can be made of a material that can transmit light (transmissive material). As an example, the second transparent electrode layer 340 is made of indium tin oxide (ITO), aluminum zinc oxide (AZO), boron zinc oxide (BZO), and indium-tungsten. It may include at least one of indium tungsten oxide (IWO) and indium cesium oxide (ICO). However, the present invention is not limited to this and may include the second transparent electrode layer 340 and various other materials.

The second metal electrode layer 342 located on the second transparent electrode layer 340 may include a metal material. The second metal electrode layer 342 may contain metal to improve characteristics such as carrier collection efficiency and resistance reduction. As such, the second metal electrode layer 342 contains metal and can block the incidence of light, so it can have a certain pattern to minimize shading loss. In the second electrode 34, the second metal electrode layer 342 is entirely located only on the second transparent electrode layer 340 and is spaced apart from the second conductive region 32, but only via the first transparent electrode layer 320. It may be electrically connected to the second conductive region 32.

In the first structure 20 as described above, the first intermediate layer 22a may have a relatively thin thickness for carrier movement through the first intermediate layer 22a composed of an insulating film or a dielectric film. And the first conductive region 22 may have a relatively thick thickness so as to sufficiently function as an emitter region. Accordingly, the thickness of the first conductive region 22 may be greater than the thickness of the first intermediate layer 22a. Meanwhile, in the second structure 30, the second intermediate layer 32a and the second conductive region 32 are made of a semiconductor material to facilitate the movement of carriers, so the thickness of the second conductive region 32 is the second thickness. It may be equal to, larger than, or smaller than the thickness of the middle layer 32a. For example, the passivation characteristics can be improved by making the thickness of the second intermediate layer 32a the same as or larger than that of the second conductive region 32. As another example, the thickness of the second conductive region 32 may be greater than the thickness of the second intermediate layer 32a so that the effect of the second conductive region 32 can be implemented more stably.

Here, the thickness of the second intermediate layer 32a may be equal to or greater than the thickness of the first intermediate layer 22a. In particular, the thickness of the second intermediate layer 32a may be greater than the thickness of the first intermediate layer 22a. This is because it is advantageous for the second intermediate layer 32a to have a certain thickness for passivation characteristics, and for the first intermediate layer 22a to have a thin thickness for carrier movement.

More specifically, the thickness of the first intermediate layer 22a may be smaller than the thickness of the other insulating films (each of the anti-reflection film 56 and the rear passivation layer 40, in particular, the other insulating films including an oxide film). For example, the thickness of the first intermediate layer 22a may be 5 nm or less (more specifically, 2 nm or less, for example, 0.5 nm to 2 nm), and other insulating films (anti-reflection film 56, front passivation layer 50) may be used. The thickness of each) may be 50 nm to 100 nm to ensure stable insulating properties. If the thickness of the first intermediate layer 22a exceeds 5 nm, it is difficult for carriers to move and the solar cell 100 may not operate, and if the thickness of the first intermediate layer 22a is less than 0.5 nm, the first intermediate layer ( There may be difficulty in forming 22a). To facilitate carrier movement and dopant diffusion, the first intermediate layer 22a may have a thickness of 2 nm or less (more specifically, 0.5 nm to 2 nm). At this time, the first intermediate layer 22a may have a thickness of 1 nm to 2 nm to facilitate movement of carriers and diffusion of dopants.

Additionally, the thickness of the second intermediate layer 32a may be smaller than the thickness of the other insulating films (each of the anti-reflection film 56 and the rear passivation layer 40). For example, the thickness of the second intermediate layer 32a may be 10 nm or less (more specifically, 0.5 nm to 10 nm). If the thickness of the second intermediate layer 32a exceeds 10 nm, carrier movement may not be smooth, and if the thickness of the second intermediate layer 32a is less than 0.5 nm, it is difficult to form the second intermediate layer 32a with the desired quality. and the passivation characteristics may not be excellent.

Additionally, the thickness of the first conductive region 22 may be equal to or greater than the thickness of the second conductive region 32 . In particular, the thickness of the first conductive type region 22 may be greater than the thickness of the second conductive type region 32. According to this, the photoelectric conversion effect can be maximized by maximizing the volume of the first conductive region 22, which functions as an emitter region. In addition, the deposition rate of the first conductivity type region 22 is greater than the deposition rate of the second conductivity type region 32 and the process conditions of the first conductivity type region 22 are the process conditions of the second conductivity type region 32. Since it is not more stringent, the manufacturing process can be simplified even when the first conductive region 22 has a relatively large thickness.

More specifically, the thickness of the first conductive region 22 may be 350 nm or less. For example, the thickness of the first conductive region 22 may be greater than the thickness of the insulating film (each of the anti-reflection film 56 and the rear passivation layer 40). Accordingly, the effect of the first conductive region 22 can be maximized without excessively increasing the process time.

Additionally, the thickness of the second conductive region 32 may be smaller than the thickness of the insulating film (each of the anti-reflection film 56 and the rear passivation layer 40). For example, the thickness of the second conductive region 32 may be 10 nm or less (more specifically, 0.5 nm to 10 nm). If the thickness of the second conductive region 32 exceeds 10 nm, the process time increases and it may be difficult to maintain the relatively less stable amorphous structure. If the thickness of the second conductive region 32 is less than 0.5 nm, the effect of the second conductive region 32 may not be sufficient.

However, the present invention is not limited to this and includes the first intermediate layer 22a, the second intermediate layer 32a, the first conductive region 22, the second conductive region 32, the anti-reflection film 56, and the rear passivation layer. (40) The thickness of the back may have various values. In the case where the front passivation layer 50 and the front electric field region 52 included in the front structure are each made of a layer made of the same material as the second intermediate layer 32a and the second conductive region 32, the above-described The thickness of the second intermediate layer 32a and the second conductive region 32 and their thickness relationship with other layers can be applied to the front passivation layer 50 and the front electric field region 52 as is.

In the above description, in this embodiment, it is exemplified that the first structure 20 has a tunnel junction structure and the second structure 30 has a heterojunction structure including an amorphous semiconductor material. Accordingly, the first conductive region 22 and the second conductive region 32 may include the same semiconductor material (eg, a single semiconductor material, for example, silicon), but may have different crystal structures. Then, the semiconductor substrate 10 and the first and second conductive regions 22 and 32, which are largely involved in photoelectric conversion, may include the same material, thereby improving stability. However, the bonding structure of the first structure 20 and the second structure 30 is not limited to the above-described structure, and may be modified in various ways while having different bonding structures.

A rear passivation layer (insulating layer) 40 may be provided on the rear surface of the semiconductor substrate 10 to cover at least the rear surface of the semiconductor substrate 10 exposed between the first structure 20 and the second structure 30.

For example, in this embodiment, the rear passivation layer 40 is a semiconductor substrate 10 exposed between the first and second conductive regions 22 and 32 or between the first and second intermediate layers 22a and 32a. ), a portion above the first conductive region 22 excluding the second opening 404 corresponding to the contact portion 242a of the first metal electrode layer 242, and a first conductive region around this region. It can be formed continuously while covering (22). The rear passivation layer 40 covers the first conductive region 22 except for the second opening 404 and is composed of a polycrystalline semiconductor layer, thereby forming a first conductive region 22 whose passivation characteristics may be somewhat reduced. Passivation can be performed stably. In addition, the rear passivation layer 40 has a first opening 402 formed in a portion corresponding to the second intermediate layer 32a and the second conductive region 32. Accordingly, the second intermediate layer 32a and the second conductive region 32 may be entirely located only inside the first opening 402. This is because the second intermediate layer 32a and the second conductive region 32 were selectively formed in this portion after forming the first opening 402. However, the present invention is not limited to this, and the rear passivation layer 40 may be formed in various shapes.

The rear passivation layer 40 may be formed of various materials. More specifically, the rear passivation layer 40 may be composed of an insulating layer including an insulating material. For example, the rear passivation layer 40 is any selected from the group consisting of a silicon nitride film, a hydrogen-containing silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a silicon carbide film, MgF ₂ , ZnS, TiO ₂ and CeO ₂ It may have a single layer structure or a multilayer structure in which two or more layers are combined. As an example, the rear passivation layer 40 may be composed of a silicon nitride film and a silicon carbide film that are sequentially stacked. Then, the silicon nitride film can contain hydrogen and sufficiently and effectively exhibit the effect of hydrogen passivation. In this embodiment, the rear passivation layer 40 is not formed on the first conductivity type region 22 including an amorphous semiconductor, but is formed on the second conductivity type region 32 including a polycrystalline semiconductor, thereby providing hydrogen passivation. Through this, polycrystalline semiconductors can be effectively passivated. However, the present invention is not limited to this and it is also possible not to include a silicon nitride film. The silicon carbide film has excellent acid resistance and chemical resistance, preventing penetration of unwanted impurities and dopants, and can be easily patterned by a laser, so the first and second openings 402 and 404 can be easily and simply formed by a laser. there is.

In this embodiment, a front electric field region 52 is formed on the front side of the semiconductor substrate 10, and a front passivation layer 50 may be further provided between the semiconductor substrate 10 and the front electric field region 52. The front electric field region 52 forms an electric field region that prevents recombination near the front surface of the semiconductor substrate 10, and the front passivation layer 50 can effectively passivate the front surface of the semiconductor substrate 10.

The front electric field region 52 and the front passivation layer 50 may be made of various structures or materials. For example, in this embodiment, the front electric field region 52 may be the same layer having the same material, crystal structure, etc. as the second conductive region 32, and the front passivation layer 50 may be formed of the second intermediate layer 32a and the second intermediate layer 32a. It may be the same layer with the same material, crystal structure, etc. In this case, the descriptions of the second conductive region 32 and the second intermediate layer 32a can be applied as descriptions of the front electric field region 52 and the front passivation layer 50. According to this, in the process of forming the second intermediate layer 32a and the second conductive region 32 located on the rear side, the front passivation layer 50 and the front electric field region 52 located on the front side are simultaneously formed, The process can be simplified. In addition, since a structure based on an amorphous semiconductor is provided on the front surface of the semiconductor substrate 10, excessive light absorption that may occur when a structure based on a polycrystalline semiconductor is provided can be prevented.

However, the present invention is not limited to this. Therefore, the front electric field region 52 is composed of a doped region having the same first or second conductivity type (for example, a second conductivity type) as the base region 110 and a higher doping concentration than the base region 110. It could be. In this case, the front electric field region 52 may form part of the semiconductor substrate 10. Alternatively, the front electric field region 52 may be composed of an undoped layer that does not contain first and second conductivity type dopants and may be formed by being positioned (for example, in contact) on the front surface of the semiconductor substrate 10. This will be described in detail later with reference to FIG. 4 .

Additionally, the transparent conductive film 54 may be positioned (for example, in contact) on the front surface of the semiconductor substrate 10 or on the front electric field area 52 . This transparent conductive film 54 is a floating electrode that is not connected to an external circuit or another solar cell 100. This floating electrode can prevent unnecessary ions, etc. from gathering on the surface of the semiconductor substrate 10. Accordingly, it is possible to prevent deterioration caused by ions, etc. (for example, potential induced degradation (PID), a phenomenon in which the power generation efficiency of the solar cell module is reduced in a high temperature and high humidity environment). Additionally, the transparent conductive film 54 may function as a type of anti-reflection film.

The transparent conductive film 54 may be made of various structures or materials. For example, in this embodiment, the transparent conductive film 54 may be the same layer having the same material, crystal structure, etc. as the first and/or second transparent electrode layers 240 and 340. In this case, the description of the first and/or second transparent electrode layers 240 and 340 may be applied as is to the description of the transparent conductive film 54. According to this, the transparent conductive film 54 located on the front side can be simultaneously formed in the process of forming the first and/or second transparent electrode layers 240 and 340 located on the back side, thereby simplifying the manufacturing process.

This transparent conductive film 54 is not an essential film, and it is possible to not include the transparent conductive film 54.

The anti-reflection film 56 may be positioned (eg, in contact with) on the entire surface of the semiconductor substrate 10 or on the transparent conductive film 54. The anti-reflection film 56 reduces the reflectance of light incident on the front surface of the semiconductor substrate 10. As a result, the amount of light reaching the pn junction formed by the semiconductor substrate 10 and the first structure 20 can be increased. Accordingly, the short circuit current (Isc) of the solar cell 100 can be increased.

The anti-reflection film 56 may be formed of various materials. For example, the anti-reflection film 56 is any one selected from the group consisting of a silicon nitride film, a hydrogen-containing silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a silicon carbide film, MgF ₂ , ZnS, TiO ₂ and CeO ₂ It may have a single layer structure or a multilayer structure combining two or more layers. For example, the anti-reflection film 56 is composed of an MgF ₂ film, so that the anti-reflection effect can be further improved in a structure including the transparent conductive film 54.

The front passivation layer 50, the front electric field region 52, the transparent conductive layer 54, and the anti-reflection layer 56 may be formed substantially on the entire front surface of the semiconductor substrate 10. Here, being formed as a whole includes not only being physically completely formed, but also cases where some parts are inevitably excluded. This simplifies the manufacturing process and allows each layer to fully play its role.

Referring to FIG. 2, in this embodiment, the first intermediate layer 22a and the first conductive region 22, and the second intermediate layer 32a and the second conductive region 32 are each formed long to form a stripe shape. As a result, they are positioned alternately in the direction crossing the longitudinal direction. Between the first intermediate layer 22a and the first conductive region 22 and the second intermediate layer 32a and the second conductive region 32, an unformed conductive region, a trench, an empty space, etc. is formed long enough to space them apart. This is provided.

Additionally, the first electrode 24 may be formed in a stripe shape corresponding to the first conductive region 22, and the second electrode 34 may be formed in a stripe shape corresponding to the second conductive region 32. . The first electrode 42 and the second electrode 34 may be entirely in contact with or connected to the first and second conductive regions 22 and 32, respectively. Accordingly, the contact area between the first and second electrodes 24 and 34 and the first and second conductive regions 22 and 32 can be maximized to improve carrier collection efficiency. Alternatively, parts of the first electrode 42 and the second electrode 34 may be in contact with or connected to the first and second conductive regions 22 and 32, respectively, through contact holes or the like. Various other variations are possible. For clear understanding, the width of the second electrode 34 is shown to be smaller than the width of the second conductive region 32, but the present invention is not limited thereto.

Referring to Figures 1 and 2, when light is incident on the solar cell 100 according to this embodiment, electrons and holes are generated through photoelectric conversion. The generated holes pass through the first intermediate layer 22a and move to the first conductivity type region 22 and are transferred to the first electrode 24, and the generated electrons pass through the second intermediate layer 32a to the second conductivity type region 22. It moves to area 32 and is transmitted to the second electrode 34. Holes and electrons transferred to the first and second electrodes 24 and 34 move to an external circuit or another solar cell 100. This generates electrical energy.

As in this embodiment, the solar cell 100 has a back electrode structure in which the electrodes 24 and 34 are formed on the back of the semiconductor substrate 10 and the electrodes 24 and 34 are not formed on the front of the semiconductor substrate 10. It is possible to minimize shading loss on the front surface of the semiconductor substrate 10. As a result, the efficiency of the solar cell 100 can be improved. However, the present invention is not limited to this. And since the first and second conductive regions 22 and 32 are formed on the semiconductor substrate 10 with the first and second intermediate layers 22a and 32a interposed therebetween, they are composed of a separate layer from the semiconductor substrate 10. do. As a result, loss due to recombination can be minimized compared to the case where the doped region formed by doping the semiconductor substrate 10 with a dopant is used as a conductive region.

At this time, the first structure 20 including the first conductive region 22 and the second structure 30 including the second conductive region 32 have different bonding structures, so that the solar cell 100 The efficiency and characteristics can be effectively improved.

That is, the first structure 20 including the first conductive region 22 constituting the emitter region has a tunnel junction structure to improve carrier mobility, and the first conductive region 22 and the first conductive region 22 have a tunnel junction structure. By improving the contact characteristics of the electrode 24, series resistance can be reduced. And in the dark state, it effectively prevents unwanted minority carriers (e.g., electrons if the first conductivity type region 22 is p-type, holes if it is n-type) from flowing into the first conductivity type region 22. By limiting this, Auger recombination can be reduced and the open-circuit voltage can be greatly improved. In addition, the first structure 20 having a tunnel junction structure is advantageous in the manufacturing process because conditions such as materials and manufacturing process are not strict. Accordingly, the efficiency and productivity of the solar cell 100 can be effectively improved. In particular, the first structure 20, which has a relatively large area and includes a first conductive region 22 constituting the emitter region directly involved in photoelectric conversion, has a tunnel junction structure, so that the above-described effect can be doubled. there is.

In addition, the second structure 30 constituting the rear electric field region has a heterojunction structure containing an amorphous semiconductor material to prevent undesired diffusion of dopants into the interior of the semiconductor substrate 10, thereby improving the efficiency of the solar cell 100. can be improved effectively. In particular, if the second structure 30 including the second conductive region 32 that forms a rear electric field region and improves passivation characteristics has a heterojunction structure including an amorphous semiconductor material, the heterojunction structure has very excellent passivation characteristics. The effect of the joint structure can be doubled. In addition, when the second conductivity type region 32 has an n-type conductivity, the activation energy (solubility) of the n-type dopant is small, so dopant penetration undesirably penetrates into the semiconductor substrate 10 after the heat treatment process. This phenomenon may occur, and the heterojunction structure can effectively prevent unwanted dopant penetration as described above compared to the tunnel junction structure. Moreover, when forming the second structure 30, if the layer constituting at least a part of the second structure 30 is simultaneously formed on the front surface of the semiconductor substrate 10, the amorphous semiconductor layer is formed on the front surface of the semiconductor substrate 10. A front structure is formed. In this way, if the front structure is based on an amorphous semiconductor layer, light absorption is low and it is suitable for improving the efficiency of the solar cell 100. On the other hand, if the front surface agent is based on a polycrystalline semiconductor layer, light absorption is large, so the efficiency of the solar cell may be greatly reduced.

In this way, the efficiency of the solar cell 100 can be improved by specifically limiting the bonding structure of the first and second structures 20 and 30, taking into account the functions, roles, characteristics, etc. of the first and second structures 20 and 30. can be maximized.

Hereinafter, a method of manufacturing the solar cell 100 according to an embodiment of the present invention will be described in detail with reference to FIGS. 3A to 3H.

3A to 3H are cross-sectional views showing a method of manufacturing a solar cell 100 according to an embodiment of the present invention.

First, as shown in FIG. 3A, a first intermediate layer 22a and a first conductive region 22 are formed to correspond to a portion of the rear surface of the semiconductor substrate 10 consisting of the base region 110. Here, the first intermediate layer 22a and the first conductive region 22 may be formed using various methods and processes.

As an example, an insulating film (dielectric film) for the first intermediate layer 22a and an intrinsic amorphous semiconductor layer for the first conductive region 22 are formed entirely on the rear surface of the semiconductor substrate 10. Then, a heat treatment is performed to crystallize the intrinsic amorphous semiconductor layer while doping it with a first conductivity type dopant, thereby performing the doping and crystallization processes together. Through this heat treatment, the amorphous semiconductor layer is changed into a polycrystalline semiconductor layer doped with a first conductivity type dopant. Afterwards, the insulating film and the polycrystalline semiconductor layer doped with the first conductivity type dopant are patterned together to form the first intermediate layer 22a and the first conductivity type region 22 only in the desired area. According to this, the process temperature can be lowered by forming an amorphous semiconductor layer.

The insulating film for the first intermediate layer 22a may be formed through various processes, such as thermal growth (e.g., thermal oxidation), chemical oxidation, deposition (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.) It can be formed by etc. Additionally, the intrinsic amorphous semiconductor layer for the first conductive region 22 may be formed through various processes, such as deposition (eg, chemical vapor deposition). A variety of known methods can be used for doping and crystallization processes. For example, various methods such as ion implantation, heat diffusion using a gas containing a dopant, heat treatment after forming a doping layer, and laser doping may be applied. Various processes (eg, an etching process using an etching solution or an etching paste, etc.), also known as a patterning process of the polycrystalline semiconductor layer doped with the insulating film and the first conductivity type dopant, may be used. However, the present invention is not limited to this and various other processes may be applied.

As another example, an insulating film for the first intermediate layer 22a and an intrinsic polycrystalline semiconductor layer for the first conductive region 22 are formed entirely on the rear surface of the semiconductor substrate 10. Then, a doping process is performed by performing heat treatment to dope the intrinsic polycrystalline semiconductor layer with a first conductivity type dopant. Through this heat treatment, the intrinsic polycrystalline semiconductor layer is changed into a polycrystalline semiconductor layer doped with a first conductivity type dopant. Afterwards, the insulating film and the polycrystalline semiconductor layer doped with the first conductivity type dopant are patterned together to form the first intermediate layer 22a and the first conductivity type region 22 only in the desired area. According to this, the first conductivity type region 22 can have a stable polycrystalline structure by forming an intrinsic polycrystalline semiconductor layer.

As another example, an insulating film for the first intermediate layer 22a and a polycrystalline semiconductor layer doped with a first conductivity type dopant for the first conductivity type region 22 are formed on the rear surface of the semiconductor substrate 10 as a whole. The polycrystalline semiconductor layer doped with the first conductivity type dopant may be formed by providing a base containing the first conductivity type dopant in the process of forming the polycrystalline semiconductor layer (eg, deposition process). Afterwards, the insulating film and the polycrystalline semiconductor layer doped with the first conductivity type dopant are patterned together to form the first intermediate layer 22a and the first conductivity type region 22 only in the desired area.

In the above-described example, patterning is performed after forming the first intermediate layer 22a and the first conductive region 22 as a whole. However, the present invention is not limited to this. Accordingly, the first intermediate layer 22a and the first conductive region 22 may be formed to have a pattern corresponding to a partial region on the rear surface of the semiconductor substrate 10 using a mask or mask layer. According to this, the process can be simplified by not requiring a separate patterning process.

Next, as shown in FIG. 3B, a rear passivation layer 40 is formed entirely on the rear surface of the semiconductor substrate 10 to cover the first intermediate layer 22a and the first conductive region 22. The rear passivation layer 40 may be formed by various methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing, or spray coating.

Subsequently, as shown in FIG. 3C, the rear passivation layer 40 is patterned to correspond to the area where the second intermediate layer 32a and the second conductive region 32 are to be formed. An opening 402 is formed. Then, a texturing structure is formed on the front surface of the semiconductor substrate 10. At this time, the first opening 402 may be formed by laser ablation using a laser, or various methods using an etching solution or etching paste.

Various known processes may be applied as a process for texturing the front surface of the semiconductor substrate 10. For example, the entire surface of the semiconductor substrate 10 may be textured by wet or dry texturing, or reactive ion etching (RIE). In this embodiment, after forming the first intermediate layer 22a and the first conductive region 22, the front surface of the semiconductor substrate 10 is textured, and the semiconductor substrate 10 is protected by the rear passivation layer 40. The full texturing process can be performed in this state. However, the present invention is not limited to this, and the process of texturing the entire surface of the semiconductor substrate 10 may be performed in various orders. For example, a texturing process may be performed on the entire surface before forming the first intermediate layer 22a and the first conductive region 22.

Subsequently, as shown in FIG. 3D, a second intermediate layer 32a and a second conductive region 32 are formed in the first opening 402 on the rear surface of the semiconductor substrate 10. Additionally, a front passivation layer 50 and a front electric field region 52 may be formed entirely on the front surface of the semiconductor substrate 10 .

The second intermediate layer 32a, the second conductive region 32, the front passivation layer 50, and the front electric field region 52 may be formed by various methods. For example, the second intermediate layer 32a, the second conductive region 32, the front passivation layer 50, and the front electric field region 52 may be formed by deposition. More specifically, the second intermediate layer 32a, the second conductive region 32, and the front passivation layer 50 and the front electric field region 52 are formed by depositing a second conductive type dopant after depositing the intrinsic amorphous silicon layer. It can be formed by a continuous process of depositing by additionally providing a dopant gas containing a dopant gas, that is, an in-situ process. According to the deposition process, etc., the second intermediate layer 32a and the second conductive region 32 are partially formed on the rear surface of the semiconductor substrate 10 in the portion exposed by the first opening 402, and separate patterning is required. This is not required.

Here, when the second intermediate layer 32a and the front passivation layer 50 include the same material, the second intermediate layer 32a and the front passivation layer 50 can be formed simultaneously in the same process. When the second conductive region 32 and the front electric field region 52 include the same material, the second conductive region 32 and the front electric field region 52 can be formed simultaneously in the same process. In this case, the manufacturing process can be simplified.

However, the present invention is not limited to this. Accordingly, the second intermediate layer 32a and the front passivation layer 50 may be formed through separate processes, or may have different materials, thicknesses, etc. Additionally, the second conductive region 32 and the front electric field region 52 may be formed through separate processes, or may have different materials, thicknesses, etc. In this case, the formation order of the second intermediate layer 32a, the second conductive region 32, the front passivation layer 50, and the front electric field region 52 may be modified in various ways.

Next, as shown in FIG. 3E, transparent conductive films 54 and 440 are formed on the front and back sides of the semiconductor substrate 10, respectively. Additionally, an anti-reflection film 56 can be formed on the transparent conductive film 54 located on the front side of the semiconductor substrate 10.

More specifically, a transparent conductive film 54 may be formed on the front surface of the semiconductor substrate 10, covering the entire front electric field area 52. On the rear side of the semiconductor substrate 10, the transparent conductive film 440 is a stack of the first intermediate layer 22a, the first conductive region 22, and the rear passivation layer 40, the second intermediate layer 32a, and the second intermediate layer 32a. It can be formed by entirely covering the stack of the two conductive regions 32 and the rear passivation layer 40 located on the semiconductor substrate 10. Here, when the transparent conductive films 54 and 440 include the same material, the transparent conductive films 54 and 440 can be formed simultaneously in the same process. In this case, the manufacturing process can be simplified. However, the present invention is not limited to this, and the transparent conductive films 54 and 440 may be formed through separate processes, or may have different materials, thicknesses, etc. In this case, the formation order of the transparent conductive films 54 and 440 and the anti-reflective film 56 may be modified in various ways.

And the transparent conductive films 54 and 440 and the anti-reflective film 56 may be formed through various processes. For example, the transparent conductive films 54 and 440 may be formed by a deposition method (e.g., chemical vapor deposition (PECVD)), a coating method, etc., and the anti-reflection film 56 may be formed by a vacuum deposition method or a deposition method (e.g., , chemical vapor deposition), spin coating, screen printing, or spray coating. Various other variations are possible.

Subsequently, as shown in FIG. 3F, part of the back passivation layer 40 and the transparent conductive film 440 located on the first conductive region 22 on the back of the semiconductor substrate 10 is removed to form a contact portion ( A portion of the first conductive region 22 corresponding to 242a) is exposed. Various known methods can be used to form the second opening 404 by removing a portion of the rear passivation layer 40 and the transparent conductive film 440 corresponding to the contact portion 242a. For example, the second opening 404 can be formed by various methods using laser ablation, etching paste, etching solution, etc.

For example, in this embodiment, the contact portion 242a is made smaller than the area of the first metal electrode layer (reference numeral 242 in FIG. 3H, hereinafter the same), and the first conductive region 22 is formed by the rear passivation layer 40. This stable passivation was exemplified. As a result, a part of the first metal electrode layer 242 is formed in contact with the first conductive region 22, and the remaining part is formed by patterning the rear passivation layer 40 and the transparent conductive film 440. It is located on the laminate of the electrode layer (reference numeral 240 in FIG. 3h, hereinafter the same). However, the present invention is not limited to this, and the contact portion 242a may have the same shape and size as the first metal electrode layer 242. In this case, the entire first metal electrode layer 242 is in contact with the first conductive region 22, and a rear passivation layer ( 40) and the first transparent electrode layer 240 are located. Various other variations are possible.

Next, as shown in FIG. 3G, a metal film 442 is formed entirely on the rear surface of the semiconductor substrate 10. More specifically, a metal film 442 may be formed on the rear surface of the semiconductor substrate 10 while entirely covering the transparent conductive film 440 and the contact portion 242a of the first conductive region 22. The metal film 442 may be formed by various methods such as plating, deposition, sputtering, and printing.

Subsequently, as shown in FIG. 3H, the transparent conductive film 440 and the metal film 442 are patterned to correspond to the first and second electrodes 24 and 34 to form first and second electrodes 24 having a pattern. , 34). Here, the first electrode 24 may be patterned to have a smaller planar shape than the first intermediate layer 22a and the first conductive region 22. Additionally, the second electrode 34 may be patterned to have the same planar shape as the second intermediate layer 32a and the second conductive region 32. According to this, the second conductive region 32 can be stably protected, and the second electrode 34 connected to the second conductive region 32, which has a relatively small area, is formed with a sufficient area to improve electrical characteristics. can be improved However, the present invention is not limited to this.

In this embodiment, the manufacturing process is simplified by forming the transparent conductive film 440 and the metal film 442 as a whole and then patterning them to form the first and second electrodes 24 and 34. However, the present invention is not limited to this, and it is also possible to form the first and second electrodes 24 and 34 to have a desired pattern using a mask, printing, etc. In addition, various modifications are possible.

According to the manufacturing method of the solar cell 100 described above, the manufacturing process of the solar cell 100 according to this embodiment can be simplified. As a result, the solar cell 100 with excellent characteristics and efficiency can be manufactured with high productivity. However, the present invention is not limited to this, and the manufacturing process sequence and specific methods of the solar cell 100 may be modified in various ways.

Hereinafter, a solar cell and its manufacturing method according to another embodiment of the present invention will be described in detail. Detailed description of parts that are the same or extremely similar to the above description will be omitted, and only different parts will be described in detail. Also, combining the above-described embodiments or modified examples thereof with the following embodiments or modified examples thereof also falls within the scope of the present invention.

Figure 4 is a cross-sectional view schematically showing a solar cell according to another embodiment of the present invention.

Referring to FIG. 4, in the solar cell 100a according to this embodiment, the semiconductor substrate is formed in a portion on one side (eg, back) of the semiconductor substrate 10 where the first and second structures 20 and 30 are not located. An additional electric field forming layer 60 may be provided between (10) and the rear passivation layer (40). The additional electric field forming layer 60 is an undoped layer that does not contain first and second conductivity type dopants, and is a layer with a fixed charge or a layer capable of selectively collecting and/or extracting electrons or holes, and is an electrode (24, 34) may not be connected. This additional electric field forming layer 60 forms an electric field region that prevents recombination near the rear surface of the semiconductor substrate 10 and can assist in the generation of carriers.

Meanwhile, the front electric field region 52a located on (for example, in contact with) the front surface of the semiconductor substrate 10 is an undoped layer that does not include the first and second conductivity type dopants, and is a layer with a fixed charge or an electron or It is a layer that can selectively collect and/or extract holes, and may not be connected to the electrodes 24 and 34. The front electric field region 52a may form an electric field region that prevents recombination near the front surface of the semiconductor substrate 10 . When the front electric field region 52a, which does not contain a dopant, contacts the semiconductor substrate 10, the effect of the front electric field region 52a can be maximized while maintaining excellent passivation characteristics. In addition, the front electric field region 52a described above has less light loss due to light absorption and has a simpler manufacturing process compared to the tunnel junction structure and the heterojunction structure.

In this embodiment, the additional electric field forming layer 60 or the front electric field region 52a may be made of various materials. For example, the additional electric field forming layer 60 may be composed of a compound (eg, a metal oxide), an alkali metal salt or an alkaline earth metal salt, an organic material, a metal, etc.

For example, the additional electric field forming layer 60 or the front electric field region 52a may be an aluminum oxide layer containing aluminum oxide having a fixed charge. Alternatively, a metal oxide layer in which the additional electric field forming layer 60 or the front electric field region 52a can selectively extract and collect electrons or holes, for example, a molybdenum oxide layer, a tungsten oxide layer, a vanadium oxide layer, or a nickel oxide layer. layer, rhenium oxide layer, titanium oxide layer, zinc oxide layer, niobium oxide layer, etc. Alternatively, the additional electric field forming layer 60 or the front electric field region 52a may be a layer including a plurality of the above-described layers.

As another example, the additional electric field forming layer 60 or the front electric field region 52a may be made of an alkali metal salt or alkaline earth metal salt material that can selectively extract and collect electrons, such as LiFx, KFx, CsFx, or MgFx.

As another example, the additional electric field forming layer 60 or the front electric field region 52a is made of an organic material capable of selectively extracting and/or collecting holes, such as poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate). )(Poly(3,4-Ethylene Di Oxy Thiophene):Poly(Styrene-Sulfonate, PEDOT:PSS), Polytriarylamine (PTAA), Poly-3-hexylthiophene (P3HT) ), etc. Alternatively, the additional electric field forming layer 60 or the front electric field region 52a may be made of an organic material capable of selectively extracting and/or collecting electrons. tris(8-hydroxyquinolino)aluminum, Alq3), Yb, tris(4-carbazoyl-9-ylphenyl)amine (TCTA), 4,4'-bis( Carbazoyl-9-yl)biphenyl (4,4'-Bis(carbazol-9-yl)biphenyl, CBP), 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline ( 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline, BCP), etc.

As another example, the additional electric field forming layer 60 or the front electric field region 52a may include a metal material capable of selectively extracting and/or collecting electrons, such as Ca/Al.

The additional electric field forming layer 60 and the front electric field region 52a may have the same material, composition, etc., or may have different materials, composition, etc. If the additional electric field forming layer 60 and the front electric field region 52a are formed of the same layer, the manufacturing process can be simplified by forming them together in the same process. If the additional electric field forming layer 60 and the front electric field area 52a have different materials, compositions, etc. or are formed in different processes, the characteristics required for the additional electric field forming layer 60 formed on the back and the front electric field area formed on the front ( A variety of materials can be selected taking into account the properties required for 52a). For example, the additional electric field forming layer 60 may be formed of a material having excellent reflectivity, and the front electric field region 52a may be formed of a material having excellent transmittance.

This additional electric field forming layer 60 or the front electric field area 52a may be formed to have excellent ohmic contact, low contact resistivity, etc. The additional electric field forming layer 60 or the front electric field area 52a is not a part connected to the electrodes 24 and 34, but if it has excellent ohmic contact, low contact resistance, etc., the electric field forming effect and carrier generation assistance effect can be excellent. .

As described above, if the additional electric field forming layer 60 or the front electric field region 52a is composed of an undoped layer that does not contain the first and second conductivity type dopants, the passivation characteristics can be improved, thereby reducing the effect caused by the electric field region. It can be sufficiently implemented. In addition, the manufacturing process is simple, the manufacturing cost is low, and the freedom of material selection is improved, making it easier to match the energy level. In the above description, it is exemplified that the additional electric field forming layer 60 and the front electric field region 52a are each composed of an undoped layer that does not contain the first and second conductivity type dopants, but the present invention is not limited thereto. Accordingly, at least one of the additional electric field forming layer 60 and the front electric field region 52a may be composed of an undoped layer that does not include the first and second conductivity type dopants. For example, an additional electric field forming layer 60 is formed on the back of the semiconductor substrate 10, and a front passivation layer 52 containing a dopant is formed on the front of the semiconductor substrate 10, as in the embodiment referring to FIG. 1. It may also include a front electric field area 52, a transparent conductive film 54, an anti-reflection film 56, etc. Additionally, the additional electric field forming layer 60 may be composed of an amorphous semiconductor layer containing a first or second conductivity type dopant. However, according to this, the passivation characteristics may be somewhat deteriorated due to the dopant.

And in FIG. 4, it is illustrated that the additional electric field forming layer 60 includes a first layer 62 with holes as majority carriers and a second layer 64 with electrons as majority carriers. Here, the number of first layers 62 may be equal to or greater than the number of second layers 64, or the total area of first layers 62 may be equal to the total area of second layers 64. It could be bigger than that. For example, the number of first layers 62 may be greater than the number of second layers 64, or the total area of the first layer 62 may be greater than the total area of the second layer 64. According to this, the effect of assisting the generation of majority carriers in the first conductivity type region 22 by the first layer 62 having the same majority carriers as the majority carriers of the first conductivity type region 22 functioning as an emitter region. can be improved. However, the present invention is not limited to this. As another example, the number of second layers 64 may be greater than the number of first layers 62, or the total area of the second layer 64 may be greater than the total area of the first layer 62. Alternatively, only the first layer 62 may be provided and the second layer 64 may not be provided, or only the second layer 64 may be provided and the first layer 62 may not be provided. Various other variations are possible.

The additional electric field forming layer 60 is formed before or after the formation of the first intermediate layer 22a and the first conductive region 22, and before the formation of the second intermediate layer 32a and the second conductive region 32, and the rear passivation layer It may be formed prior to the formation of layer 40. The front electric field region 52a may be formed through various processes. If the additional electric field forming layer 60 and the front electric field region 52a are made of the same material, composition, etc., they can be formed together in the same process to simplify the manufacturing process. The additional electric field forming layer 60 or the front electric field region 52a may be formed by various methods. For example, it may be formed by deposition.

The features, structures, effects, etc. described above are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. illustrated in each embodiment can be combined or modified and implemented in other embodiments by a person with ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to such combinations and modifications should be construed as being included in the scope of the present invention.

100: solar cell
10: Semiconductor substrate
20: first structure
22a: first intermediate layer
22: First conductive region
24: first electrode
30: second structure
32a: second intermediate layer
32: Second conductive area
34: second electrode
40: rear passivation layer
50: Front passivation layer
52: front electric field area
54: Transparent conductive film
56: Anti-reflective film

Claims (20)

semiconductor substrate;
a first structure formed on one surface of the semiconductor substrate to generate and collect first carriers;
A second structure is formed separately from the first structure on one surface of the semiconductor substrate and generates and collects second carriers.
Including,
The first structure has a tunnel junction structure,
The second structure has a heterojunction structure including an amorphous semiconductor material,
The first structure includes a first conductivity type region having a first conductivity type, and a first electrode connected to the first conductivity type region,
The second structure includes a second conductivity type region having a second conductivity type opposite to the first conductivity type, and a second electrode connected to the second conductivity type region,
The first conductivity type region is composed of a polycrystalline semiconductor layer having a polycrystalline structure,
The second conductive region is composed of an amorphous semiconductor layer having an amorphous structure,
The first structure and the second structure have different bonding structures,
The thickness of the first conductive type region is greater than the thickness of the second conductive type region. solar cells. According to paragraph 1,
The first structure includes a first conductivity type region having a first conductivity type, and a first electrode connected to the first conductivity type region,
The second structure includes a second conductivity type region having a second conductivity type opposite to the first conductivity type, and a second electrode connected to the second conductivity type region,
A solar cell in which the first conductivity type region and the second conductivity type region include the same semiconductor material but have different crystal structures. According to paragraph 2,
The first structure further includes a first intermediate layer located between the semiconductor substrate and the first conductive type region,
The second structure further includes a second intermediate layer positioned between the semiconductor substrate and the second conductive type region,
The first intermediate layer and the second intermediate layer are different from each other in at least one of material and thickness. According to paragraph 2,
The connection structure of the first conductive region and the first electrode is different from the connection structure of the second conductive region and the second electrode, or
The stacked structure of the first electrode and the stacked structure of the second electrode are different from each other, or
A solar cell in which the materials of the first electrode and the materials of the second electrode are different from each other. delete delete delete According to paragraph 1,
It further includes at least one of a passivation layer covering one side of the semiconductor substrate and an anti-reflection layer covering the other side of the semiconductor substrate between the first structure and the second structure,
The thickness of the first conductive region is greater than the passivation layer or the anti-reflection film,
A solar cell in which the thickness of the second conductive region is smaller than that of the passivation layer or the anti-reflection film. semiconductor substrate;
a first structure formed on one surface of the semiconductor substrate to generate and collect first carriers;
A second structure is formed separately from the first structure on one surface of the semiconductor substrate and generates and collects second carriers.
Including,
The first structure has a tunnel junction structure,
The second structure has a heterojunction structure including an amorphous semiconductor material,
The first structure includes a first conductive type region having a first conductivity type, and a first electrode connected to the first conductive type region,
The second structure includes a second conductivity type region having a second conductivity type opposite to the first conductivity type, and a second electrode connected to the second conductivity type region,
The first conductive region is composed of a polycrystalline semiconductor layer having a polycrystalline structure,
The second conductive region is composed of an amorphous semiconductor layer having an amorphous structure,
The first electrode includes a first metal electrode layer in direct contact with the first conductive region,
A solar cell wherein the second electrode includes a transparent electrode layer made of a transparent conductive oxide directly contacting the second conductive type region and a second metal electrode layer located on the transparent electrode layer. According to clause 9,
A solar cell wherein a portion of the first metal electrode layer is in direct contact with a portion of the first conductive region, and another portion is located on at least one of a passivation layer and another transparent electrode layer. According to clause 9,
The transparent electrode layer is in direct contact with the second conductive region as a whole,
A solar cell in which the second metal electrode layer is entirely in direct contact with the transparent electrode layer. According to claim 1 or 9,
The first structure further includes a first intermediate layer located between the semiconductor substrate and the first conductive type region,
The second structure further includes a second intermediate layer positioned between the semiconductor substrate and the second conductive type region,
A solar cell wherein the first intermediate layer is composed of an oxide film, and the second intermediate layer is composed of an intrinsic amorphous silicon layer. According to clause 12,
The first intermediate layer and the first conductive region have the same planar shape,
A solar cell wherein the second intermediate layer and the second conductive region have the same planar shape. According to clause 12,
A solar cell in which the thickness of the second intermediate layer is equal to or greater than the thickness of the first intermediate layer. According to claim 1 or 9,
The semiconductor substrate has a second conductivity type,
The area of the first conductive type region is larger than the area of the second conductive type region,
The first conductivity type is p-type,
A solar cell wherein the second conductivity type is n-type. According to claim 1 or 9,
The first structure includes a first conductivity type region having a first conductivity type, and a first electrode connected to the first conductivity type region,
The second structure includes a second conductivity type region having a second conductivity type opposite to the first conductivity type, and a second electrode connected to the second conductivity type region,
A solar cell in which the first conductive region and the second conductive region are spaced apart from each other and a trench or empty space is located between them. According to clause 16,
A solar cell in which an additional electric field forming layer that does not contain a dopant is provided in a portion of the semiconductor substrate where the first and second structures are not located. A first structure for generating and collecting first carriers on one surface of the semiconductor substrate and a second structure formed separately from the first structure for generating and collecting second carriers,
In the method of manufacturing a solar cell, the first structure and the second structure have different bonding structures,
The first structure has a tunnel junction structure,
The second structure has a heterojunction structure including an amorphous semiconductor material,
The first structure includes a first conductivity type region having a first conductivity type, and a first electrode connected to the first conductivity type region,
The second structure includes a second conductivity type region having a second conductivity type opposite to the first conductivity type, and a second electrode connected to the second conductivity type region,
The first conductivity type region is composed of a polycrystalline semiconductor layer having a polycrystalline structure,
The second conductive region is composed of an amorphous semiconductor layer having an amorphous structure,
A method of manufacturing a solar cell in which the thickness of the first conductivity type region is greater than the thickness of the second conductivity type region. delete According to clause 18,
forming a first intermediate layer and the first conductive type region on one surface of the semiconductor substrate;
forming a second intermediate layer and the second conductive type region on one surface of the semiconductor substrate;
forming a transparent conductive film on one surface of the semiconductor substrate to entirely cover the first intermediate layer and the first conductive type region, the second intermediate layer and the second conductive type region;
forming an opening by removing a portion of the transparent conductive film to expose at least a portion of the first conductive type region;
forming a metal film on one surface of the semiconductor substrate to entirely cover the first intermediate layer, the first conductive region, the second intermediate layer, the second conductive region, and the transparent conductive film; and
Patterning the transparent conductive film and the metal film to form a first electrode and a second electrode.
Including,
Forming the first structure including the first intermediate layer, the first conductive region and the first electrode, and the second structure including the second intermediate layer, the second conductive region and the second electrode. Method for manufacturing solar cells.

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