KR102473522B1 - Display device and method of driving the same - Google Patents

Abstract

According to the present invention, a power control unit capable of analyzing an image signal and controlling the current value of the output buffer unit of the data driver according to the complexity of the image signal is provided.
Accordingly, the current value of the output buffer unit is reduced for an image signal having a low complexity, and the current value of the output buffer unit is increased for an image signal having a high complexity. It is possible to reduce power consumption while maintaining reliability.

Description

Display device and its driving method {DISPLAY DEVICE AND METHOD OF DRIVING THE SAME}

The present invention relates to a display device and a driving method thereof, and more particularly, to a display device capable of reducing power consumption and a driving method thereof.

Recently, as society enters the information age in earnest, the display field for processing and displaying a large amount of information has developed rapidly, and in response to this, various flat panel displays (FPDs) have been developed and are in the spotlight. , Examples of flat panel display devices include a liquid crystal display device (LCD device), a plasma display panel device (PDP device), and an organic light emitting diode device (OLED device). can be heard

In general, a display device includes a display panel for displaying an image and a driver for supplying a plurality of signals to the display panel. It includes a gate driver and a data driver for generating gate signals and data signals using signals.

1 is a diagram schematically illustrating a general display device.

As shown in FIG. 1, the display device 10 outputs a gate control signal (GCS) and a data control signal (DCS) for controlling the driving of the gate driver 12 and the data driver 13, The timing control unit 11 outputs the image signal received from the system unit as digital image data (R, G, B) in frame units, and the gate signal to each gate line GL of the display panel 14 The gate driver 12 for supplying , the data driver 13 for supplying pixel signals to each data line DL of the display panel 14 , and the display panel 14 driven by the gate signal and the pixel signal include

The timing controller 11 generates a gate control signal GCS for controlling the gate driver 12 and a data control signal DCS for controlling the data driver 13 using the timing signal TS supplied from the system. print out

In addition, the timing control unit 11 converts the image signal received from the system unit into frame-unit digital image data (R, G, B) and supplies it to the data driver 13.

Examples of the gate control signal (GCS) include a gate start pulse (GSP), a gate shift clock (GSC), and a gate out enable (GOE), and examples of the data control signal (DCS) include a source start pulse (SSP). ), source shift clock (SSC), source out enable (SOE), and polarity signal (POL).

The gate driver 12 sequentially supplies a gate signal to the gate line GL in response to the gate control signal GCS input from the timing controller 11, and thereby the thin film transistor connected to the gate line GL ( TFT) is driven in units of gate lines.

Here, the data driver 13 converts the digital video data (RGB) serially input from the timing controller 11 into a parallel system, converts the analog data voltage using a gamma compensation voltage, and supplies it to the data line DL. do.

However, the data driver 13 includes a plurality of buffers, and the bias current value of each of the plurality of buffers is fixed regardless of the type of the image signal, so that more than necessary current consumption is consumed, and thus the display device 10 A problem arises in that power consumption increases.

The present invention has been proposed to solve this problem, and a display capable of reducing power consumption of a display device by analyzing an image signal and controlling a bias current value of an output buffer in response to the complexity of the image signal. There is a problem in providing an apparatus and a driving method thereof.

In order to achieve the above object, the present invention provides a display panel in which a plurality of data wires and a plurality of gate wires intersect in a matrix form, pixels are defined at the intersection, and display an image corresponding to an image signal. A display device including a data driver connected to the plurality of data lines, a gate driver connected to the plurality of gate lines, and a power control unit controlling power consumption of an output buffer according to the complexity of the image signal. .

The data driver may include the output buffer connected to the plurality of data lines, and the power controller may vary a bias current value of the output buffer of the data driver according to the complexity of the image signal.

Here, the complexity of the image signal may be the sum of differences in grayscale values of adjacent pixels.

And, as the complexity of the image signal decreases, the bias current value of the output buffer may decrease.

Also, as the complexity of the image signal increases, the bias current value of the output buffer may increase.

Here, the power control unit includes a receiver for receiving the video signal from the outside, a storage unit for storing the video signal received from the receiver, an analyzer for analyzing the complexity of the video signal, and power control according to the complexity. It may include an output unit that outputs a signal.

Meanwhile, the present invention includes the step of supplying a gate signal by a gate driver, the step of supplying a data signal by a data driver, the step of receiving an image signal by a power controller, and the steps of the power controller outputting an image according to the complexity of the image signal. A method of driving a display device including controlling power consumption of a buffer and displaying an image using the gate signal and the data signal on a display panel.

Here, the step of controlling the power consumption of the output buffer according to the complexity of the video signal by the power control unit includes the step of varying the bias current value of the output buffer of the data driver unit by the power control unit according to the complexity of the video signal. can include

Also, the complexity of the image signal may be the sum of differences in grayscale values of adjacent pixels.

In addition, the bias current value of the output buffer may decrease as the complexity of the image signal decreases.

Also, as the complexity of the image signal increases, the bias current value of the output buffer may increase.

In the present invention, power consumption can be reduced by controlling the bias current value of the output buffer in response to the complexity of the video signal.

1 is a diagram schematically illustrating a general display device.
2 is a diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.
3 is a schematic block diagram of a power control unit of a display device according to an exemplary embodiment of the present invention.
4 is a diagram schematically illustrating a data driving unit of a display device according to an exemplary embodiment of the present invention.
5 is an exemplary diagram of a control unit of a display device according to an embodiment of the present invention.
6 is a table comparing power consumption for each pattern of a conventional display device and a display device according to an exemplary embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

2 is a diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.

As shown in FIG. 2 , the display device 100 according to an embodiment of the present invention includes a display panel 140 displaying an image (image) according to input image data and driving the display panel 140. It includes a circuit unit and a system unit 160 that transmits a signal to the driving circuit unit.

Although not shown, the power supply may further include a power supply unit that receives an input power supply voltage (VIN) from an external power supply unit, generates a plurality of output power voltages, and supplies them to the data driving unit 130 and the gate driving unit 120 .

Here, the driving circuit unit includes a gate driver 120 , a data driver 130 , a timing controller 110 and a power controller 150 .

The display device 100 of the present invention may be a liquid crystal display device (LCD device) or an organic light emitting diode display device (LED display device). The case of a liquid crystal display device will be described as an example.

The display panel 140 may include a lower substrate and an upper substrate bonded together to face each other, and a liquid crystal layer formed between the lower substrate and the upper substrate.

Also, a lower polarizing film may be disposed on a rear surface of the lower substrate, and an upper polarizing film may be disposed on an upper surface of the upper substrate.

Here, the upper substrate may include a color filter for displaying a color image by converting light incident through the pixels P of the lower substrate into color light.

Also, the lower substrate may include a plurality of gate lines GL and a plurality of data lines DL.

Here, a pixel (P) is defined by the intersection of the gate line (GL) and the data line (DL), and each pixel (P) includes a thin film transistor (Tp), a storage capacitor (Cs), and a liquid crystal capacitor. (Cl).

The thin film transistor (Tp) is switched by a gate signal supplied through the gate line (GL), and when the thin film transistor (Tp) is turned on, the data voltage supplied through the data line (DL) is applied to the pixel (P). supply

In addition, the display panel 140 includes a pixel electrode for applying a data voltage to the pixel P and a common electrode for applying a common voltage. Here, the pixel electrode may be formed on the lower substrate, and the common electrode may be formed on the lower substrate or the upper substrate.

In the display panel 140, an arrangement state of liquid crystals is changed by an electric field difference between a data voltage and a common voltage, and an image is displayed by adjusting the transmittance of light incident from a backlight unit (not shown) by adjusting the arrangement of the liquid crystals.

Meanwhile, the system unit 160 may supply an image signal and a timing signal TS to the timing controller 110 .

Here, the timing signal TS may include a clock signal CLK, horizontal and vertical synchronization signals Hsync and Vsync, gate and data enable signals GE and DE, and the like.

The data enable signal DE represents the period for supplying data to the pixel P, the horizontal synchronization signal Hsync represents the time required to display one line of the screen, and the vertical synchronization signal Vsync represents one frame. represents the time required to display the screen of , and the clock signal CLK represents a signal serving as a reference for generating various signals by synchronizing the gate and data driver 120 and 130 with the timing controller 110 .

Also, the timing controller 110 uses the timing signal TS transmitted from the system unit 160 to generate a gate control signal GCS for controlling the gate driver 120 and data for controlling the data driver 130. A control signal DCS may be generated.

In addition, the timing controller 110 may convert the image signal received from the system unit 160 into frame-unit digital image data R, G, and B and supply the converted image signal to the data driver 130 .

The gate control signal GCS is supplied to the gate driver 120 and the data control signal DCS is supplied to the data driver 130 .

Here, the gate control signal GCS may include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), and the like.

Here, the gate start pulse GSP is a signal applied to a shift register generating the first gate pulse among a plurality of shift registers constituting the gate driver 120 to control the generation of the first gate pulse, and is a gate shift clock. (GSC) is a clock signal commonly input to all shift registers and is a clock signal for shifting the gate start pulse (GSP).

Also, the gate output enable (GOE) controls outputs of the shift registers to prevent the thin film transistors (Tp) corresponding to different horizontal sections from overlapping and turning on.

Also, the data control signal DCS may include a source start pulse (SSP), a source sampling clock (SSC), a source output enable (SOE), and the like.

Here, the source start pulse (SSP) is a signal that controls the data sampling start timing of the data driver 130, and the source sampling clock (SSC) corresponds to a rising or falling edge for each driving IC constituting the data driver 130 It is a clock signal that controls the sampling timing of data in .

Also, the source output enable (SOE) may play a role of controlling the output timing of the data driver 130 .

The gate driver 120 drives (On-Off) the thin film transistors Tp formed in each pixel P of the display panel 140 based on the gate control signal GCS supplied from the timing controller 110. generate a gate signal. The generated gate signal may be sequentially supplied to the plurality of gate lines GL.

The data driver 130 sequentially receives the digital image data (R, G, and B) supplied from the timing controller 110 and converts them into analog image data (data voltage) by referring to the reference voltage to display the display panel 140. can be supplied to each pixel P of

At this time, the data voltage is supplied to the display panel 140 based on the data control signal DCS supplied from the timing controller 110 .

In particular, the display device 100 according to an embodiment of the present invention may include a power control unit 150 that receives an image signal from the system unit 160 .

Here, the power control unit 150 analyzes the complexity of the image signal and outputs a power control signal (PCS) according to the complexity of the image signal to reduce the power consumption of the output buffer of the driver. You can control it.

3 is a schematic block diagram of a power control unit of a display device according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the power control unit 150 includes a receiver 151 that receives an image signal from the system unit (160 in FIG. 2) and an image signal received from the receiver 151. A storage unit 153 for storing , an analysis unit 155 for analyzing the complexity of the stored image signal, and a power control signal (PCS) according to the complexity of the image signal. An output unit 157 outputting to the driving unit may be included.

Here, a case in which the driving unit controlled by the power control signal (PCS) is a data driving unit (130 in FIG. 2) will be described as an example, but it is not limited thereto, and the gate driving unit (120 in FIG. 2) is a power control signal ( PCS) may be controlled.

Specifically, the receiving unit 151 of the power control unit 150 receives an image signal transmitted from the system unit ( 160 in FIG. 2 ). Also, the input image signal may be stored in the storage unit 153 of the power control unit 150 .

Also, the analysis unit 155 of the power control unit 150 may calculate complexity according to a gray difference between adjacent pixels (P in FIG. 2 ) in a specific Nth frame.

For example, the complexity can be calculated by summing the differences in grayscale values of pixels (P in FIG. 2 ) disposed above, below, left, and right adjacent to a specific pixel (P in FIG. 2 ) of the N-th frame.

That is, the case of high complexity means a case where the output current is very large and a high voltage and a large amount of current are required. may be a smear pattern that alternates in units of 2 pixels.

Also, the output unit 150 may output the power control signal PCS of a specific frame according to complexity.

That is, the power control signal (PCS) according to the complexity is determined in advance, and the output unit 157 can output the power control signal (PCS) in response to the complexity calculated by the analysis unit 155 of the power control unit 150. have.

Here, the power control signal (PCS) may be composed of 3 bits such as '000' to '111', but is not limited thereto, and may be composed of various bits according to the size and resolution of the display device.

In addition, the complexity may be calculated according to the gray difference between adjacent pixels (P in FIG. 2) in the specific Nth frame and output as a power control signal (PCS) in the N+1 frame. .

Such a power control signal (PCS) is transmitted to the data driver (130 in FIG. 2) so that the bias current value of the output buffer of the data driver (130 in FIG. 2) can be adjusted.

That is, the power control signal (PCS) can be controlled to reduce the bias current value of the output buffer of the data driver (130 in FIG. 2) when the complexity of the image signal is small, and the image signal It is a signal that can be controlled to increase the bias current value of the output buffer of the data driver (130 in FIG. 2) when the complexity of is large.

4 is a diagram schematically illustrating a data driving unit of a display device according to an exemplary embodiment of the present invention.

As shown in FIG. 4, a serial/parallel converter and control logic unit 131 convert serial data of digital image data (R, G, B) supplied from the timing controller (110 in FIG. 2) into parallel data and output the converted parallel data. ), and a 2-line latch 133 that sequentially stores data input from the serial/parallel converter and control logic unit 131 and then outputs the stored data to the D/A converter 135, and the 2-line latch A D/A converter 135 converts the digital image data (R, G, B) input from 133 into analog image signals and outputs them, and the analog image signals converted by the D/A converter 135 are buffered. An output buffer unit 137 that amplifies and outputs the output buffer unit 137 and a control unit 139 for controlling power of the output buffer unit 137 may be included.

Specifically, the serial/parallel converter and control logic unit 131 converts serial data of digital image data (R, G, B) input from the outside into parallel data and transfers it to the 2-line latch unit 133 side. can be performed.

Also, the two-line latch unit 133 may substantially include a sampling latch unit and a holding latch unit.

Here, the sampling latch unit may sequentially store digital image data (R, G, and B) received from the serial/parallel converter and the control logic unit 131 .

To this end, the sampling latch unit may include a predetermined number of sampling latches.

Also, the holding latch unit may receive and store digital image data (R, G, and B) from the sampling latch unit and output them to the D/A converter 135. To this end, the holding latch unit may also include a predetermined number of holding latches.

The D/A converter 135 is composed of a number of D/A converters 135 substantially corresponding to the number of channels, and they transmit digital image data (R, G, B) input from the holding latch unit to the gamma reference voltage generator. It can be converted into an analog video signal using the reference voltage of .

Also, the output buffer unit 137 may buffer-amplify and output the analog video signal converted by the D/A converter 135. Here, the output buffer unit 137 may include a plurality of output buffers respectively connected to a plurality of data lines.

In particular, the control unit 139 of the display device (100 in FIG. 2) according to an embodiment of the present invention is provided in the data driver 130 to control the power of the output buffer unit 137, and the output buffer unit 137 It has a feature that power consumption in the output buffer unit 137 is controlled by controlling the amount of current applied to .

The controller 139 may be built into the data driver 130 composed of a data drive IC or may be composed of a separate integrated circuit (IC).

Also, the control unit 139 is composed of various types of switches and can output currents having various types of current values.

For example, when the power control signal (PCS) of the present invention is composed of 3 bits, the controller 139 can be switched to 8 modes of 2³. When the power control signal PCS is composed of 1 bit, the controller 139 may switch only to two modes (low power driving mode and normal driving mode).

However, it is not limited thereto, and the mode of the power control signal (PCS) bit and the control unit 139 may be variously changed.

5 is an exemplary diagram of a control unit of a display device according to an embodiment of the present invention.

As shown in FIG. 5, the power control signal (PCS) of the display device (100 in FIG. 2) according to the embodiment of the present invention is composed of 3 bits, and the controller 139 is 8 modes with 2³. The case of switching to will be described as an example.

That is, the controller 139 may include 8 switches M1 to M8 connected to resistors, and each switch is connected to be driven according to 8 different power control signals 000-111. has been

Here, since the voltage value (Vin) applied to the control unit 139 is constant, and the expression I = V / R is established between the resistance and the current, which switch (M1 to M8) among the eight switches (M1 to M8) Depending on how many switches M1 to M8 are selected, the resistance value inside the control unit 139 varies.

Therefore, the value of the current applied from the control unit 139 to the output buffer unit (137 in FIG. 4) varies depending on which switch (M1 to M8) or how many switches (M1 to M8) in the control unit 139 are selected. Accordingly, the power consumption consumed in the output buffer unit (137 in FIG. 4) also changes, and eventually, the power consumption consumed in the data driver (130 in FIG. 4) changes.

That is, the control unit 139 outputs different resistance values and current values by selecting at least one of the switches M1 to M8 according to the received power control signals 000 to 111, thereby outputting Power consumption consumed by the data driver (130 in FIG. 4) including the buffer unit (137 in FIG. 4) can be controlled.

6 is a table comparing power consumption for each pattern of a conventional display device and a display device according to an exemplary embodiment of the present invention.

As shown in FIG. 6, the power consumption (mW) is shown in the white pattern and black pattern according to the minimum and maximum values of the current applied to the output buffer unit (137 in FIG. 4). .

In the conventional display device (10 in FIG. 1), the value of the current applied to the output buffer is driven at the maximum value (meaning the current when the complexity of the video signal is the highest) for driving reliability regardless of the complexity of the video signal. Therefore, about 99.5mW of power was consumed in the white pattern, and about 86.4Mw of power was consumed in the black pattern.

On the other hand, the display device (100 in FIG. 2) according to an embodiment of the present invention can drive the value of the current applied to the output buffer unit (137 in FIG. 4) to the minimum value in the white pattern and the black pattern. In this case, about 71.2mW of power was consumed in the white pattern, and about 63.2Mw was consumed in the black pattern.

As such, the display device (100 in FIG. 2) according to an embodiment of the present invention analyzes the image signal and determines the data driver (130 in FIG. 4) according to the complexity of the image signal. Since the current value of the output buffer unit (137 in FIG. 4) can be controlled, the current value of the output buffer unit (137 in FIG. 4) is reduced for an image signal with low complexity, and the complexity ( For an image signal with high complexity, the current value of the output buffer unit (137 in FIG. 4) is increased to maintain the reliability of the display device (100 in FIG. 2) and reduce power consumption.

100: display device 110: timing control unit
120: gate driving unit 130: data driving unit
140: display panel 150: power control unit
160: system unit TS: timing signal
DCS: data control signal GCS: gate control signal
Image Signal: Video signal R, G, B: Digital video data
PCS: power control signal Tp: thin film transistor
Cl: liquid crystal capacitor Cs: storage capacitor
P: Pixel GL: Gate wiring
DL: data wiring

Claims (13)

a display panel in which a plurality of data wires and a plurality of gate wires intersect in a matrix form, a plurality of pixels are defined at intersections, and displays an image corresponding to an image signal;
a data driver including an output buffer having a plurality of output buffers respectively connected to the plurality of data lines;
a gate driver connected to the plurality of gate wires; and
A power control unit for controlling power consumption of the plurality of output buffers of the output buffer unit by outputting a power control signal according to the complexity of the video signal.
including,
The data driver further includes a control unit adjusting bias current values applied to the plurality of output buffers of the output buffer unit according to the power control signal,
The complexity of the image signal is the sum of differences in grayscale values of pixels disposed above, below, left, and right adjacent to one of the plurality of pixels.
delete delete According to claim 1,
A display device wherein bias current values of the plurality of output buffers of the output buffer unit decrease as the complexity of the image signal decreases.
According to claim 1,
A display device wherein bias current values of the plurality of output buffers of the output buffer unit increase as the complexity of the image signal increases.
According to claim 1,
The power control unit,
a receiver for receiving the video signal from the outside;
a storage unit for storing the image signal received from the receiver;
an analyzer to analyze the complexity of the video signal;
An output unit for outputting the power control signal according to the complexity
A display device including a.
supplying a gate signal by a gate driver;
supplying data signals to a data driver including an output buffer having a plurality of output buffers respectively connected to a plurality of data wires;
receiving a video signal by a power control unit;
controlling, by the power control unit, power consumption of a plurality of output buffers of the output buffer unit of the data driver unit by outputting a power control signal according to the complexity of the image signal;
Displaying an image by a display panel using the gate signal and the data signal
including,
The data driver further includes a control unit adjusting bias current values applied to the plurality of output buffers of the output buffer unit according to the power control signal,
The complexity of the image signal is the sum of differences in grayscale values of pixels disposed above, below, left, and right adjacent to one of the plurality of pixels.
delete delete According to claim 7,
A method of driving a display device in which bias current values of the plurality of output buffers of the output buffer unit decrease as the complexity of the image signal decreases.
According to claim 7,
A method of driving a display device in which bias current values of the plurality of output buffers of the output buffer unit increase as the complexity of the image signal increases.
According to claim 1,
The power control signal is composed of N bits,
The control unit is a display device that is switched to 2 ^N modes.
According to claim 12,
The controller includes ^2N resistors and ^2N switches respectively connected to the ^2N resistors, receives a constant voltage value, and selects at least one of the ^2N switches according to the power control signal. and applying the bias current value, which changes when an internal resistance value is changed by at least one of the 2 ^N resistors, to the plurality of output buffers of the output buffer unit.

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