KR102471283B1 - Electronic component, connector, connector production method, and electronic component connecting method - Google Patents

Electronic component, connector, connector production method, and electronic component connecting method Download PDF

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Publication number
KR102471283B1
KR102471283B1 KR1020227024835A KR20227024835A KR102471283B1 KR 102471283 B1 KR102471283 B1 KR 102471283B1 KR 1020227024835 A KR1020227024835 A KR 1020227024835A KR 20227024835 A KR20227024835 A KR 20227024835A KR 102471283 B1 KR102471283 B1 KR 102471283B1
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South Korea
Prior art keywords
bump
side edge
region
bump region
output
Prior art date
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KR1020227024835A
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Korean (ko)
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KR20220107072A (en
Inventor
겐이치 히라야마
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데쿠세리아루즈 가부시키가이샤
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Priority claimed from JP2013264377A external-priority patent/JP6434210B2/en
Priority claimed from JP2014162480A external-priority patent/JP6457214B2/en
Application filed by 데쿠세리아루즈 가부시키가이샤 filed Critical 데쿠세리아루즈 가부시키가이샤
Priority to KR1020227040690A priority Critical patent/KR102514158B1/en
Publication of KR20220107072A publication Critical patent/KR20220107072A/en
Application granted granted Critical
Publication of KR102471283B1 publication Critical patent/KR102471283B1/en

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)

Abstract

입력 범프 영역과 출력 범프 영역에 면적차를 가짐과 함께 비대칭으로 배치되어 있는 전자 부품에 있어서도 열압착 헤드에 의한 압력차를 해소해 접속 신뢰성을 향상시킨다.
회로 기판(14)에의 실장면(2)에는, 서로 대향하는 1쌍의 측가장자리의 일방측(2a)에 근접해 출력 범프(3)가 배열된 출력 범프 영역(4)이 형성되고, 1쌍의 측가장자리의 타방측(2b)에 근접해 입력 범프(5)가 배열된 입력 범프 영역(6)이 형성되고, 출력 범프 영역(4) 및 상기 입력 범프 영역(6)은, 상이한 면적이고, 또한 실장면(2)에 있어서 비대칭으로 배치되고, 출력 범프 영역(4) 또는 입력 범프 영역(6) 중, 상대적으로 대면적인 일방은, 1쌍의 측가장자리 간의 폭(W)의 4％ 이상의 거리만큼, 근접하는 일방 또는 타방의 측가장자리(2a, 2b)로부터 내측에 형성되어 있다. In addition to having a difference in area between the input bump area and the output bump area, connection reliability is improved by eliminating the pressure difference caused by the thermocompression bonding head even for electronic components that are asymmetrically arranged.
On the mounting surface 2 on the circuit board 14, an output bump region 4 in which output bumps 3 are arranged adjacent to one side 2a of a pair of opposite side edges is formed. An input bump region 6 in which input bumps 5 are arranged is formed close to the other side 2b of the side edge, and the output bump region 4 and the input bump region 6 are different areas, and are actually Arranged asymmetrically in the scene 2, one of the output bump regions 4 and the input bump region 6, which has a relatively large area, has a distance of 4% or more of the width W between the pair of side edges, It is formed inside from one or the other side edge 2a, 2b adjoining.

Description

전자 부품, 접속체, 접속체의 제조 방법 및 전자 부품의 접속 방법{ELECTRONIC COMPONENT, CONNECTOR, CONNECTOR PRODUCTION METHOD, AND ELECTRONIC COMPONENT CONNECTING METHOD}Electronic parts, connecting bodies, manufacturing methods of connecting bodies, and connecting methods of electronic parts

본 발명은, 접착제를 개재하여 회로 기판 상에 접속되는 전자 부품, 회로 기판 상에 전자 부품이 접속된 접속체, 접속체의 제조 방법 및 전자 부품의 접속 방법에 관계되고, 특히 회로 기판에의 실장면에 복수의 범프 전극이 비대칭으로 배치되어 있는 전자 부품과, 이 전자 부품이 접속된 접속체, 접속체의 제조 방법 및 전자 부품의 접속 방법에 관한 것이다.The present invention relates to an electronic component connected on a circuit board via an adhesive, a connector in which an electronic component is connected on a circuit board, a method for manufacturing the connector, and a method for connecting the electronic component, particularly to a circuit board. It relates to an electronic component in which a plurality of bump electrodes are asymmetrically arranged on a surface, a connecting body to which the electronic component is connected, a manufacturing method of the connecting body, and a connecting method of the electronic component.

본 출원은, 일본에 있어서 2013년 12월 20일에 출원된 일본 특허출원 번호 일본 특허출원 2013-264377 및 일본에 있어서 2014년 8월 8일에 출원된 일본 특허출원 번호 일본 특허출원 2014-162480을 기초로 해서 우선권을 주장하는 것이고, 이들 출원은 참조됨으로써 본 출원에 원용된다. This application is based on Japanese Patent Application No. 2013-264377 filed on December 20, 2013 in Japan and Japanese Patent Application No. 2014-162480 filed on August 8, 2014 in Japan. Priority is claimed on the basis of, and these applications are incorporated into this application by reference.

종래, 각종 전자기기의 회로 기판에 IC칩이나 LSI칩 등의 전자 부품이 접속된 접속체가 제공되고 있다. 최근, 각종 전자기기에 있어서는, 파인 피치화, 경량 박형화 등의 관점에서, 전자 부품으로서 실장면에 돌기상의 전극인 범프가 배열된 IC칩이나 LSI칩을 사용하고, 이들 IC칩 등의 전자 부품을 직접 회로 기판 상에 실장하는 이른바 COB(chip on board)나, COG(chip on glass)가 채용되고 있다.BACKGROUND OF THE INVENTION [0002] Conventionally, connection bodies in which electronic components such as IC chips and LSI chips are connected to circuit boards of various electronic devices have been provided. In recent years, in various electronic devices, from the viewpoint of fine pitch reduction, light weight and thinning, etc., IC chips and LSI chips having bumps, which are protruding electrodes, are used as electronic components on the mounting surface, and electronic components such as these IC chips are used. A so-called COB (chip on board) or COG (chip on glass) that is directly mounted on a circuit board is employed.

COB 접속이나 COG 접속에 있어서는, 회로 기판의 단자부 상에 이방성 도전 필름을 개재하여 IC칩이 열압착되고 있다. 이방성 도전 필름은, 열경화형 바인더 수지에 도전성 입자를 혼합해 필름상으로 한 것으로, 2개의 도체 사이에서 가열 압착됨으로써 도전 입자에 의해 도체 간의 전기적 도통이 취해지고, 바인더 수지에 의해 도체 간의 기계적 접속이 유지된다. 이방성 도전 필름을 구성하는 접착제로서는, 통상 신뢰성이 높은 열경화성 접착제를 사용하도록 되어 있다. 또 한편으로, 광경화성 수지에 의한 접속이나, 열경화와 광경화를 병용한 접속 방법도 이용되고 있지만, 툴에 의해 가압하는 경우에 있어서, 열경화성 접착제와 동일한 문제를 내포한다고 상정된다.In a COB connection or a COG connection, an IC chip is thermally compressed on a terminal portion of a circuit board with an anisotropic conductive film interposed therebetween. The anisotropic conductive film is obtained by mixing conductive particles with a thermosetting binder resin to form a film. By heating and pressing between two conductors, electrical conduction between the conductors is achieved by the conductive particles, and mechanical connection between the conductors is achieved by the binder resin. maintain. As the adhesive constituting the anisotropic conductive film, a highly reliable thermosetting adhesive is usually used. On the other hand, although a connection method using a photocurable resin or a combination of heat curing and photocuring is also used, it is assumed that the same problem as the thermosetting adhesive is involved in the case of pressing with a tool.

범프가 형성된 IC칩(50)은, 예를 들어 도 6(A)에 나타내는 바와 같이, 회로 기판의 실장면에, 일방의 측가장자리(50a)를 따라 입력 범프(51)가 일렬로 배열된 입력 범프 영역(52)이 형성되고, 일방의 측가장자리(50a)와 대향하는 타방의 측가장자리(50b)를 따라 출력 범프(53)가 2열의 지그재그상으로 배열된 출력 범프 영역(54)이 형성되어 있다. 범프 배열은 IC칩의 종류에 따라 다양하지만, 일반적으로 종래의 범프가 형성된 IC칩은, 입력 범프(51)의 수보다 출력 범프(53)의 수가 많아, 입력 범프 영역(52)의 면적보다 출력 범프 영역(54)의 면적이 넓어지고, 또 입력 범프(51)의 형상이 출력 범프(53)의 형상보다 크게 형성되어 있다.As shown in FIG. 6(A), for example, the bumped IC chip 50 has input bumps 51 arranged in a row along one side edge 50a on the mounting surface of the circuit board. A bump region 52 is formed, and an output bump region 54 in which output bumps 53 are arranged in a zigzag pattern in two rows along one side edge 50a and the opposite side edge 50b is formed. have. Although the arrangement of bumps varies depending on the type of IC chip, in general, the number of output bumps 53 is greater than the number of input bumps 51 in conventional bumped IC chips, and the area of the input bump region 52 is larger than the output bump area 52. The area of the bump region 54 is widened, and the shape of the input bump 51 is larger than that of the output bump 53.

그리고, COG 실장에서는, 예를 들어 도 6(B)에 나타내는 바와 같이, 이방성 도전 필름(55)을 개재하여 회로 기판(56)의 전극 단자(57) 상에 IC칩(50)이 탑재된 후, 열압착 헤드(58)에 의해 IC칩(50)의 위로부터 가열 압박한다. 이 열압착 헤드(58)에 의한 열가압에 의해, 이방성 도전 필름(55)의 바인더 수지가 용융되어 각 입출력 범프(51, 53)와 회로 기판(56)의 전극 단자(57) 사이로부터 유동함과 함께, 각 입출력 범프(51, 53)와 회로 기판(56)의 전극 단자(57) 사이에 도전성 입자가 협지되고, 이 상태에서 바인더 수지가 열경화된다. 이것에 의해, IC칩(50)은, 회로 기판(56) 상에 전기적, 기계적으로 접속된다.And in COG mounting, after the IC chip 50 is mounted on the electrode terminal 57 of the circuit board 56 via the anisotropic conductive film 55, for example, as shown in FIG. 6(B), , heat-pressing from above the IC chip 50 by the thermocompression bonding head 58. The binder resin of the anisotropic conductive film 55 is melted and flows between the input/output bumps 51 and 53 and the electrode terminal 57 of the circuit board 56 by the thermal pressurization by the thermocompression head 58. In addition, conductive particles are sandwiched between the input/output bumps 51 and 53 and the electrode terminal 57 of the circuit board 56, and the binder resin is thermally cured in this state. In this way, the IC chip 50 is electrically and mechanically connected on the circuit board 56 .

일본 특허공개 2004-214373호 공보Japanese Unexamined Patent Publication No. 2004-214373

여기서, 상기 서술한 바와 같이, 범프가 형성된 IC칩(50) 등의 전자 부품은, 실장면에 형성된 입력 범프(51)와 출력 범프(53)의 각 범프 배열 및 크기가 상이하여, 입력 범프 영역(52)과 출력 범프 영역(54)에 면적차를 갖는다. 또, 전자 부품은, 입력 범프 영역(52)과 출력 범프 영역(54)이 실장면에 있어서 비대칭으로 배치되어 있다.Here, as described above, in the electronic component such as the bumped IC chip 50, the arrangement and size of the bumps of the input bumps 51 and the output bumps 53 formed on the mounting surface are different, and the input bump area (52) and the output bump region 54 have an area difference. In the electronic component, the input bump region 52 and the output bump region 54 are asymmetrically arranged on the mounting surface.

그 때문에, 종래의 COB 접속이나 COG 접속에 있어서는, 열압착 헤드(58)에 의한 입력 범프(51)와 출력 범프(53)에 가해지는 압박력이 불균일해지고, 예를 들어 출력 범프 영역(54)에 있어서는, 타방의 측가장자리(50b)측에 배열된 출력 범프(53)와, 실장면의 내측에 배열된 출력 범프(53)에서 압력차가 생길 수 있다. Therefore, in the conventional COB connection or COG connection, the pressing force applied to the input bump 51 and the output bump 53 by the thermocompression bonding head 58 becomes uneven, and for example, the output bump area 54 In this case, a pressure difference may occur between the output bump 53 arranged on the side of the other side edge 50b and the output bump 53 arranged on the inside of the mounting surface.

또, 열압착 헤드(58)에 의한 압력이 입력 범프 영역(52)과 출력 범프 영역(54)의 각 내측가장자리에 편중함으로써, 출력 범프 영역(54)에 있어서는, 타방의 측가장자리(50b)측에 배열된 출력 범프(53)에 대한 압력이 약해져, 도전성 입자의 압입이 부족해 도통 불량을 일으킬 우려가 있다.In addition, the pressure by the thermal compression head 58 is biased on the inner edge of the input bump area 52 and the output bump area 54, so that in the output bump area 54, the other side edge 50b side The pressure on the output bumps 53 arranged in the upper part becomes weak, and there is a possibility that the press-fitting of the conductive particles is insufficient, resulting in poor conduction.

이와 같은 문제를 해결하기 위해서, 신호 등의 입출력에는 사용하지 않는 이른바 더미 범프를 형성해, 열압착 헤드로부터 IC칩 전체면에 가해지는 응력을 분산시켜 균일화시키는 것이 이루어지고 있다. 그러나, 이 수법에서도 응력의 지점(支點)이 증가함으로써, 기술적 난이도는 높아진다. 또, 더미 범프를 형성하기 위해서는, 전자 부품의 제조 공정수가 증가하고, 또 쓸데없이 재료 비용도 필요해져 버리기 때문에, 더미 범프를 사용하지 않는 구성이 요망된다.In order to solve such a problem, so-called dummy bumps that are not used for signal input and output are formed to disperse and equalize the stress applied from the thermal compression head to the entire surface of the IC chip. However, even in this technique, the technical difficulty increases as the point of stress increases. In addition, since the number of manufacturing steps for electronic components increases and material costs are unnecessarily required to form dummy bumps, a configuration in which dummy bumps are not used is desired.

그래서, 본 발명은, 입력 범프 영역과 출력 범프 영역이 면적차를 가짐과 함께 비대칭으로 배치되어 있는 전자 부품에 있어서, 열압착 헤드에 의한 압력차를 해소해 접속 신뢰성을 향상시킬 수 있는 전자 부품, 접속체, 접속체의 제조 방법 및 접속 방법을 제공하는 것을 목적으로 한다.Therefore, the present invention is an electronic component in which an input bump region and an output bump region have a difference in area and are asymmetrically disposed, and can improve connection reliability by eliminating the pressure difference caused by a thermocompression bonding head, It is an object of the present invention to provide a connected body, a manufacturing method of the connected body, and a connecting method.

상기 서술한 과제를 해결하기 위해서 본 발명에 관련된 전자 부품은, 서로 대향하는 1쌍의 측가장자리의 일방측에 근접해 출력 범프가 배열된 출력 범프 영역이 형성되고, 상기 1쌍의 측가장자리의 타방측에 근접해 입력 범프가 배열된 입력 범프 영역이 형성되고, 상기 출력 범프 영역 및 상기 입력 범프 영역은, 상이한 면적이고, 또한 비대칭으로 배치되고, 상기 출력 범프 영역 또는 상기 입력 범프 영역 중 상대적으로 대면적인 일방은, 상기 1쌍의 측가장자리 간의 폭의 4％ 이상의 거리만큼, 근접하는 상기 일방 또는 타방의 측가장자리로부터 내측에 형성되어 있는 것이다. In order to solve the problems described above, in the electronic component of the present invention, an output bump region in which output bumps are arranged is formed close to one side of a pair of side edges facing each other, and the other side of the pair of side edges is formed. An input bump area in which input bumps are arranged close to is formed, the output bump area and the input bump area are different areas and are asymmetrically arranged, and either the output bump area or the input bump area has a relatively large area. is formed on the inner side from one or the other side edge adjoining by a distance of 4% or more of the width between the pair of side edges.

또, 본 발명에 관련된 접속체는, 전자 부품이 접착제를 개재하여 회로 기판 상에 배치되고, 가압 툴로 가압됨으로써, 상기 전자 부품이 상기 회로 기판 상에 접속된 접속체에 있어서, 상기 전자 부품의 상기 회로 기판에의 실장면에는, 서로 대향하는 1쌍의 측가장자리의 일방측에 근접해 출력 범프가 배열된 출력 범프 영역이 형성되고, 상기 1쌍의 측가장자리의 타방측에 근접해 입력 범프가 배열된 입력 범프 영역이 형성되고, 상기 출력 범프 영역 및 상기 입력 범프 영역은, 상이한 면적이고, 또한 상기 실장면에 있어서 비대칭으로 배치되고, 상기 출력 범프 영역 또는 상기 입력 범프 영역 중, 상대적으로 대면적인 일방은, 상기 1쌍의 측가장자리 간의 폭의 4％ 이상의 거리만큼, 근접하는 상기 일방 또는 타방의 측가장자리로부터 내측에 형성되어 있는 것이다.Further, in the connection body according to the present invention, the electronic component is disposed on a circuit board via an adhesive and is pressed with a pressing tool so that the electronic component is connected on the circuit board. On the mounting surface on the circuit board, an output bump region in which output bumps are arranged close to one side of a pair of side edges facing each other is formed, and an input bump area where input bumps are arranged close to the other side of the pair of side edges facing each other. A bump area is formed, and the output bump area and the input bump area are different areas and are asymmetrically arranged on the mounting surface, and either the output bump area or the input bump area has a relatively large area, A distance of 4% or more of the width between the pair of side edges is formed on the inner side from one or the other side edge adjoining.

또, 본 발명에 관련된 접속체의 제조 방법은, 접착제를 개재하여 회로 기판 상에 전자 부품을 배치하고, 가압 툴로 가압함으로써 상기 전자 부품을 상기 회로 기판 상에 접속하는 접속체의 제조 방법에 있어서, 상기 전자 부품의 상기 회로 기판에의 실장면에는, 서로 대향하는 1쌍의 측가장자리의 일방측에 근접해 출력 범프가 배열된 출력 범프 영역이 형성되고, 상기 1쌍의 측가장자리의 타방측에 근접해 입력 범프가 배열된 입력 범프 영역이 형성되고, 상기 출력 범프 영역 및 상기 입력 범프 영역은, 상이한 면적이고, 또한 상기 실장면에 있어서 비대칭으로 배치되고, 상기 출력 범프 영역 또는 상기 입력 범프 영역 중, 상대적으로 대면적인 일방은, 상기 1쌍의 측가장자리 간의 폭의 4％ 이상의 거리만큼, 근접하는 상기 일방 또는 타방의 측가장자리로부터 내측에 형성되어 있는 것이다.In addition, in the manufacturing method of a connected body according to the present invention, in the manufacturing method of a connected body in which an electronic component is placed on a circuit board with an adhesive interposed therebetween, and the electronic component is connected to the circuit board by pressing with a pressure tool, On the mounting surface of the electronic component on the circuit board, an output bump region in which output bumps are arranged in proximity to one side of a pair of side edges facing each other is formed, and is adjacent to the other side of the pair of side edges to input input. An input bump area in which bumps are arranged is formed, the output bump area and the input bump area are different areas and are asymmetrically arranged on the mounting surface, and either the output bump area or the input bump area is relatively One side of the face is formed inward from the one or the other side edge adjoining by a distance of 4% or more of the width between the pair of side edges.

또, 본 발명에 관련된 접속 방법은, 접착제를 개재하여 회로 기판 상에 전자 부품을 배치하고, 가압 툴로 가압함으로써 상기 전자 부품을 상기 회로 기판 상에 접속하는 전자 부품의 접속 방법에 있어서, 상기 전자 부품의 상기 회로 기판에의 실장면에는, 서로 대향하는 1쌍의 측가장자리의 일방측에 근접해 출력 범프가 배열된 출력 범프 영역이 형성되고, 상기 1쌍의 측가장자리의 타방측에 근접해 입력 범프가 배열된 입력 범프 영역이 형성되고, 상기 출력 범프 영역 및 상기 입력 범프 영역은, 상이한 면적이고, 또한 상기 실장면에 있어서 비대칭으로 배치되고, 상기 출력 범프 영역 또는 상기 입력 범프 영역 중, 상대적으로 대면적인 일방은, 상기 1쌍의 측가장자리 간의 폭의 4％ 이상의 거리만큼, 근접하는 상기 일방 또는 타방의 측가장자리로부터 내측에 형성되어 있는 것이다.Further, a connection method according to the present invention is an electronic component connection method comprising arranging an electronic component on a circuit board with an adhesive and then pressurizing the electronic component on the circuit board by pressing with a pressure tool. An output bump region in which output bumps are arranged close to one side of a pair of side edges facing each other is formed on the mounting surface on the circuit board, and input bumps are arranged close to the other side of the pair of side edges. an input bump area is formed, wherein the output bump area and the input bump area are different areas and are asymmetrically disposed on the mounting surface, and either the output bump area or the input bump area has a relatively large area. is formed on the inner side from one or the other side edge adjoining by a distance of 4% or more of the width between the pair of side edges.

상기 서술한 과제를 해결하기 위해서, 본 발명에 관련된 전자 부품은, 제 1 측가장자리를 따라 범프열이 형성된 사각형상의 제 1 범프 영역과, 상기 제 1 측가장자리에 대향하는 제 2 측가장자리를 따라 범프열이 형성된 사각형상의 제 2 범프 영역을 구비하고, 상기 제 1 범프 영역의 폭 방향의 거리가, 상기 제 2 범프 영역의 폭 방향의 거리보다 크고, 상기 제 1 범프 영역의 폭 방향의 외측과 상기 제 2 범프 영역의 폭 방향의 외측 사이의 범프 영역 외측 간 중점이, 상기 제 1 측가장자리와 상기 제 2 측가장자리 사이의 측가장자리 간 중점보다, 상기 제 2 측가장자리측에 존재하는 것이다.In order to solve the problems described above, an electronic component according to the present invention includes a rectangular first bump region in which a row of bumps are formed along a first side edge, and a bump along a second side edge opposite to the first side edge. A quadrangular second bump region with rows formed thereon, a distance between the first bump regions in the width direction is greater than a distance between the second bump regions in the width direction, and an outer side of the first bump region in the width direction and the second bump region in the width direction. The midpoint between the outer sides of the bump area between the outer sides of the second bump area in the width direction is closer to the second side edge than the midpoint between the side edges between the first side edge and the second side edge.

또, 본 발명에 관련된 접속체는, 제 1 측가장자리를 따라 범프열이 형성된 사각형상의 제 1 범프 영역과, 상기 제 1 측가장자리에 대향하는 제 2 측가장자리를 따라 범프열이 형성된 사각형상의 제 2 범프 영역을 구비하고, 상기 제 1 범프 영역의 폭 방향의 거리가, 상기 제 2 범프 영역의 폭 방향의 거리보다 크고, 상기 제 1 범프 영역의 폭 방향의 외측과 상기 제 2 범프 영역의 폭 방향의 외측 사이의 범프 영역 외측 간 중점이, 상기 제 1 측가장자리와 상기 제 2 측가장자리 사이의 측가장자리 간 중점보다, 상기 제 2 측가장자리측에 존재하는 전자 부품과, 상기 회로 부품이 접착제를 개재하여 접속된 회로 기판을 구비하는 것이다.Further, the connection body according to the present invention comprises a quadrangular first bump region in which bump rows are formed along the first side edge, and a quadrangular second bump region in which bump rows are formed along the second side edge opposite to the first side edge. A bump region is provided, wherein a distance of the first bump region in the width direction is greater than a distance of the second bump region in the width direction, and the outside of the first bump region in the width direction and the width direction of the second bump region are The midpoint between the outer sides of the bump area between the outer sides of is higher than the midpoint between the side edges between the first side edge and the second side edge, and the electronic component existing on the side of the second side edge and the circuit component interpose an adhesive. to provide a circuit board connected thereto.

또, 본 발명에 관련된 접속체의 제조 방법은, 제 1 측가장자리를 따라 범프열이 형성된 사각형상의 제 1 범프 영역과, 상기 제 1 측가장자리에 대향하는 제 2 측가장자리를 따라 범프열이 형성된 사각형상의 제 2 범프 영역을 구비하고, 상기 제 1 범프 영역의 폭 방향의 거리가, 상기 제 2 범프 영역의 폭 방향의 거리보다 크고, 상기 제 1 범프 영역의 폭 방향의 외측과 상기 제 2 범프 영역의 폭 방향의 외측 사이의 범프 영역 외측 간 중점이, 상기 제 1 측가장자리와 상기 제 2 측가장자리 사이의 측가장자리 간 중점보다, 상기 제 2 측가장자리측에 존재하는 전자 부품을, 접착제를 개재하여 회로 기판 상에 배치하고, 가압 툴로 가압함으로써 상기 전자 부품을 상기 회로 기판 상에 접속하는 것이다.Further, the method for manufacturing a connected body according to the present invention includes a rectangular first bump region in which rows of bumps are formed along a first side edge, and rows of bumps are formed along a second side edge opposite to the first side edge. a second bump area on the upper side, wherein a distance of the first bump area in the width direction is greater than a distance of the second bump area in the width direction, and a distance between the outer side of the first bump area in the width direction and the second bump area The midpoint between the outer sides of the bump region between the outer sides in the width direction of is higher than the midpoint between the side edges between the first side edge and the second side edge, and the electronic component existing on the side of the second side edge, through an adhesive The electronic component is connected on the circuit board by placing it on the circuit board and pressing it with a pressing tool.

또, 본 발명에 관련된 접속 방법은, 제 1 측가장자리를 따라 범프열이 형성된 사각형상의 제 1 범프 영역과, 상기 제 1 측가장자리에 대향하는 제 2 측가장자리를 따라 범프열이 형성된 사각형상의 제 2 범프 영역을 구비하고, 상기 제 1 범프 영역의 폭 방향의 거리가, 상기 제 2 범프 영역의 폭 방향의 거리보다 크고, 상기 제 1 범프 영역의 폭 방향의 외측과 상기 제 2 범프 영역의 폭 방향의 외측 사이의 범프 영역 외측 간 중점이, 상기 제 1 측가장자리와 상기 제 2 측가장자리 사이의 측가장자리 간 중점보다, 상기 제 2 측가장자리측에 존재하는 전자 부품을, 접착제를 개재하여 회로 기판 상에 배치하고, 가압 툴로 가압함으로써 상기 전자 부품을 상기 회로 기판 상에 접속하는 것이다.Further, the connection method according to the present invention comprises a rectangular first bump region in which rows of bumps are formed along the first side edge, and a second bump region in the shape of a rectangle in which rows of bumps are formed along the second side edge opposite to the first side edge. A bump region is provided, wherein a distance of the first bump region in the width direction is greater than a distance of the second bump region in the width direction, and the outside of the first bump region in the width direction and the width direction of the second bump region are The midpoint between the outer sides of the bump region between the outer sides of the above is higher than the midpoint between the side edges between the first side edge and the second side edge, and the electronic component existing on the side of the second side edge is placed on the circuit board via an adhesive. , and pressurizing with a pressing tool to connect the electronic component on the circuit board.

본 발명에 의하면, 대면적의 범프 영역을 실장면의 폭에 대해 소정 비율만큼, 측가장자리로부터 내측에 형성함으로써, 당해 범프 영역의 폭 방향에 걸쳐 형성되어 있는 압력 구배가 완만하게 평균화되어, 당해 측가장자리측에 있어서 열압착 헤드에 의한 압박력이 부족한 사태를 방지한다. 이것에 의해, 전자 부품은, 당해 측가장자리측의 범프에 있어서도 회로 기판에 형성된 전극 단자와의 사이에서 확실하게 도전성 입자를 협지하여, 도통성을 확보할 수 있다.According to the present invention, by forming a large-area bump region from the side edge to the inside at a predetermined ratio with respect to the width of the mounting surface, the pressure gradient formed over the width direction of the bump region is gently averaged, and the side A situation where the pressing force by the thermocompression bonding head is insufficient on the edge side is prevented. In this way, the electronic component can reliably hold the conductive particles between the electrode terminals formed on the circuit board even at the bumps on the side edges to ensure conductivity.

본 발명에 의하면, 제 1 범프 영역의 폭 방향의 외측과 제 2 범프 영역의 폭 방향의 외측 사이의 범프 영역 외측 간 중점이, 제 1 측가장자리와 상기 제 2 측가장자리 사이의 측가장자리 간 중점보다, 제 2 측가장자리측에 존재하기 때문에, 범프 영역의 폭 방향에 걸쳐 형성되어 있는 압력 구배가 완만하게 평균화되어, 측가장자리측에 있어서 열압착 헤드에 의한 압박력이 부족한 사태를 방지할 수 있다. 이것에 의해, 측가장자리측의 범프에 있어서도 확실하게 도전성 입자를 협지할 수 있고, 우수한 도통성을 얻을 수 있다.According to the present invention, the midpoint between the outer sides of the bump area between the outer side in the width direction of the first bump area and the outer side in the width direction of the second bump area is greater than the midpoint between the side edges between the first side edge and the second side edge. , exists on the second side edge side, so that the pressure gradient formed over the width direction of the bump area is gently averaged, and a situation where the pressing force by the thermocompression bonding head is insufficient on the side edge side can be prevented. Thereby, also in the bump by the side edge side, electroconductive particle can be clamped reliably, and excellent conduction property can be obtained.

도 1은, 본 발명에 관련된 전자 부품의 실장면을 나타내는 평면도이다.
도 2는, 전자 부품이 접속된 접속체를 나타내는 단면도이다.
도 3은, 더미 범프를 형성한 본 발명에 관련된 전자 부품의 실장면을 나타내는 평면도이다.
도 4는, 이방성 도전 필름을 나타내는 단면도이다.
도 5는, 본 발명에 관련된 전자 부품의 폭 방향의 실장면을 나타내는 단면도이다.
도 6의 (A)는 종래의 전자 부품의 실장면을 나타내는 평면도이고, (B)는 실장 상태를 나타내는 단면도이다.1 is a plan view showing a mounting surface of an electronic component related to the present invention.
Fig. 2 is a cross-sectional view showing a connecting body to which electronic components are connected.
Fig. 3 is a plan view showing a mounting surface of an electronic component according to the present invention in which dummy bumps are formed.
4 is a cross-sectional view showing an anisotropic conductive film.
Fig. 5 is a cross-sectional view showing a mounting surface in the width direction of the electronic component according to the present invention.
Fig. 6 (A) is a plan view showing a mounted surface of a conventional electronic component, and (B) is a cross-sectional view showing a mounted state.

이하, 본 발명이 적용된 전자 부품, 접속체, 접속체의 제조 방법 및 접속 방법에 대해, 도면을 참조하면서 상세하게 설명한다. 또한, 본 발명은, 이하의 실시형태에만 한정되는 것은 아니고, 본 발명의 요지를 일탈하지 않는 범위 내에 있어서 여러 가지 변경이 가능한 것은 물론이다. 또, 도면은 모식적인 것이고, 각 치수의 비율 등은 현실의 것과는 상이한 경우가 있다. 구체적인 치수 등은 이하의 설명을 참작해 판단해야 하는 것이다. 또, 도면 상호 간에 있어서도 서로의 치수 관계나 비율이 상이한 부분이 포함되어 있는 것은 물론이다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, electronic components, connecting bodies, and manufacturing methods and connecting methods of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited only to the following embodiment, Of course, various changes are possible within the range which does not deviate from the summary of this invention. In addition, the drawing is typical, and the ratio of each dimension may differ from an actual thing. Specific dimensions and the like should be judged in consideration of the following description. In addition, it goes without saying that even between the drawings, there are portions in which the dimensional relationships and ratios of each other are different.

[제 1 실시형태][First Embodiment]

먼저, 본 발명의 제 1 실시형태에 대해 설명한다. 본 발명이 적용된 전자 부품은, 접착제를 개재하여 회로 기판 상에 배치되고, 열압착 헤드로 가압됨으로써 회로 기판 상에 접속되는 전자 부품이고, 예를 들어 드라이버 IC나 시스템 LSI 등의 패키지화된 전자 부품이다. 이하에서는, 전자 부품으로서 IC칩(1)을 예로 설명한다.First, the first embodiment of the present invention will be described. The electronic component to which the present invention is applied is an electronic component that is placed on a circuit board via an adhesive and is connected to the circuit board by being pressed with a thermocompression bonding head, and is, for example, a packaged electronic component such as a driver IC or system LSI. . Below, the IC chip 1 is demonstrated as an example as an electronic component.

도 1에 나타내는 바와 같이, IC칩(1)의 회로 기판 상에 접속되는 실장면(2)은, 대략 사각형상을 이루고, 길이 방향이 되는 서로 대향하는 1쌍의 측가장자리(2a, 2b)를 따라, 출력 범프(3)가 배열된 출력 범프 영역(4) 및 입력 범프(5)가 배열된 입력 범프 영역(6)이 형성되어 있다. IC칩(1)은, 출력 범프 영역(4)이 실장면(2)의 일방의 측가장자리(2a)측에 형성되고, 입력 범프 영역(6)이 실장면(2)의 타방의 측가장자리(2b)측에 형성되어 있다. 이것에 의해, IC칩(1)은, 실장면(2)의 폭 방향에 걸쳐 출력 범프 영역(4)과 입력 범프 영역(6)이 이간되어 형성되어 있다.As shown in Fig. 1, the mounting surface 2 connected on the circuit board of the IC chip 1 has a substantially rectangular shape and has a pair of opposite side edges 2a and 2b in the longitudinal direction. Accordingly, an output bump region 4 in which the output bumps 3 are arranged and an input bump region 6 in which the input bumps 5 are arranged are formed. In the IC chip 1, the output bump region 4 is formed on one side edge 2a side of the mounting surface 2, and the input bump region 6 is formed on the other side edge of the mounting surface 2 ( It is formed on the side of 2b). As a result, the IC chip 1 is formed with the output bump region 4 and the input bump region 6 spaced apart across the width direction of the mounting surface 2 .

출력 범프 영역(4)에는, 예를 들어 동일 형상으로 형성된 복수의 출력 범프(3)가, 실장면(2)의 길이 방향을 따라 3열로 지그재그상으로 배열되어 있다. 또, 입력 범프 영역(6)에는, 예를 들어 동일 형상으로 형성된 복수의 입력 범프(5)가, 실장면(2)의 길이 방향을 따라 1열로 배열되어 있다. 또한, 입력 범프(5)는, 출력 범프(3)보다 크게 형성된다. 이것에 의해, IC칩(1)은, 출력 범프 영역(4)과 입력 범프 영역(6)이 면적차를 가짐과 함께, 실장면(2)에 있어서 비대칭으로 배치되어 있다. 또한, 출력 범프 영역(4)에 배열되어 있는 각 출력 범프(3)는, 각각 동일한 치수로 형성되는 것이 바람직하다. 마찬가지로, 입력 범프 영역(6)에 배열되어 있는 각 입력 범프(5)는, 각각 동일한 치수로 형성되는 것이 바람직하다.In the output bump region 4 , for example, a plurality of output bumps 3 formed in the same shape are arranged in a zigzag pattern in three rows along the longitudinal direction of the mounting surface 2 . Further, in the input bump region 6 , for example, a plurality of input bumps 5 formed in the same shape are arranged in a row along the longitudinal direction of the mounting surface 2 . Also, the input bump 5 is formed to be larger than the output bump 3 . As a result, in the IC chip 1, the output bump region 4 and the input bump region 6 have a difference in area and are arranged asymmetrically on the mounting surface 2. In addition, it is preferable that each of the output bumps 3 arranged in the output bump region 4 is formed to have the same dimensions. Similarly, each of the input bumps 5 arranged in the input bump region 6 is preferably formed to have the same dimensions.

[대면적 범프 영역의 오프셋] [Offset of large-area bump area]

본 발명에 관련된 IC칩(1)에서는, 출력 범프 영역(4)이, 일방의 측가장자리(2a)와 타방의 측가장자리(2b) 사이에 걸치는 IC 폭(W)에 대해 소정 비율만큼, 일방의 측가장자리(2a)로부터 내측에 형성되어 있다. 이것에 의해, IC칩(1)은, 후술하는 열압착 헤드(17)에 의해 회로 기판(14) 상에 가열 압박된 경우에, 압박력이 출력 범프 영역(4)의 내측에 편재하는 것을 방지해, 일방의 측가장자리(2a)측에 배열되어 있는 출력 펌프(3)에 대해서도 적정한 압박력을 가할 수 있다.In the IC chip 1 according to the present invention, the output bump region 4 is formed at a predetermined ratio to the IC width W extending between one side edge 2a and the other side edge 2b. It is formed inside from the side edge 2a. This prevents the pressing force from being unevenly distributed inside the output bump region 4 when the IC chip 1 is heated and pressed onto the circuit board 14 by the thermocompression bonding head 17 described later. , an appropriate pressing force can be applied also to the output pump 3 arranged on one side edge 2a side.

즉, IC칩(1)은, 출력 범프 영역(4)과 입력 범프 영역(6)에 면적차를 가짐과 함께 실장면(2)에 있어서 비대칭으로 배치되어 있기 때문에, 열압착 헤드(17)에 의해 실장면(2)의 전체면에 대해 압력이 가해지면, 출력 범프(3)가 복수열로 배열됨으로써 폭 방향에 걸쳐 대면적으로 형성되어 있는 출력 범프 영역(4)에 있어서는, 입력 범프 영역(6)과 대치하는 내측가장자리에 있어서의 압박력이 강해져 실장면(2)의 일방의 측가장자리(2a)측에 걸쳐 압박력이 약해지는 압력 구배가 되고, 일방의 측가장자리(2a)측에 배열되어 있는 출력 범프(3)에 대한 압박력이 부족하다. 이것에 의해, 도전성 입자의 압입이 부족한 것에 의해, 특히 범프의 외측가장자리 영역에 있어서 출력 범프(3)의 도통 저항이 높아질 우려가 있었다.That is, since the IC chip 1 has an area difference between the output bump region 4 and the input bump region 6 and is asymmetrically arranged on the mounting surface 2, the thermal compression head 17 When pressure is applied to the entire surface of the mounting surface 2 by the input bump area ( 6), the pressing force at the opposite inner edge becomes stronger, and a pressure gradient in which the pressing force is weakened across the side edge 2a side of one side of the mounting surface 2 is formed, and arranged on one side edge 2a side. The pressing force against the output bump 3 is insufficient. As a result, there is a possibility that the conduction resistance of the output bump 3 increases particularly in the outer edge region of the bump due to lack of press-fitting of the conductive particles.

그래서, IC칩(1)은, 출력 범프 영역(4)을 실장면(2)의 폭에 대해 소정 비율만큼, 일방의 측가장자리(2a)로부터 내측에 형성함으로써, 출력 범프 영역(4)의 폭 방향에 걸쳐 형성되어 있는 압력 구배가 완만하게 평균화되고, 당해 일방의 측가장자리(2a)측에 있어서 열압착 헤드(17)에 의한 압박력이 부족한 사태를 방지한다. 이것에 의해, IC칩(1)은, 당해 일방의 측가장자리(2a)측의 출력 범프(3)에 있어서도 회로 기판(14)에 형성된 전극 단자(15)와의 사이에서 확실하게 도전성 입자를 협지해, 도통성을 확보할 수 있다.Therefore, the IC chip 1 forms the output bump region 4 inside from one side edge 2a by a predetermined ratio with respect to the width of the mounting surface 2, so that the width of the output bump region 4 The pressure gradient formed over the direction is gently averaged, and a situation where the pressing force by the thermal compression bonding head 17 is insufficient on the side of the one side edge 2a is prevented. As a result, the IC chip 1 reliably holds the conductive particles between the electrode terminals 15 formed on the circuit board 14 also in the output bump 3 on the one side edge 2a side. , conductivity can be secured.

이 일방의 측가장자리(2a)로부터 출력 범프 영역(4)까지의 거리(A)는, 실장면(2)의 서로 대향하는 측가장자리 2a 2b 사이에 걸치는 IC 폭(W)에 대해 4％ 이상의 거리로 하는 것이 바람직하다. 출력 범프 영역(4)을, IC 폭(W)에 대해 4％ 이상의 거리만큼, 일방의 측가장자리(2a)로부터 내측에 형성함으로써, 면적차를 갖는 출력 범프 영역(4)과 입력 범프 영역(6)이 비대칭으로 배치되어 있는 실장면(2)에 대해 열압착 헤드(17)가 균등하게 압력을 가한 경우에도, 제 1 측가장자리(2a)측에 배치된 출력 범프(3)까지 충분히 압박력이 전해진다. 그러나, 일방의 측가장자리(2a)로부터 출력 범프(3)까지의 거리(A)가 IC 폭(W)에 대해 4％ 미만이면, 열압착 헤드(17)에 의한 압박력이 일방의 측가장자리(2a)측의 출력 범프(3)까지 충분히 전해지지 않아 도전성 입자의 압입 부족에 의한 도통 불량이 일어날 위험이 있다.The distance A from this one side edge 2a to the output bump region 4 is a distance of 4% or more of the IC width W extending between the opposite side edges 2a and 2b of the mounting surface 2 It is preferable to The output bump region 4 having an area difference between the output bump region 4 and the input bump region 6 is formed by forming the output bump region 4 inside from one side edge 2a by a distance of 4% or more with respect to the IC width W. ) is evenly applied to the mounting surface 2 in which ) is asymmetrically arranged, the pressing force is sufficiently transmitted even to the output bump 3 disposed on the side of the first side edge 2a. . However, if the distance A from one side edge 2a to the output bump 3 is less than 4% with respect to the IC width W, the pressing force by the thermocompression bonding head 17 will be less than one side edge 2a. )-side output bump 3, there is a risk that conduction failure due to insufficient press-fitting of the conductive particles may occur.

또, 거리(A)가 지나치게 커지면 IC칩(1) 전체면에 대한 압력의 균일화에 차질이 생겨, 압력의 불균형을 별도로 유발할 우려가 생긴다. 그 때문에, 거리(A)는 30％ 이내가 바람직하고, 보다 바람직하게는 20％ 이내이며, 보다 더 바람직하게는 15％ 이내이다.In addition, if the distance A is excessively large, pressure uniformity over the entire surface of the IC chip 1 may be hindered, causing pressure imbalance separately. Therefore, the distance A is preferably within 30%, more preferably within 20%, still more preferably within 15%.

[거리(A)＞거리(B)][Distance (A) > Distance (B)]

또한, IC칩(1)은, 상대적으로 대면적인 출력 범프 영역(4)의 일방의 측가장자리(2a)로부터의 거리(A)가, 입력 범프 영역(6)의 타방의 측가장자리(2b)로부터의 거리(B)보다 긴 것이 바람직하다. 즉, 비교적 소면적인 입력 범프 영역(6)의 타방의 측가장자리(2b)로부터의 거리(B)가 대면적인 출력 범프 영역(4)의 일방의 측가장자리(2a)로부터의 거리(A)보다 길면, 출력 범프 영역(4)에 있어서의 폭 방향에 걸치는 압력 구배가 크게 되어, 일방의 측가장자리(2a)측의 출력 범프(3)에 있어서의 도전성 입자의 압입 부족의 해소를 저해해 버린다.Further, in the IC chip 1, the distance A from one side edge 2a of the relatively large output bump region 4 is from the other side edge 2b of the input bump region 6. is preferably longer than the distance (B) of That is, if the distance B from the other side edge 2b of the relatively small-area input bump region 6 is longer than the distance A from one side edge 2a of the large-area output bump region 4 , the pressure gradient across the width direction in the output bump region 4 becomes large, and the elimination of insufficient press-fitting of the conductive particles in the output bump 3 on one side edge 2a side is hindered.

또, 입력 범프(5)가 일렬로 배열됨으로써 비교적 소면적인 입력 범프 영역(6)에 있어서는, 출력 범프 영역(4)과의 면적차 및 비대칭 배치에 의해서도 열압착 헤드(17)에 의한 압박력이 편재하는 것에 의한 압입 부족의 위험이 적은 점에서, 실장면(2)의 타방의 측가장자리(2b)로부터의 거리(B)가 짧아도 문제는 없다.In addition, since the input bumps 5 are arranged in a line, in the input bump region 6 having a relatively small area, the pressing force by the thermocompression bonding head 17 is unevenly distributed even by the difference in area from the output bump region 4 and the asymmetrical arrangement. There is no problem even if the distance B from the other side edge 2b of the mounting surface 2 is short because there is little risk of insufficient press-fitting.

[대면적의 입력 범프 영역(6)을 오프셋][Offset large-area input bump area (6)]

또한, IC칩(1)은, 실장면(2)의 입출력 범프의 구성은 적절히 설계할 수 있다. IC칩(1)은, 상기 서술한 바와 같이 출력 범프(3)를 폭 방향으로 복수 배열함으로써 상대적으로 대면적화시킨 출력 범프 영역(4)을 형성했지만, 반대로 입력 범프(5)를 폭 방향으로 복수 배열함으로써 상대적으로 입력 범프 영역(6)을 대면적 화시켜도 된다.Further, the configuration of the input/output bumps on the mounting surface 2 of the IC chip 1 can be designed appropriately. In the IC chip 1, as described above, output bump regions 4 having a relatively large area are formed by arranging a plurality of output bumps 3 in the width direction, but conversely, a plurality of input bumps 5 are arranged in the width direction. By arranging, the area of the input bump region 6 may be relatively large.

입력 범프 영역(6)을 상대적으로 대면적화한 경우에는, IC칩(1)은, 입력 범프 영역(6)을, IC 폭(W)에 대해 소정 비율, 바람직하게는 IC 폭(W)의 4％ 이상의 거리, 타방의 측가장자리(2b)로부터 내측에 형성시킨다. 또 이 경우, 상대적으로 대면적인 입력 범프 영역(6)의 타방의 측가장자리(2b)로부터의 거리(B)가, 출력 범프 영역(4)의 일방의 측가장자리(2a)로부터의 거리(A)보다 긴 것이 바람직하다.When the input bump region 6 has a relatively large area, the IC chip 1 has the input bump region 6 at a predetermined ratio to the IC width W, preferably 4 of the IC width W. It is formed on the inside from the distance of % or more and the other side edge 2b. In this case, the distance B from the other side edge 2b of the relatively large input bump region 6 is the distance A from the one side edge 2a of the output bump region 4 Longer is preferred.

또한, 입력 범프 영역(6)을 타방의 측가장자리(2b)로부터 IC 폭(W)의 4％ 이상 내측에 형성한 경우, 도 2에 나타내는 바와 같이, 인접하여 회로 기판(14) 상에 플렉시블 기판(16)이 이방성 도전 필름(10)을 개재하여 접속될 때에, 입력 범프(5)와 전극 단자(15)의 접속 위치가 플렉시블 기판(16)을 열가압하는 열압착 헤드(17)로부터 이간된다. 따라서, IC칩(1)의 접속 후에 있어서의 열압착 헤드(17)로부터의 방열에 의한 접속성의 악화를 방지할 수 있다.Further, when the input bump region 6 is formed inside the IC width W by 4% or more from the other side edge 2b, as shown in FIG. 2, the flexible substrate is adjacently placed on the circuit board 14. When (16) is connected via the anisotropic conductive film (10), the connection position of the input bump (5) and the electrode terminal (15) is separated from the thermocompression bonding head (17) that thermally presses the flexible substrate (16). . Accordingly, it is possible to prevent deterioration of connectivity due to heat dissipation from the thermal compression bonding head 17 after the IC chip 1 is connected.

[더미 범프] [dummy bump]

또한, 도 3에 나타내는 바와 같이, IC칩(1)은, 출력 범프 영역(4)과 입력 범프 영역(6) 사이에, 신호 등의 입출력에는 사용하지 않는 이른바 더미 범프(18)가 배열된 더미 범프 영역(19)을 적절히 형성해도 된다.As shown in Fig. 3, in the IC chip 1, between the output bump region 4 and the input bump region 6, so-called dummy bumps 18, which are not used for input/output of signals or the like, are arranged. You may form the bump area|region 19 suitably.

[접착제][glue]

또한, IC칩(1)을 회로 기판(14)에 접속하는 접착제로서는, 이방성 도전 필름(10)(ACF : Anisotropic Conductive Film)을 바람직하게 사용할 수 있다. 이방성 도전 필름(10)은, 도 4에 나타내는 바와 같이 통상 기재가 되는 박리 필름(11) 상에 도전성 입자(12)를 함유하는 바인더 수지층(접착제층)(13)이 형성된 것이다. 이방성 도전 필름(10)은, 도 2에 나타내는 바와 같이, 회로 기판(14)에 형성된 전극 단자(15)와 IC칩(1) 사이에 바인더 수지층(13)을 개재시킴으로써, 회로 기판(14)과 IC칩(1)을 접속해, 도통시키기 위해서 사용된다.Also, as an adhesive for connecting the IC chip 1 to the circuit board 14, an anisotropic conductive film 10 (ACF: Anisotropic Conductive Film) can be preferably used. As shown in Fig. 4, the anisotropic conductive film 10 is one in which a binder resin layer (adhesive layer) 13 containing conductive particles 12 is formed on a release film 11, which is usually a base material. As shown in FIG. 2 , the anisotropic conductive film 10 is formed on the circuit board 14 by interposing a binder resin layer 13 between the electrode terminal 15 formed on the circuit board 14 and the IC chip 1. It is used to connect and conduct the IC chip 1.

바인더 수지층(13)의 접착제 조성물은, 예를 들어 막형성 수지, 열경화성 수지, 잠재성 경화제, 실란 커플링제 등을 함유하는 통상적인 바인더 성분으로 이루어진다.The adhesive composition of the binder resin layer 13 consists of conventional binder components containing, for example, a film forming resin, a thermosetting resin, a latent curing agent, a silane coupling agent and the like.

막형성 수지로서는, 평균 분자량이 10000∼80000 정도인 수지가 바람직하고, 특히 에폭시 수지, 변형 에폭시 수지, 우레탄 수지, 페녹시 수지 등의 각종 수지를 들 수 있다. 그 중에서도, 막형성 상태, 접속 신뢰성 등의 관점에서 페녹시 수지가 바람직하다.As the film-forming resin, a resin having an average molecular weight of about 10000 to 80000 is preferable, and various resins such as epoxy resins, modified epoxy resins, urethane resins, and phenoxy resins are particularly exemplified. Among them, a phenoxy resin is preferable from the viewpoints of film formation state, connection reliability, and the like.

열경화성 수지로서는 특별히 한정되지 않고, 예를 들어 시판되는 에폭시 수지나 아크릴 수지 등을 사용할 수 있다.It does not specifically limit as a thermosetting resin, For example, a commercially available epoxy resin, an acrylic resin, etc. can be used.

에폭시 수지로서는, 특별히 한정되지 않지만, 예를 들어 나프탈렌형 에폭시 수지, 비페닐형 에폭시 수지, 페놀노볼락형 에폭시 수지, 비스페놀형 에폭시 수지, 스틸벤형 에폭시 수지, 트리페놀메탄형 에폭시 수지, 페놀아르알킬형 에폭시 수지, 나프톨형 에폭시 수지, 디시클로펜타디엔형 에폭시 수지, 트리페닐메탄형 에폭시 수지 등을 들 수 있다. 이들은 단독이라도 되고, 2종 이상의 조합이어도 된다.Examples of the epoxy resin include, but are not particularly limited to, naphthalene type epoxy resins, biphenyl type epoxy resins, phenol novolak type epoxy resins, bisphenol type epoxy resins, stilbene type epoxy resins, triphenolmethane type epoxy resins, and phenol aralkyls. type epoxy resins, naphthol type epoxy resins, dicyclopentadiene type epoxy resins, triphenylmethane type epoxy resins, and the like. These may be individual or may be a combination of two or more types.

아크릴 수지로서는, 특별히 제한은 없고, 목적에 따라 아크릴 화합물, 액상 아크릴레이트 등을 적절히 선택할 수 있다. 예를 들어, 메틸아크릴레이트, 에틸아크릴레이트, 이소프로필아크릴레이트, 이소부틸아크릴레이트, 에폭시아크릴레이트, 에틸렌글리콜디아크릴레이트, 디에틸렌글리콜디아크릴레이트, 트리메틸올프로판트리아크릴레이트, 디메틸올트리시클로데칸디아크릴레이트, 테트라메틸렌글리콜테트라아크릴레이트, 2-하이드록시-1,3-디아크릴옥시프로판, 2,2-비스[4-(아크릴옥시메톡시)페닐]프로판, 2,2-비스[4-(아크릴옥시에톡시)페닐]프로판, 디시클로펜테닐아크릴레이트, 트리시클로데카닐아크릴레이트, 트리스(아크릴옥시에틸)이소시아누레이트, 우레탄아크릴레이트, 에폭시아크릴레이트 등을 들 수 있다. 또한, 아크릴레이트를 메타크릴레이트로 한 것을 사용할 수도 있다. 이들은, 1종 단독으로 사용 해도 되고, 2종 이상을 병용해도 된다.The acrylic resin is not particularly limited, and an acrylic compound, liquid acrylate, or the like can be appropriately selected according to the purpose. For example, methyl acrylate, ethyl acrylate, isopropyl acrylate, isobutyl acrylate, epoxy acrylate, ethylene glycol diacrylate, diethylene glycol diacrylate, trimethylolpropane triacrylate, dimethylol tricyclo Decanediacrylate, tetramethylene glycol tetraacrylate, 2-hydroxy-1,3-diacryloxypropane, 2,2-bis[4-(acryloxymethoxy)phenyl]propane, 2,2-bis[ 4-(acryloxyethoxy)phenyl]propane, dicyclopentenyl acrylate, tricyclodecanyl acrylate, tris(acryloxyethyl)isocyanurate, urethane acrylate, epoxy acrylate and the like. Moreover, what made acrylate the methacrylate can also be used. These may be used individually by 1 type, and may use 2 or more types together.

잠재성 경화제로서는, 특별히 한정되지 않지만, 가열 경화형의 경화제를 들 수 있다. 잠재성 경화제는, 통상에서는 반응하지 않고, 열, 광, 가압 등의 용도에 따라 선택되는 각종 트리거에 의해 활성화해, 반응을 개시한다. 열활성형 잠재성 경화제의 활성화 방법에는, 가열에 의한 해리 반응 등으로 활성종(카티온이나 아니온, 라디칼)을 생성하는 방법, 실온 부근에서는 에폭시 수지 중에 안정적으로 분산되어 있고 고온에서 에폭시 수지와 상용·용해해 경화 반응을 개시하는 방법, 몰레큘러시브 봉입 타입의 경화제를 고온에서 용출해 경화 반응을 개시하는 방법, 마이크로 캡슐에 의한 용출·경화 방법 등이 존재한다. 열활성형 잠재성 경화제로서는, 이미다졸계, 하이드라지드계, 삼불화붕소-아민 착체, 술포늄염, 아민이미드, 폴리아민염, 디시안디아미드 등이나, 이들의 변성물이 있고, 이들은 단독이라도 되고, 2종 이상의 혼합체여도 된다. 라디칼 중합 개시제로서는, 공지된 것을 사용할 수 있고, 그 중에서도 유기 과산화물을 바람직하게 사용할 수 있다.Although it does not specifically limit as a latent hardener, A heat hardening type hardener is mentioned. The latent curing agent does not usually react, but is activated by various triggers selected according to the use such as heat, light, and pressure to initiate the reaction. The activation method of the heat-activated latent curing agent is a method of generating active species (cations, anions, radicals) by a dissociation reaction by heating, etc., it is stably dispersed in the epoxy resin at around room temperature and reacts with the epoxy resin at high temperature. There are a method of initiating a commercial/dissolving and curing reaction, a method of initiating a curing reaction by eluting a molecular sieve-encapsulated type curing agent at a high temperature, and a method of eluting and curing using microcapsules. Examples of the heat-activated latent curing agent include imidazole-based, hydrazide-based, boron trifluoride-amine complexes, sulfonium salts, amineimides, polyamine salts, dicyandiamide, and the like, and modified products thereof. It may be, and 2 or more types of mixtures may be sufficient. As the radical polymerization initiator, known ones can be used, and organic peroxides can be preferably used among them.

실란 커플링제로서는, 특별히 한정되지 않지만, 예를 들어 에폭시계, 아미노계, 메르캅토·술파이드계, 우레이도계 등을 들 수 있다. 실란 커플링제를 첨가함으로써, 유기 재료와 무기 재료의 계면에 있어서의 접착성이 향상된다.Although it does not specifically limit as a silane coupling agent, For example, an epoxy type, an amino type, a mercapto sulfide type, a ureido type etc. are mentioned. By adding a silane coupling agent, the adhesiveness at the interface of an organic material and an inorganic material improves.

[도전성 입자][Conductive Particles]

바인더 수지층(13)에 함유되는 도전성 입자(12)로서는, 이방성 도전 필름에 있어서 사용되고 있는 공지된 어느 도전성 입자를 들 수 있다. 즉, 도전성 입자로서는, 예를 들어 니켈, 철, 구리, 알루미늄, 주석, 납, 크롬, 코발트, 은, 금 등의 각종 금속이나 금속 합금의 입자, 금속 산화물, 카본, 그라파이트, 유리, 세라믹, 플라스틱 등의 입자의 표면에 금속을 코트한 것, 혹은 이들 입자의 표면에 추가로 절연 박막을 코트한 것 등을 들 수 있다. 수지 입자의 표면에 금속을 코트한 것인 경우, 수지 입자로서는, 예를 들어 에폭시 수지, 페놀 수지, 아크릴 수지, 아크릴로니트릴·스티렌(AS) 수지, 벤조구아나민 수지, 디비닐벤젠계 수지, 스티렌계 수지 등의 입자를 들 수 있다.As the conductive particles 12 contained in the binder resin layer 13, any known conductive particles used in anisotropic conductive films can be mentioned. That is, examples of the conductive particles include particles of various metals and metal alloys such as nickel, iron, copper, aluminum, tin, lead, chromium, cobalt, silver, and gold, metal oxides, carbon, graphite, glass, ceramics, and plastics. What coated the surface of the particle|grains of the etc. with metal, or what coated the surface of these particle|grains with an insulating thin film further, etc. are mentioned. In the case of resin particles coated with metal, examples of the resin particles include epoxy resins, phenol resins, acrylic resins, acrylonitrile-styrene (AS) resins, benzoguanamine resins, divinylbenzene-based resins, Particles, such as a styrenic resin, are mentioned.

바인더 수지층(13)을 구성하는 접착제 조성물은, 이와 같이 막형성 수지, 열경화성 수지, 잠재성 경화제, 실란 커플링제 등을 함유하는 경우에 한정되지 않고, 통상적인 이방성 도전 필름의 접착제 조성물로서 사용되는 어느 재료로 구성되도록 해도 된다.The adhesive composition constituting the binder resin layer 13 is not limited to the case of containing a film-forming resin, a thermosetting resin, a latent curing agent, a silane coupling agent, etc., and is used as an adhesive composition for a typical anisotropic conductive film. It may be made of any material.

*바인더 수지층(13)을 지지하는 박리 필름(11)은, 예를 들어 PET(Poly Ethylene Terephthalate), OPP(Oriented Polypropylene), PMP(Poly-4-methylpentene-1), PTFE(Polytetrafluoroethylene) 등에 실리콘(silicone) 등의 박리제를 도포해 이루어지고, 이방성 도전 필름(10)의 건조를 방지함과 함께, 이방성 도전 필름(10)의 형상을 유지한다.* The release film 11 supporting the binder resin layer 13 is, for example, PET (Poly Ethylene Terephthalate), OPP (Oriented Polypropylene), PMP (Poly-4-methylpentene-1), PTFE (Polytetrafluoroethylene), etc. It is formed by applying a release agent such as (silicone) to prevent drying of the anisotropic conductive film 10 and to maintain the shape of the anisotropic conductive film 10 .

이방성 도전 필름(10)은, 어느 방법으로 제작하도록 해도 되지만, 예를 들어 이하의 방법에 의해 제작할 수 있다. 막형성 수지, 열경화성 수지, 잠재성 경화제, 실란 커플링제, 도전성 입자 등을 함유하는 접착제 조성물을 조정한다. 조정한 접착제 조성물을 바 코터, 도포 장치 등을 사용하여 박리 필름(11) 상에 도포하고, 오븐 등에 의해 건조시킴으로써, 박리 필름(11)에 바인더 수지층(13)이 지지된 이방성 도전 필름(10)을 얻는다.The anisotropic conductive film 10 may be produced by any method, but can be produced by, for example, the following method. An adhesive composition containing a film forming resin, a thermosetting resin, a latent curing agent, a silane coupling agent, conductive particles and the like is prepared. An anisotropic conductive film 10 in which the binder resin layer 13 is supported on the release film 11 by applying the adjusted adhesive composition onto the release film 11 using a bar coater, applicator or the like and drying it in an oven or the like. ) to get

또 상기 서술한 실시형태에서는, 접착제로서, 바인더 수지층(13)에 적절히 도전성 입자(12)를 함유한 열경화성 수지 조성물을 필름상으로 성형한 접착 필름을 예로 설명했지만, 본 발명에 관련된 접착제는 이것에 한정되지 않고, 예를 들어 바인더 수지층(13)만으로 이루어지는 절연성 접착 필름이어도 된다. 또, 본 발명에 관련된 접착제는, 바인더 수지층(13)만으로 이루어지는 절연성 접착제층과 도전성 입자(12)를 함유한 바인더 수지층(13)으로 이루어지는 도전성 입자 함유층을 적층한 구성으로 할 수 있다. 또, 접착제는, 이와 같은 필름 성형되어 이루어지는 접착 필름에 한정되지 않고, 바인더 수지 조성물에 도전성 입자(12)가 분산된 도전성 접착 페이스트, 혹은 바인더 수지 조성물만으로 이루어지는 절연성 접착 페이스트로 해도 된다. 본 발명에 관련된 접착제는, 상기 서술한 어느 형태도 포함하는 것이다.Further, in the above-described embodiment, as an adhesive, an adhesive film obtained by molding a thermosetting resin composition appropriately containing conductive particles 12 in a binder resin layer 13 into a film shape has been described as an example, but the adhesive according to the present invention has this It is not limited thereto, and may be, for example, an insulating adhesive film composed only of the binder resin layer 13. Further, the adhesive according to the present invention may have a structure in which an insulating adhesive layer composed of only the binder resin layer 13 and a conductive particle-containing layer composed of the binder resin layer 13 containing conductive particles 12 are laminated. In addition, the adhesive is not limited to such a film-formed adhesive film, and may be a conductive adhesive paste in which conductive particles 12 are dispersed in a binder resin composition or an insulating adhesive paste composed only of a binder resin composition. The adhesive according to the present invention includes any of the forms described above.

[접속 공정][Splicing process]

이어서, 회로 기판(14)에 IC칩(1)을 접속하는 접속 공정에 대해 설명한다. 먼저, 회로 기판(14)의 전극 단자(15)가 형성된 실장부 상에 이방성 도전 필름(10)을 가부착한다. 이어서, 이 회로 기판(14)을 접속 장치의 스테이지 상에 재치(載置)하고, 회로 기판(14)의 실장부 상에 이방성 도전 필름(10)을 개재하여 IC칩(1)을 배치한다.Next, a connection process for connecting the IC chip 1 to the circuit board 14 will be described. First, the anisotropic conductive film 10 is temporarily attached on the mounting portion of the circuit board 14 where the electrode terminal 15 is formed. Next, this circuit board 14 is placed on a stage of a connection device, and the IC chip 1 is placed on the mounting portion of the circuit board 14 with the anisotropic conductive film 10 interposed therebetween.

이어서, 바인더 수지층(13)을 경화시키는 소정 온도로 가열된 열압착 헤드(17)에 의해, 소정 압력, 시간으로 IC칩(1) 상으로부터 열가압한다. 이것에 의해, 이방성 도전 필름(10)의 바인더 수지층(13)은 유동성을 나타내고, IC칩(1)의 실장면(2)과 회로 기판(14)의 실장부 사이로부터 유출됨과 함께, 바인더 수지층(13) 중의 도전성 입자(12)는, IC칩(1)의 출력 범프(3) 및 입력 범프(5)와 회로 기판(14)의 전극 단자(15) 사이에서 협지되어 눌려 찌그러진다.Next, thermal pressure is applied from the top of the IC chip 1 at a predetermined pressure and time using the thermal compression head 17 heated to a predetermined temperature to cure the binder resin layer 13 . As a result, the binder resin layer 13 of the anisotropic conductive film 10 exhibits fluidity, flows out between the mounting surface 2 of the IC chip 1 and the mounting portion of the circuit board 14, and the number of binders increases. The conductive particles 12 in the paper layer 13 are pinched between the output bumps 3 and the input bumps 5 of the IC chip 1 and the electrode terminals 15 of the circuit board 14 and are crushed.

이때, 본 발명이 적용된 IC칩(1)에 의하면, 출력 범프 영역(4)을 IC 폭(W)에 대해 4％ 이상의 거리만큼, 일방의 측가장자리(2a)로부터 내측에 형성함으로써, 출력 범프 영역(4)의 폭 방향에 걸쳐 형성되어 있는 압력 구배가 평균화되고, 열압착 헤드(17)에 의한 압박력이 츨력 범프 영역(4) 전역에 있어서 대략 균등하게 가해져, 당해 일방의 측가장자리(2a)측에 있어서 압박력이 부족한 사태가 방지되고 있다.At this time, according to the IC chip 1 to which the present invention is applied, the output bump region 4 is formed on the inside from one side edge 2a by a distance of 4% or more with respect to the IC width W, so that the output bump region The pressure gradient formed over the width direction of (4) is averaged, and the pressing force by the thermocompression bonding head 17 is applied substantially equally over the entire output bump area 4, and the one side edge 2a side The situation where there is insufficient pressure is prevented.

그 결과, 출력 범프(3) 및 입력 범프(5)와 회로 기판(14)의 전극 단자(15) 사이에서 도전성 입자(12)를 협지함으로써 전기적으로 접속되고, 이 상태에서 열압착 헤드(17)에 의해 가열된 바인더 수지가 경화된다. 따라서, IC칩(1)은, 당해 일방의 측가장자리(2a)측의 출력 범프(3)에 있어서도 회로 기판(14)에 형성된 전극 단자(15)와의 사이에서 확실하게 도통성을 확보할 수 있다.As a result, they are electrically connected by holding the conductive particles 12 between the output bump 3 and the input bump 5 and the electrode terminal 15 of the circuit board 14, and in this state, the thermocompression bonding head 17 As a result, the heated binder resin is cured. Accordingly, the IC chip 1 can reliably ensure conductivity between the electrode terminals 15 formed on the circuit board 14 even at the output bumps 3 on the one side edge 2a side. .

출력 범프(3) 및 입력 범프(5)와 전극 단자(15) 사이에 없는 도전성 입자(12)는, 바인더 수지에 분산되어 있고, 전기적으로 절연된 상태를 유지하고 있다. 이것에 의해, IC칩(1)의 출력 범프(3) 및 입력 범프(5)와 회로 기판(14)의 전극 단자(15) 사이에서만 전기적 도통이 도모된다. 또한 바인더 수지로서, 라디칼 중합 반응계의 속경화 타입의 것을 사용함으로써, 짧은 가열 시간에 의해서도 바인더 수지를 속경화시킬 수 있다. 또, 이방성 도전 필름(10)으로서는, 열경화형에 한정하지 않고, 가압 접속을 행하는 것이면, 광경화형 혹은 광열 병용형의 접착제를 사용해도 된다.The conductive particles 12 that are not present between the output bump 3 and the input bump 5 and the electrode terminal 15 are dispersed in the binder resin and maintain an electrically insulated state. Thus, electrical conduction is achieved only between the output bumps 3 and 5 of the IC chip 1 and the electrode terminals 15 of the circuit board 14. In addition, by using a fast curing type of a radical polymerization reaction system as the binder resin, the binder resin can be cured quickly even with a short heating time. In addition, the anisotropic conductive film 10 is not limited to a thermosetting type, and a photocuring type or light-heat combined type adhesive may be used as long as it is press-connected.

제 1 실시예Example 1

이어서, 본 발명의 제 1 실시예에 대해 설명한다. 제 1 실시예에서는, 출력 범프 영역 및 입력 범프 영역에 면적차를 가짐과 함께 실장면에 비대칭으로 배치된 IC칩을 사용하고, 이방성 도전 필름을 개재하여 회로 기판 상에 접속한 접속체 샘플을 제조했다. 실시예 및 비교예에 관련된 IC칩은, IC 폭 및 실장면의 일방의 측가장자리(2a)로부터 출력 범프 영역까지의 거리(A)를 다르게 하고, 각각 접속체 샘플에 있어서의 출력 범프 및 입력 범프의 도통 저항값을 측정, 평가했다. Next, the first embodiment of the present invention will be described. In the first embodiment, an IC chip having an area difference between the output bump region and the input bump region and disposed asymmetrically on the mounting surface is used, and a connection body sample connected on a circuit board through an anisotropic conductive film is manufactured did. In the IC chips related to Examples and Comparative Examples, the IC width and the distance A from one side edge 2a of the mounting surface to the output bump region are different, and the output bump and input bump in each connected body sample are different. The conduction resistance value of was measured and evaluated.

실시예 및 비교예에 관련된 IC칩은, 대략 사각형상의 실장면(2)의 길이 방향이 되는 서로 대향하는 1쌍의 측가장자리(2a, 2b)를 따라, 출력 범프(3)가 배열된 출력 범프 영역(4) 및 입력 범프(5)가 배열된 입력 범프 영역(6)이 형성되어 있다. IC칩(1)은, 출력 범프 영역(4)이 실장면(2)의 일방의 측가장자리(2a)측에 형성되고, 입력 범프 영역(6)이 실장면(2)의 타방의 측가장자리(2b)측에 형성되어 있다. 이것에 의해, IC칩(1)은, 실장면의 폭 방향에 걸쳐 출력 범프 영역(4)과 입력 범프 영역(6)이 이간되어 형성되어 있다(도 1 참조).The IC chips related to Examples and Comparative Examples are output bumps in which output bumps 3 are arranged along a pair of opposite side edges 2a and 2b in the longitudinal direction of a substantially rectangular mounting surface 2. An input bump region 6 in which the region 4 and the input bump 5 are arranged is formed. In the IC chip 1, the output bump region 4 is formed on one side edge 2a side of the mounting surface 2, and the input bump region 6 is formed on the other side edge of the mounting surface 2 ( It is formed on the side of 2b). As a result, the IC chip 1 is formed such that the output bump region 4 and the input bump region 6 are separated from each other across the width direction of the mounting surface (see Fig. 1).

출력 범프 영역(4)에는, 동일 형상으로 형성된 복수의 출력 범프(3)가, 실장면(2)의 길이 방향을 따라 3열로 지그재그상으로 배열되어 있다. 출력 범프 영역(4)에 형성되어 있는 출력 범프를 열마다 나누고, 일방의 측가장자리(2a)측으로부터 순서대로 출력 범프열 (3A, 3B, 3C) 로 한다. 각 열에 형성되어 있는 출력 범프(3)는 사각형상을 이루고(면적 : 1437.5㎛2, 폭 : 12.5㎛, 길이 : 115㎛), 출력 범프열(3A, 3B, 3C)마다 1276개 배열되어 있다. 각 범프열(3A, 3B, 3C)에 있어서의 출력 범프(3)의 전체 면적은, 각각 1834250㎛2이다. 출력 범프 영역(4)의 전체 면적은, 12919500㎛2(폭 : 31900㎛, 길이 : 405㎛)이다.In the output bump region 4 , a plurality of output bumps 3 formed in the same shape are arranged in a zigzag pattern in three rows along the longitudinal direction of the mounting surface 2 . The output bumps formed in the output bump area|region 4 are divided for each row, and it is set as output bump rows 3A, 3B, and 3C in order from one side edge 2a side. The output bumps 3 formed in each row form a square shape (area: 1437.5 μm 2 , width: 12.5 μm, length: 115 μm), and 1276 are arranged for each output bump row 3A, 3B, 3C. The total area of the output bumps 3 in each of the bump rows 3A, 3B, and 3C is 1834250 μm 2 respectively. The total area of the output bump region 4 is 12919500 μm 2 (width: 31900 μm, length: 405 μm).

또, 입력 범프 영역(6)에는, 동일 형상으로 형성된 복수의 입력 범프(5)가, 실장면(2)의 길이 방향을 따라 1열로 배열되어 있다. 입력 범프 영역(6)에 형성되어 있는 1열의 입력 범프열을, 입력 범프열(5A)로 한다. 입력 범프열(5A)에 배열되어 있는 입력 범프(5)는, 사각형상을 이루고(면적 : 3600㎛2, 폭 : 45.0㎛, 길이 : 80㎛), 515개 배열되어 있다. 입력 범프열(5A)에 있어서의 입력 범프(5)의 전체 면적은, 1854000㎛2이다. 입력 범프 영역(6)의 전체 면적은, 2553040㎛2(폭 : 31913㎛, 길이 : 80㎛)이다.Further, in the input bump region 6 , a plurality of input bumps 5 formed in the same shape are arranged in a row along the longitudinal direction of the mounting surface 2 . One row of input bump rows formed in the input bump region 6 is referred to as an input bump row 5A. The input bumps 5 arranged in the input bump row 5A have a rectangular shape (area: 3600 μm 2 , width: 45.0 μm, length: 80 μm), and 515 are arranged. The total area of the input bumps 5 in the input bump row 5A is 1854000 µm 2 . The total area of the input bump region 6 is 2553040 μm 2 (width: 31913 μm, length: 80 μm).

[실시예 1][Example 1]

*실시예 1에 관련된 IC칩은, 실장면(2)의 서로 대향하는 측가장자리(2a, 2b) 사이에 걸치는 IC 폭(W)이 1.5㎜, 입출력 범프(3, 5)의 배열 방향이 되는 IC 길이가 32㎜이다. 또, 일방의 측가장자리(2a)로부터 출력 범프 영역(4)까지의 거리(A)는 150㎛이고, IC 폭(W)(1.5㎜)에 대한 10％의 거리이다. 또, 실시예 1에 관련된 IC칩은, 출력 범프 영역(4)과 입력 범프 영역(6) 사이에 더미 범프 영역은 형성하지 않고, 또 타방의 측가장자리(2b)로부터 입력 범프 영역(6)까지의 거리(B)는 50㎛이다.* In the IC chip related to Example 1, the IC width W extending between the opposite side edges 2a and 2b of the mounting surface 2 is 1.5 mm, and the direction of arrangement of the input/output bumps 3 and 5 is The IC length is 32 mm. Further, the distance A from one side edge 2a to the output bump region 4 is 150 µm, which is 10% of the IC width W (1.5 mm). Further, in the IC chip according to the first embodiment, no dummy bump area is formed between the output bump area 4 and the input bump area 6, and the area extends from the other side edge 2b to the input bump area 6. The distance (B) of is 50 μm.

[실시예 2][Example 2]

실시예 2에 관련된 IC칩은, 일방의 측가장자리(2a)로부터 출력 범프 영역(4)까지의 거리(A)를 100㎛로 한 것 이외에는 실시예 1과 동일한 조건으로 했다. 실시예 2에 있어서의 거리(A)는, IC 폭(W)(1.5㎜)에 대해 6.6％의 거리가 된다.The IC chip according to Example 2 was made under the same conditions as Example 1 except that the distance A from one side edge 2a to the output bump region 4 was 100 µm. The distance A in Example 2 is 6.6% of the distance with respect to the IC width W (1.5 mm).

[실시예 3][Example 3]

실시예 3에 관련된 IC칩은, 일방의 측가장자리(2a)로부터 출력 범프 영역(4)까지의 거리(A)를 75㎛로 한 것 이외에는 실시예 1과 동일한 조건으로 했다. 실시예 3에 있어서의 거리(A)는, IC 폭(W)(1.5㎜)에 대해 5.0％의 거리가 된다.The IC chip according to Example 3 was made under the same conditions as Example 1 except that the distance A from one side edge 2a to the output bump region 4 was 75 µm. The distance A in Example 3 is a distance of 5.0% with respect to the IC width W (1.5 mm).

[실시예 4] [Example 4]

실시예 4에 관련된 IC칩은, 일방의 측가장자리(2a)로부터 출력 범프 영역(4)까지의 거리(A)를 62.5㎛로 한 것 이외에는 실시예 1과 동일한 조건으로 했다. 실시예 4에 있어서의 거리(A)는, IC 폭(W)(1.5㎜)에 대해 4.2％의 거리가 된다.The IC chip according to Example 4 was made under the same conditions as Example 1 except that the distance A from one side edge 2a to the output bump region 4 was 62.5 µm. The distance A in Example 4 is 4.2% of the distance with respect to the IC width W (1.5 mm).

[실시예 5][Example 5]

실시예 5에 관련된 IC칩은, 실장면(2)의 서로 대향하는 측가장자리(2a, 2b) 사이에 걸치는 IC 폭(W)이 2.0㎜, 입출력 범프(3, 5)의 배열 방향이 되는 IC 길이가 32㎜이다. 또, 일방의 측가장자리(2a)로부터 출력 범프 영역(4)까지의 거리(A)는 83㎛이고, IC 폭(W)(2.0㎜)에 대한 4.2％의 거리이다. 또, 실시예 5에 관련된 IC칩은, 출력 범프 영역(4)과 입력 범프 영역(6) 사이에 더미 범프 영역은 형성하지 않고, 또 타방의 측가장자리(2b)로부터 입력 범프 영역(6)까지의 거리(B)는 50㎛이다.In the IC chip according to Example 5, the IC width W extending between the opposite side edges 2a and 2b of the mounting surface 2 is 2.0 mm, and the input/output bumps 3 and 5 are aligned in the direction of arrangement. It is 32 mm long. Further, the distance A from one side edge 2a to the output bump region 4 is 83 µm, which is 4.2% of the IC width W (2.0 mm). Further, in the IC chip according to the fifth embodiment, no dummy bump area is formed between the output bump area 4 and the input bump area 6, and the area extends from the other side edge 2b to the input bump area 6. The distance (B) of is 50 μm.

[실시예 6][Example 6]

실시예 6에 관련된 IC칩은, 실장면(2)의 서로 대향하는 측가장자리(2a, 2b) 사이에 걸치는 IC 폭(W)이 3.0㎜, 입출력 범프(3, 5)의 배열 방향이 되는 IC 길이가 32㎜이다. 또, 일방의 측가장자리(2a)로부터 출력 범프 영역(4)까지의 거리(A)는 125㎛이고, IC 폭(W)(3.0㎜)에 대한 4.2％의 거리이다. 또, 실시예 6에 관련된 IC칩은, 출력 범프 영역(4)과 입력 범프 영역(6) 사이에 더미 범프 영역은 형성하지 않고, 또 타방의 측가장자리(2b)로부터 입력 범프 영역(6)까지의 거리(B)는 50㎛이다.In the IC chip according to Example 6, the IC width W extending between the opposite side edges 2a and 2b of the mounting surface 2 is 3.0 mm and the input/output bumps 3 and 5 are aligned in the direction of arrangement. It is 32 mm long. Further, the distance A from one side edge 2a to the output bump region 4 is 125 µm, which is 4.2% of the IC width W (3.0 mm). Further, in the IC chip according to the sixth embodiment, no dummy bump area is formed between the output bump area 4 and the input bump area 6, and the area extends from the other side edge 2b to the input bump area 6. The distance (B) of is 50 μm.

[비교예 1][Comparative Example 1]

비교예 1에 관련된 IC칩은, 일방의 측가장자리(2a)로부터 출력 범프 영역(4)까지의 거리(A)를 50㎛로 한 것 이외에는 실시예 1과 동일한 조건으로 했다. 비교예 1에 있어서의 거리(A)는, IC 폭(W)(1.5㎜)에 대해 3.3％의 거리가 된다.The IC chip according to Comparative Example 1 was made under the same conditions as in Example 1 except that the distance A from one side edge 2a to the output bump region 4 was 50 µm. The distance A in Comparative Example 1 is 3.3% of the IC width W (1.5 mm).

[비교예 2][Comparative Example 2]

비교예 2에 관련된 IC칩은, 출력 범프 영역(4)과 입력 범프 영역(6) 사이에 더미 범프 영역 D를 형성한 것 이외에는, 비교예 1과 동일한 조건으로 했다. 더미 범프 영역 D는, 더미 범프가 IC칩의 길이 방향으로 1열로 배열되어 있다. 각 더미 범프는, 사각형상을 이루고(면적 : 1250㎛2, 폭 : 12.5㎛, 길이 : 100㎛), 1276개 배열되어 있다. 더미 범프열 D에 있어서의 더미 범프의 전체 면적은, 1595000㎛2이다. 더미 범프 영역 D의 전체 면적은, 3190000㎛2(폭 : 31900㎛, 길이 : 100㎛)이다.The IC chip according to Comparative Example 2 was made under the same conditions as Comparative Example 1 except that the dummy bump region D was formed between the output bump region 4 and the input bump region 6. In the dummy bump region D, dummy bumps are arranged in one row in the longitudinal direction of the IC chip. Each dummy bump has a rectangular shape (area: 1250 μm 2 , width: 12.5 μm, length: 100 μm), and 1276 of them are arranged. The total area of the dummy bumps in the dummy bump row D is 1595000 µm 2 . The total area of the dummy bump region D is 3190000 μm 2 (width: 31900 μm, length: 100 μm).

이들 실시예 1∼6, 및 비교예 1∼2에 관련된 IC칩을, 이방성 도전 필름(상품명 CP36931-18AJ : 덱세리얼즈 주식회사 제조)을 개재하여 회로 기판에 접속해, 접속체 샘플을 제조했다. 접속 조건은, 150℃, 130㎫, 5sec이다. 각 접속체 샘플에 대해, 4단자법을 사용하여, 출력 범프열(3A, 3B, 3C), 입력 범프열(5A)에 있어서의 도통 저항을 측정했다. 측정의 결과, 도통 저항이 1.0Ω 이하인 경우를 OK로 하고, 1.0Ω을 초과하는 경우를 NG로 했다. 측정 결과를 표 1에 나타낸다.The IC chips according to Examples 1 to 6 and Comparative Examples 1 to 2 were connected to a circuit board via an anisotropic conductive film (trade name: CP36931-18AJ, manufactured by Dexerials Co., Ltd.) to prepare connected body samples. Connection conditions are 150 degreeC, 130 Mpa, and 5 sec. For each connected body sample, the conduction resistance in the output bump rows 3A, 3B, 3C and the input bump row 5A was measured using the 4-terminal method. As a result of the measurement, a case where the conduction resistance was 1.0 Ω or less was regarded as OK, and a case where the conduction resistance exceeded 1.0 Ω was regarded as NG. Table 1 shows the measurement results.

Figure 112022074566657-pat00001
Figure 112022074566657-pat00001

표 1에 나타내는 바와 같이, 실시예 1∼6에 있어서는, 출력 범프열(3A, 3B, 3C) 및 입력 범프열(5A) 모두에 있어서 도통 저항이 1.0Ω 이하가 되고, 일방의 측가장자리(2a)측에 배열되어 있는 출력 범프열(3A)의 각 출력 범프(3)에 있어서도 충분한 압박력으로 압입할 수 있는 것을 알 수 있다. 이것은, 실시예 1∼6에 있어서는, 일방의 측가장자리(2a)로부터 출력 범프 영역(4)까지의 거리(A)를 IC 폭(W)의 4％ 이상으로 했으므로, 출력 범프 영역(4)의 폭 방향에 걸친 압력 구배가 평균화된 것에 의한 것이다.As shown in Table 1, in Examples 1 to 6, the conduction resistance is 1.0 Ω or less in both the output bump rows 3A, 3B, and 3C and the input bump rows 5A, and one side edge 2a ) side, it can be seen that each output bump 3 of the output bump row 3A arranged on the side can also be pressed in with a sufficient pressing force. This is because in Examples 1 to 6, the distance A from one side edge 2a to the output bump region 4 was set to 4% or more of the IC width W, so the output bump region 4 This is because the pressure gradient across the width direction is averaged.

한편, 비교예 1에서는, 출력 범프열(3A, 3B)에 있어서의 도통 저항이 높아졌다. 이것은, 일방의 측가장자리(2a)로부터 출력 범프 영역(4)까지의 거리(A)가 IC 폭(W)의 3.3％이었으므로, 외측의 출력 범프열로 갈수록 열압착 헤드의 압박력이 약해지는 압력 구배가 된 것에 의한 것이다. 이 점으로부터, 일방의 측가장자리(2a)로부터 출력 범프 영역(4)까지의 거리(A)를 IC 폭(W)의 4％ 이상 형성하는 것이 바람직한 것을 알 수 있다.On the other hand, in Comparative Example 1, the conduction resistance in the output bump trains 3A and 3B was high. This is because the distance A from one side edge 2a to the output bump region 4 was 3.3% of the IC width W, so the pressure gradient in which the pressing force of the thermocompression bonding head becomes weaker toward the outer output bump row. It is due to what has become. From this, it can be seen that it is preferable to form the distance A from one side edge 2a to the output bump region 4 by 4% or more of the IC width W.

또, 비교예 2에서는, 출력 범프 영역(4)과 입력 범프 영역(6) 사이에 더미 범프 영역 D를 형성했지만, 출력 범프열(3A, 3B)에 있어서의 도통 저항이 높아졌다. 이 점으로부터, 일방의 측가장자리(2a)로부터 출력 범프 영역(4)까지의 거리(A)가 IC 폭(W)의 3.3％인 경우, 더미 범프를 형성하는 것에 의해서는, 외측의 범프열에 있어서의 도통성을 개선할 정도의 압력 구배를 얻는 것은 곤란한 것을 알 수 있다.Further, in Comparative Example 2, although the dummy bump region D was formed between the output bump region 4 and the input bump region 6, the conduction resistance in the output bump rows 3A and 3B was high. From this point, when the distance A from one side edge 2a to the output bump region 4 is 3.3% of the IC width W, by forming dummy bumps, in the outer bump rows It is known that it is difficult to obtain a pressure gradient sufficient to improve the conductivity of

또한, 실시예 5, 6으로부터, 일방의 측가장자리(2a)로부터 출력 범프 영역(4)까지의 거리(A)를 IC 폭(W)의 4％ 이상으로 함으로써, IC 폭이 넓어져도 외측의 범프열에 있어서의 도통성을 개선할 수 있는 압력 구배가 얻어지는 것을 알 수 있다. Further, from Embodiments 5 and 6, by setting the distance A from one side edge 2a to the output bump region 4 to 4% or more of the IC width W, even if the IC width is widened, the outside bumps It can be seen that a pressure gradient capable of improving the conductivity in heat is obtained.

[제 2 실시형태][Second Embodiment]

이어서, 본 발명의 제 2 실시형태에 대해 설명한다. 이하의 설명에 있어서, 상기 서술한 제 1 실시형태에 관련된 부재와 동일한 부재에 대해서는, 동일한 부호를 붙이고 그 상세를 생략한다.Next, a second embodiment of the present invention will be described. In the following description, the same reference numerals are assigned to members identical to those of the first embodiment described above, and details thereof are omitted.

[전자 부품, 및 접속체][Electronic parts and connectors]

본 발명이 적용된 전자 부품은, 접착제를 개재하여 회로 기판 상에 배치되고, 열압착 헤드로 가압됨으로써 회로 기판 상에 접속되는 전자 부품이고, 예를 들어 드라이버 IC나 시스템 LSI 등의 패키지화된 전자 부품이다. 이하에서는, 전자 부품으로서 IC칩(1)을 예로 설명한다.The electronic component to which the present invention is applied is an electronic component that is placed on a circuit board via an adhesive and is connected to the circuit board by being pressed with a thermocompression bonding head, and is, for example, a packaged electronic component such as a driver IC or system LSI. . Below, the IC chip 1 is demonstrated as an example as an electronic component.

도 1에 나타내는 바와 같이, IC칩(1)의 회로 기판 상에 접속되는 실장면(2)은, 대략 사각형상을 이루고, 길이 방향이 되는 서로 대향하는 1쌍의 측가장자리(2a, 2b)를 따라, 출력 범프(3)가 배열된 출력 범프 영역(4) 및 입력 범프(5)가 배열된 입력 범프 영역(6)이 형성되어 있다. IC칩(1)은, 출력 범프 영역(4)이 실장면(2)의 일방의 측가장자리(2a)측에 형성되고, 입력 범프 영역(6)이 실장면(2)의 타방의 측가장자리(2b)측에 형성되어 있다. 이것에 의해, IC칩(1)은, 실장면(2)의 폭 방향에 걸쳐 출력 범프 영역(4)과 입력 범프 영역(6)이 이간되어 형성되어 있다.As shown in Fig. 1, the mounting surface 2 connected on the circuit board of the IC chip 1 has a substantially rectangular shape and has a pair of opposite side edges 2a and 2b in the longitudinal direction. Accordingly, an output bump region 4 in which the output bumps 3 are arranged and an input bump region 6 in which the input bumps 5 are arranged are formed. In the IC chip 1, the output bump region 4 is formed on one side edge 2a side of the mounting surface 2, and the input bump region 6 is formed on the other side edge of the mounting surface 2 ( It is formed on the side of 2b). As a result, the IC chip 1 is formed with the output bump region 4 and the input bump region 6 spaced apart across the width direction of the mounting surface 2 .

출력 범프 영역(4)에는, 예를 들어 동일 형상으로 형성된 복수의 출력 범프(3)가, 실장면(2)의 길이 방향을 따라 3열로 지그재그상으로 배열되어 있다. 또, 입력 범프 영역(6)에는, 예를 들어 동일 형상으로 형성된 복수의 입력 범프(5)가, 실장면(2)의 길이 방향을 따라 1열로 배열되어 있다. 또한, 입력 범프(5)는, 출력 범프(3)보다 크게 형성된다. 이것에 의해, IC칩(1)은, 출력 범프 영역(4)과 입력 범프 영역(6)이 면적차를 가짐과 함께, 실장면(2)에 있어서 비대칭으로 배치되어 있다. 또한, 출력 범프 영역(4)에 배열되어 있는 각 출력 범프(3)는, 각각 동일한 치수로 형성되는 것이 바람직하다. 마찬가지로, 입력 범프 영역(6)에 배열되어 있는 각 입력 범프(5)는, 각각 동일한 치수로 형성되는 것이 바람직하다. In the output bump region 4 , for example, a plurality of output bumps 3 formed in the same shape are arranged in a zigzag pattern in three rows along the longitudinal direction of the mounting surface 2 . Further, in the input bump region 6 , for example, a plurality of input bumps 5 formed in the same shape are arranged in a row along the longitudinal direction of the mounting surface 2 . Also, the input bump 5 is formed to be larger than the output bump 3 . As a result, in the IC chip 1, the output bump region 4 and the input bump region 6 have a difference in area and are arranged asymmetrically on the mounting surface 2. In addition, it is preferable that each of the output bumps 3 arranged in the output bump region 4 is formed to have the same dimensions. Similarly, each of the input bumps 5 arranged in the input bump region 6 is preferably formed to have the same dimensions.

도 5는, 도 1에 나타내는 전자 부품의 폭 방향의 실장면을 나타내는 단면도이다. 도 5에 나타내는 바와 같이 전자 부품으로서의 IC칩은, 제 1 측가장자리(2a)를 따라 범프열이 형성된 사각형상의 제 1 범프 영역으로서의 출력 범프 영역(4)과, 제 1 측가장자리(2a)에 대향하는 제 2 측가장자리(2b)를 따라 범프열이 형성된 사각형상의 제 2 범프 영역으로서의 입력 범프 영역(6)을 구비한다.5 is a cross-sectional view showing a mounting surface in the width direction of the electronic component shown in FIG. 1 . As shown in Fig. 5, an IC chip as an electronic component faces an output bump region 4 as a quadrangular first bump region in which a row of bumps is formed along the first side edge 2a, and the first side edge 2a. and an input bump region 6 as a quadrangular second bump region in which a row of bumps is formed along the second side edge 2b.

여기서, 제 1 범프 영역의 폭 방향의 거리(α)는, 제 2 범프 영역의 폭 방향의 거리(β)보다 크다(α＞β). 또, 제 1 측가장자리(2a)와 제 2 측가장자리(2b)의 거리(IC 폭 : W)에 대한 제 1 범프 영역의 폭 방향의 거리(α)와 제 2 범프 영역의 폭 방향의 거리(β)의 범프 영역 폭차(α-β)의 비율은, 5％∼30％인 것이 바람직하고, 10％∼25％인 것이 보다 바람직하다. 범프 영역 폭차(α-β)가 지나치게 작은 경우, 범프 영역 외측 간 중점을 이동시킬 필요성이 낮고, 범프 영역 폭차(α-β)가 지나치게 큰 경우, 범프 영역 외측 간 중점의 이동만으로는, 열압착 헤드에 의한 압력차를 해소해 접속 신뢰성을 향상시키는 것은 곤란해진다.Here, the distance α in the width direction of the first bump region is larger than the distance β in the width direction of the second bump region (α > β). In addition, the distance α in the width direction of the first bump region and the distance in the width direction of the second bump region relative to the distance (IC width: W) between the first side edge 2a and the second side edge 2b ( The ratio of the bump region width difference (α-β) of β) is preferably 5% to 30%, and more preferably 10% to 25%. When the bump area width difference (α-β) is too small, there is little need to move the midpoint between the outer sides of the bump area, and when the bump area width difference (α-β) is too large, only the movement of the midpoint between the outer sides of the bump area is enough, the thermocompression bonding head It becomes difficult to eliminate the pressure difference due to this and improve connection reliability.

또, 제 1 범프 영역의 폭 방향의 외측과 제 2 범프 영역의 폭 방향의 외측 사이의 범프 영역 외측 간 중점(A＋L2/2 or B＋L2/2)은, 제 1 측가장자리(2a)와 제 2 측가장자리(2b) 사이의 측가장자리 간 중점(W/2)보다, 제 2 측가장자리(2b)측에 존재한다. 즉, 제 1 측가장자리(2a)로부터 제 1 범프 영역까지의 거리(A)와, 제 2 측가장자리(2b)로부터 제 2 범프 영역까지의 거리(B)의 관계는, A＞B이다.Further, the midpoint (A+L2/2 or B+L2/2) between the outer side of the bump area between the outer side in the width direction of the first bump area and the outer side in the width direction of the second bump area is the first side edge 2a and the second side edge 2a. It exists on the side of the 2nd side edge 2b rather than the midpoint (W/2) between the side edges between the edges 2b. That is, the relationship between the distance A from the first side edge 2a to the first bump area and the distance B from the second side edge 2b to the second bump area is A>B.

이것에 의해, IC칩(1)은, 도 2에 나타내는 바와 같이 열압착 헤드(17)에 의해 회로 기판(14) 상에 가열 압박되었을 때에, 압박력이 출력 범프 영역(4)의 내측에 편재하는 것을 방지해, 일방의 측가장자리(2a)측에 배열되어 있는 출력 펌프(3)에 대해서도 적정한 압박력을 가할 수 있다. As a result, when the IC chip 1 is heated and pressed onto the circuit board 14 by the thermocompression bonding head 17 as shown in FIG. 2, the pressing force is unevenly distributed inside the output bump region 4. This can be prevented, and an appropriate pressing force can be applied also to the output pump 3 arranged on one side edge 2a side.

또, 측가장자리 간 중점(W/2)으로부터 범프 영역 외측 간 중점(A＋L2/2 or B＋L2/2)까지의 거리(Δ), 즉 (A-B)/2가 클수록 출력 범프 영역(4)의 폭 방향에 걸쳐 형성되는 압력 구배가 완만하게 평균화된다. 구체적인 거리(Δ)로서는, 제 1 측가장자리(2a)와 제 2 측가장자리(2b)의 거리(W)의 0.1％∼5.0％인 것이 바람직하고, 0.3％∼3.5％인 것이 보다 바람직하다. 이것에 의해, 도 2에 나타내는 바와 같이 열압착 헤드(17)에 의해 실장면(2)의 전체면에 대해 압력을 가했을 때에, 일방의 측가장자리(2a)측에 있어서 열압착 헤드(17)에 의한 압박력이 부족한 사태를 방지할 수 있다. 따라서, IC칩(1)은, 당해 일방의 측가장자리(2a)측의 출력 범프(3)에 있어서도 회로 기판(14)에 형성된 전극 단자(15)와의 사이에서 확실하게 도전성 입자를 협지해, 도통성을 확보할 수 있다.In addition, the larger the distance (Δ) from the midpoint (W/2) between the side edges to the midpoint (A+L2/2 or B+L2/2) between the outer sides of the bump area, that is, (A-B)/2, the width direction of the output bump area 4 The pressure gradient that forms over it is smoothly averaged. As a specific distance (DELTA), it is preferable that it is 0.1% - 5.0% of the distance W of the 1st side edge 2a and the 2nd side edge 2b, and it is more preferable that it is 0.3% - 3.5%. As a result, as shown in FIG. 2, when pressure is applied to the entire surface of the mounting surface 2 by the thermocompression head 17, the thermocompression head 17 on one side edge 2a side It is possible to avoid situations in which the pressure is insufficient. Therefore, the IC chip 1 reliably holds the conductive particles between the electrode terminals 15 formed on the circuit board 14 even in the output bump 3 on the one side edge 2a side, and conducts the circuit. castle can be obtained.

또한, IC칩(1)의 실장면(2)의 입출력 범프의 구성은, 적절히 설계할 수 있다. IC칩(1)은, 상기 서술한 바와 같이 출력 범프(3)를 폭 방향으로 복수 배열함으로써 상대적으로 대면적화시킨 출력 범프 영역(4)을 형성했지만, 반대로 입력 범프(5)를 폭 방향으로 복수 배열함으로써 상대적으로 입력 범프 영역(6)을 대면적 화시켜도 된다.Further, the configuration of the input/output bumps on the mounting surface 2 of the IC chip 1 can be designed appropriately. In the IC chip 1, as described above, output bump regions 4 having a relatively large area are formed by arranging a plurality of output bumps 3 in the width direction, but conversely, a plurality of input bumps 5 are arranged in the width direction. By arranging, the area of the input bump region 6 may be relatively large.

또, 도 3에 나타내는 바와 같이, IC칩(1)은, 출력 범프 영역(4)과 입력 범프 영역(6) 사이에, 신호 등의 입출력에는 사용하지 않는 이른바 더미 범프(18)가 배열된 더미 범프 영역(19)을 적절히 형성해도 된다.As shown in Fig. 3, in the IC chip 1, between the output bump area 4 and the input bump area 6, so-called dummy bumps 18 that are not used for input/output of signals or the like are arranged. You may form the bump area|region 19 suitably.

[접착제][glue]

IC칩(1)을 회로 기판(14)에 접속하는 접착제로서는, 도 4에 나타내는 바와 같이 상기 서술한 이방성 도전 필름(10)(ACF : Anisotropic Conductive Film)을 바람직하게 사용할 수 있다.As an adhesive for connecting the IC chip 1 to the circuit board 14, as shown in Fig. 4, the above-described anisotropic conductive film 10 (ACF: Anisotropic Conductive Film) can be preferably used.

[접속체의 제조 방법, 및 접속 방법][Method of manufacturing connection body, and connection method]

이어서, 회로 기판(14)에 IC칩(1)을 접속하는 접속 방법에 대해 설명한다. 먼저, 회로 기판(14)의 전극 단자(15)가 형성된 실장부 상에 이방성 도전 필름(10)을 가부착한다. 이어서, 이 회로 기판(14)을 접속 장치의 스테이지 상에 재치하고, 회로 기판(14)의 실장부 상에 이방성 도전 필름(10)을 개재하여 IC칩(1)을 배치한다.Next, a connection method for connecting the IC chip 1 to the circuit board 14 will be described. First, the anisotropic conductive film 10 is temporarily attached on the mounting portion of the circuit board 14 where the electrode terminal 15 is formed. Next, this circuit board 14 is placed on the stage of the connection device, and the IC chip 1 is placed on the mounting portion of the circuit board 14 with the anisotropic conductive film 10 interposed therebetween.

이어서, 바인더 수지층(13)을 경화시키는 소정 온도로 가열된 열압착 헤드(17)에 의해, 소정 압력, 시간으로 IC칩(1) 상으로부터 열가압한다. 이것에 의해, 이방성 도전 필름(10)의 바인더 수지층(13)은 유동성을 나타내고, IC칩(1)의 실장면(2)과 회로 기판(14)의 실장부 사이로부터 유출됨과 함께, 바인더 수지층(13) 중의 도전성 입자(12)는, IC칩(1)의 출력 범프(3) 및 입력 범프(5)와 회로 기판(14)의 전극 단자(15) 사이에서 협지되어 눌려 찌그러진다. Next, thermal pressure is applied from the top of the IC chip 1 at a predetermined pressure and time using the thermal compression head 17 heated to a predetermined temperature to cure the binder resin layer 13 . As a result, the binder resin layer 13 of the anisotropic conductive film 10 exhibits fluidity, flows out between the mounting surface 2 of the IC chip 1 and the mounting portion of the circuit board 14, and the number of binders increases. The conductive particles 12 in the paper layer 13 are pinched between the output bumps 3 and the input bumps 5 of the IC chip 1 and the electrode terminals 15 of the circuit board 14 and are crushed.

그 결과, 출력 범프(3) 및 입력 범프(5)와 회로 기판(14)의 전극 단자(15) 사이에서 도전성 입자(12)를 협지함으로써 전기적으로 접속되고, 이 상태에서 열압착 헤드(17)에 의해 가열된 바인더 수지가 경화된다. 따라서, IC칩(1)은, 당해 일방의 측가장자리(2a)측의 출력 범프(3)에 있어서도 회로 기판(14)에 형성된 전극 단자(15)와의 사이에서 확실하게 도통성을 확보할 수 있다.As a result, they are electrically connected by holding the conductive particles 12 between the output bump 3 and the input bump 5 and the electrode terminal 15 of the circuit board 14, and in this state, the thermocompression bonding head 17 As a result, the heated binder resin is cured. Accordingly, the IC chip 1 can reliably ensure conductivity between the electrode terminals 15 formed on the circuit board 14 even at the output bumps 3 on the one side edge 2a side. .

출력 범프(3) 및 입력 범프(5)와 전극 단자(15) 사이에 없는 도전성 입자(12)는, 바인더 수지에 분산되어 있고, 전기적으로 절연된 상태를 유지하고 있다. 이것에 의해, IC칩(1)의 출력 범프(3) 및 입력 범프(5)와 회로 기판(14)의 전극 단자(15) 사이에서만 전기적 도통이 도모된다. 또한, 바인더 수지로서, 라디칼 중합 반응계의 속경화 타입의 것을 사용함으로써, 짧은 가열 시간에 의해서도 바인더 수지를 속경화시킬 수 있다. 또, 이방성 도전 필름(10)으로서는, 열경화형에 한정되지 않고, 가압 접속을 행하는 것이면, 광경화형 혹은 광열 병용형의 접착제를 사용해도 된다.The conductive particles 12 that are not present between the output bump 3 and the input bump 5 and the electrode terminal 15 are dispersed in the binder resin and maintain an electrically insulated state. Thus, electrical conduction is achieved only between the output bumps 3 and 5 of the IC chip 1 and the electrode terminals 15 of the circuit board 14. In addition, by using a fast curing type of a radical polymerization reaction system as the binder resin, the binder resin can be cured quickly even with a short heating time. In addition, as the anisotropic conductive film 10, it is not limited to a thermosetting type, and a photocuring type or light-heat combined type adhesive may be used as long as it is press-connected.

제 2 실시예2nd embodiment

이어서, 본 발명의 제 2 실시예에 대해 설명한다. 제 2 실시예에서는, 제 1 범프 영역으로서의 출력 범프 영역과, 제 2 범프 영역으로서의 입력 범프 영역을 갖는 IC칩을 사용하고, 이방성 도전 필름을 개재하여 회로 기판 상에 접속한 접속체 샘플을 제조했다. 실시예 및 비교예에 관련된 IC칩은, IC 폭 및 실장면의 일방의 측가장자리(2a)로부터 출력 범프 영역까지의 거리(A)를 다르게 하고, 각각 접속체 샘플에 있어서의 출력 범프 및 입력 범프의 도통 저항값을 측정, 평가했다.Next, a second embodiment of the present invention will be described. In the second embodiment, an IC chip having an output bump region as a first bump region and an input bump region as a second bump region was used, and a connected body sample connected on a circuit board through an anisotropic conductive film was manufactured. . In the IC chips related to Examples and Comparative Examples, the IC width and the distance A from one side edge 2a of the mounting surface to the output bump region are different, and the output bump and input bump in each connected body sample are different. The conduction resistance value of was measured and evaluated.

[IC칩][IC Chip]

IC칩은, 대략 사각형상의 실장면(2)의 길이 방향이 되는 서로 대향하는 1쌍의 측가장자리(2a, 2b)를 따라, 출력 범프(3)가 배열된 출력 범프 영역(4) 및 입력 범프(5)가 배열된 입력 범프 영역(6)이 형성되어 있다. IC칩(1)은, 출력 범프 영역(4)이 실장면(2)의 일방의 측가장자리(2a)측에 형성되고, 입력 범프 영역(6)이 실장면(2)의 타방의 측가장자리(2b)측에 형성되어 있다. 이것에 의해, IC칩(1)은, 실장면의 폭 방향에 걸쳐 출력 범프 영역(4)과 입력 범프 영역(6)이 이간되어 형성되어 있다(도 1, 도 5 참조).The IC chip has an output bump region 4 in which output bumps 3 are arranged along a pair of opposite side edges 2a and 2b in the longitudinal direction of the substantially rectangular mounting surface 2 and an input bump An input bump region 6 in which (5) is arranged is formed. In the IC chip 1, the output bump region 4 is formed on one side edge 2a side of the mounting surface 2, and the input bump region 6 is formed on the other side edge of the mounting surface 2 ( It is formed on the side of 2b). As a result, the IC chip 1 is formed such that the output bump region 4 and the input bump region 6 are separated from each other across the width direction of the mounting surface (see Figs. 1 and 5).

출력 범프 영역(4)에는, 동일 형상으로 형성된 복수의 출력 범프(3)가, 실장면(2)의 길이 방향을 따라 3열로 지그재그상으로 배열되어 있다. 출력 범프 영역(4)에 형성되어 있는 출력 범프를 열마다 나누고, 일방의 측가장자리(2a)측으로부터 순서대로 출력 범프열(3A, 3B, 3C)로 한다.In the output bump region 4 , a plurality of output bumps 3 formed in the same shape are arranged in a zigzag pattern in three rows along the longitudinal direction of the mounting surface 2 . The output bumps formed in the output bump region 4 are divided for each column, and are set as output bump columns 3A, 3B, and 3C in order from one side edge 2a side.

또, 입력 범프 영역(6)에는, 동일 형상으로 형성된 복수의 입력 범프(5)가, 실장면(2)의 길이 방향을 따라 1열로 배열되어 있다. 입력 범프 영역(6)에 형성되어 있는 1열의 입력 범프열을, 입력 범프열(5A)로 한다.Further, in the input bump region 6 , a plurality of input bumps 5 formed in the same shape are arranged in a row along the longitudinal direction of the mounting surface 2 . One row of input bump rows formed in the input bump region 6 is referred to as an input bump row 5A.

[도통 저항의 평가] [Evaluation of conduction resistance]

IC칩을, 이방성 도전 필름(상품명 CP36931-18AJ : 덱세리얼즈 주식회사 제조)을 개재하여 회로 기판에 접속해, 접속체 샘플을 제작했다. 접속 조건은, 150℃, 130㎫, 5sec로 했다. 각 접속체 샘플에 대해, 4단자법을 사용하여 출력 범프열(3A, 3B, 3C), 입력 범프열(5A)에 있어서의 도통 저항을 측정했다. 측정의 결과, 모든 범프열의 도통 저항이 1.0Ω 이하인 경우를 「OK」로 하고, 1 이상인 범프열이 1.0Ω을 초과하는 경우를 NG로 했다.The IC chip was connected to the circuit board via an anisotropic conductive film (trade name CP36931-18AJ: manufactured by Dexerials Co., Ltd.) to prepare a connected body sample. Connection conditions were 150 degreeC, 130 Mpa, and 5 sec. About each connection body sample, the conduction resistance in the output bump row 3A, 3B, 3C and the input bump row 5A was measured using the 4-terminal method. As a result of the measurement, a case where the conduction resistance of all the bump rows was 1.0 Ω or less was regarded as "OK", and a case where the bump row of 1 or more exceeded 1.0 Ω was regarded as NG.

[실시예 7][Example 7]

표 2에 나타내는 바와 같이, IC 폭(W)이 1500㎛, 출력 범프 영역(4)의 일방의 측가장자리(2a)로부터의 거리(A)가 60㎛, 출력 범프 영역(4)의 폭(α)이 385㎛, 입력 범프 영역(6)의 타방의 측가장자리(2b)로부터의 거리(B)가 50㎛, 입력 범프 영역(6)의 폭(β)이 80㎛, 및 범프 영역 폭차의 IC 폭(W)에 대한 비율이 20.3％인 IC칩을 준비했다.As shown in Table 2, the IC width (W) is 1500 μm, the distance (A) from one side edge 2a of the output bump region 4 is 60 μm, and the width (α) of the output bump region 4 is ) is 385 μm, the distance B from the other side edge 2b of the input bump region 6 is 50 μm, the width β of the input bump region 6 is 80 μm, and the IC of the bump region width difference An IC chip having a ratio of 20.3% to the width W was prepared.

출력 범프 영역(4)의 폭 방향의 내측과 입력 범프 영역(6)의 폭 방향의 내측 사이의 범프 영역 내측 간 거리(L1)는 925㎛였다. 출력 범프 영역(4)의 폭 방향의 외측과 입력 범프 영역(6)의 폭 방향의 외측 사이의 범프 영역 외측 간 거리(L2)는 1390㎛였다. IC 폭 중점(W/2)으로부터 범프 영역 외측 간 중점(A＋L2/2)까지의 거리(Δ)는 5.0㎛이고, IC 폭(W)에 대한 비율은 0.33％였다.The distance L1 between the inside of the bump region between the inside of the output bump region 4 in the width direction and the inside of the input bump region 6 in the width direction was 925 μm. The distance L2 between the outside of the output bump region 4 in the width direction and the outside of the input bump region 6 in the width direction was 1390 µm. The distance (Δ) from the midpoint of the IC width (W/2) to the midpoint between the outer sides of the bump region (A+L2/2) was 5.0 µm, and the ratio to the IC width (W) was 0.33%.

실시예 7의 IC칩을 접속한 접속체 샘플에 있어서의 출력 범프열(3A, 3B, 3C), 입력 범프열(5A)의 도통 저항의 측정 결과는, 각각 1.0Ω, 0.9Ω, 0.4Ω, 0.1Ω이고, OK의 평가였다.The measurement results of the conduction resistances of the output bump rows 3A, 3B, and 3C and the input bump rows 5A in the connected body sample to which the IC chips of Example 7 were connected were 1.0 Ω, 0.9 Ω, 0.4 Ω, It was 0.1 Ω, and it was an evaluation of OK.

[실시예 8] [Example 8]

표 2에 나타내는 바와 같이, 출력 범프 영역(4)의 일방의 측가장자리(2a)로부터의 거리(A)를 75㎛로 한 것 이외에는, 실시예 7과 동일한 IC칩을 준비했다. 출력 범프 영역(4)의 폭 방향의 내측과 입력 범프 영역(6)의 폭 방향의 내측 사이의 범프 영역 내측 간 거리(L1)는 910㎛였다. 출력 범프 영역(4)의 폭 방향의 외측과 입력 범프 영역(6)의 폭 방향의 외측 사이의 범프 영역 외측 간 거리(L2)는 1375㎛였다. IC 폭 중점(W/2)으로부터 범프 영역 외측 간 중점(A＋L2/2)까지의 거리(Δ)는 12.5㎛이고, IC 폭(W)에 대한 비율은 0.83％였다.As shown in Table 2, the same IC chip as in Example 7 was prepared except that the distance A from the side edge 2a on one side of the output bump region 4 was 75 µm. The distance L1 between the inside of the bump region between the inside of the output bump region 4 in the width direction and the inside of the input bump region 6 in the width direction was 910 μm. The distance L2 between the outside of the output bump region 4 in the width direction and the outside of the input bump region 6 in the width direction was 1375 µm. The distance (Δ) from the midpoint of the IC width (W/2) to the midpoint between the outer sides of the bump region (A+L2/2) was 12.5 μm, and the ratio to the IC width (W) was 0.83%.

실시예 8의 IC칩을 접속한 접속체 샘플에 있어서의 출력 범프열(3A, 3B, 3C), 입력 범프열(5A)의 도통 저항의 측정 결과는, 각각 0.9Ω, 0.8Ω, 0.4Ω, 0.1Ω이고, OK의 평가였다.The measurement results of the conduction resistances of the output bump rows 3A, 3B, and 3C and the input bump rows 5A in the connected body sample to which the IC chips of Example 8 were connected were 0.9 Ω, 0.8 Ω, 0.4 Ω, It was 0.1 Ω, and it was an evaluation of OK.

[실시예 9][Example 9]

표 2에 나타내는 바와 같이, 출력 범프 영역(4)의 일방의 측가장자리(2a)로부터의 거리(A)를 150㎛로 한 것 이외에는, 실시예 7과 동일한 IC칩을 준비했다. 출력 범프 영역(4)의 폭 방향의 내측과 입력 범프 영역(6)의 폭 방향의 내측 사이의 범프 영역 내측 간 거리(L1)는 835㎛였다. 출력 범프 영역(4)의 폭 방향의 외측과 입력 범프 영역(6)의 폭 방향의 외측 사이의 범프 영역 외측 간 거리(L2)는 1300㎛였다. IC 폭 중점(W/2)으로부터 범프 영역 외측 간 중점(A＋L2/2)까지의 거리(Δ)는 50.0㎛이고, IC 폭(W)에 대한 비율은 3.33％였다.As shown in Table 2, the same IC chip as in Example 7 was prepared except that the distance A from the side edge 2a on one side of the output bump region 4 was 150 µm. The distance L1 between the inside of the bump region between the inside of the output bump region 4 in the width direction and the inside of the input bump region 6 in the width direction was 835 μm. The distance L2 between the outside of the output bump region 4 in the width direction and the outside of the input bump region 6 in the width direction was 1300 µm. The distance (Δ) from the midpoint of the IC width (W/2) to the midpoint between the outer sides of the bump region (A+L2/2) was 50.0 µm, and the ratio to the IC width (W) was 3.33%.

실시예 9의 IC칩을 접속한 접속체 샘플에 있어서의 출력 범프열(3A, 3B, 3C), 입력 범프열(5A)의 도통 저항의 측정 결과는, 각각 0.9Ω, 0.7Ω, 0.5Ω, 0.1Ω이고, OK의 평가였다.The measurement results of the conduction resistances of the output bump rows 3A, 3B, and 3C and the input bump rows 5A in the connected body sample to which the IC chips of Example 9 were connected were 0.9 Ω, 0.7 Ω, 0.5 Ω, It was 0.1 Ω, and it was an evaluation of OK.

[실시예 10][Example 10]

표 2에 나타내는 바와 같이, IC 폭(W)이 2000㎛, 출력 범프 영역(4)의 일방의 측가장자리(2a)로부터의 거리(A)가 63㎛, 출력 범프 영역(4)의 폭(α)이 385㎛, 입력 범프 영역(6)의 타방의 측가장자리(2b)로부터의 거리(B)가 50㎛, 입력 범프 영역(6)의 폭(β)이 80㎛, 및 범프 영역 폭차의 IC 폭(W)에 대한 비율이 15.3％인 IC칩을 준비했다.As shown in Table 2, the IC width (W) is 2000 μm, the distance (A) from one side edge 2a of the output bump region 4 is 63 μm, and the width (α) of the output bump region 4 is ) is 385 μm, the distance B from the other side edge 2b of the input bump region 6 is 50 μm, the width β of the input bump region 6 is 80 μm, and the IC of the bump region width difference An IC chip having a ratio of 15.3% to the width W was prepared.

출력 범프 영역(4)의 폭 방향의 내측과 입력 범프 영역(6)의 폭 방향의 내측 사이의 범프 영역 내측 간 거리(L1)는 1422㎛였다. 출력 범프 영역(4)의 폭 방향의 외측과 입력 범프 영역(6)의 폭 방향의 외측 사이의 범프 영역 외측 간 거리(L2)는 1887㎛였다. IC 폭 중점(W/2)으로부터 범프 영역 외측 간 중점(A＋L2/2)까지의 거리(Δ)는 6.5㎛이고, IC 폭(W)에 대한 비율은 0.33％였다.The distance L1 between the inside of the bump region between the inside of the output bump region 4 in the width direction and the inside of the input bump region 6 in the width direction was 1422 μm. The distance L2 between the outside of the output bump region 4 in the width direction and the outside of the input bump region 6 in the width direction was 1887 µm. The distance (Δ) from the midpoint of the IC width (W/2) to the midpoint between the outside of the bump region (A+L2/2) was 6.5 µm, and the ratio to the IC width (W) was 0.33%.

실시예 10의 IC칩을 접속한 접속체 샘플에 있어서의 출력 범프열(3A, 3B, 3C), 입력 범프열(5A)의 도통 저항의 측정 결과는, 각각 1.0Ω, 0.9Ω, 0.4Ω, 0.1Ω이고, OK의 평가였다.The measurement results of the conduction resistances of the output bump rows 3A, 3B, and 3C and the input bump rows 5A in the connected body sample to which the IC chips of Example 10 were connected were 1.0 Ω, 0.9 Ω, 0.4 Ω, It was 0.1 Ω, and it was an evaluation of OK.

[실시예 11][Example 11]

표 2에 나타내는 바와 같이, IC 폭(W)이 3000㎛, 출력 범프 영역(4)의 일방의 측가장자리(2a)로부터의 거리(A)가 70㎛, 출력 범프 영역(4)의 폭(α)이 385㎛, 입력 범프 영역(6)의 타방의 측가장자리(2b)로부터의 거리(B)가 50㎛, 입력 범프 영역(6)의 폭(β)이 80㎛, 및 범프 영역 폭차의 IC 폭(W)에 대한 비율이 10.2％인 IC칩을 준비했다.As shown in Table 2, the IC width (W) is 3000 μm, the distance (A) from one side edge 2a of the output bump region 4 is 70 μm, and the width (α) of the output bump region 4 is ) is 385 μm, the distance B from the other side edge 2b of the input bump region 6 is 50 μm, the width β of the input bump region 6 is 80 μm, and the IC of the bump region width difference An IC chip having a ratio of 10.2% to the width W was prepared.

출력 범프 영역(4)의 폭 방향의 내측과 입력 범프 영역(6)의 폭 방향의 내측 사이의 범프 영역 내측 간 거리(L1)는 2415㎛였다. 출력 범프 영역(4)의 폭 방향의 외측과 입력 범프 영역(6)의 폭 방향의 외측 사이의 범프 영역 외측 간 거리(L2)는 2880㎛였다. IC 폭 중점(W/2)으로부터 범프 영역 외측 간 중점(A＋L2/2)까지의 거리(Δ)는 10.0㎛이고, IC 폭(W)에 대한 비율은 0.33％였다. The distance L1 between the inside of the bump region between the inside of the output bump region 4 in the width direction and the inside of the input bump region 6 in the width direction was 2415 μm. The distance L2 between the outside of the output bump region 4 in the width direction and the outside of the input bump region 6 in the width direction was 2880 µm. The distance (Δ) from the midpoint of the IC width (W/2) to the midpoint between the outside of the bump region (A+L2/2) was 10.0 µm, and the ratio to the IC width (W) was 0.33%.

실시예 11의 IC칩을 접속한 접속체 샘플에 있어서의 출력 범프열(3A, 3B, 3C), 입력 범프열(5A)의 도통 저항의 측정 결과는, 각각 1.0Ω, 0.9Ω, 0.4Ω, 0.1Ω이고, OK의 평가였다.The measurement results of the conduction resistance of the output bump rows 3A, 3B, and 3C and the input bump rows 5A in the connected body sample to which the IC chips of Example 11 were connected were 1.0 Ω, 0.9 Ω, 0.4 Ω, It was 0.1 Ω, and it was an evaluation of OK.

[비교예 3][Comparative Example 3]

표 2에 나타내는 바와 같이, 출력 범프 영역(4)의 일방의 측가장자리(2a)로부터의 거리(A)를 50㎛로 하고, 더미 범프 영역을 형성한 것 이외에는, 실시예 7과 동일한 IC칩을 준비했다. 더미 범프 영역은, 출력 범프 영역(4)과 입력 범프 영역(6) 사이에 형성되고, 더미 범프가 IC칩의 길이 방향으로 1열로 배열되어 있다. 또한, 더미 범프열은, 입력 범프열(5A)과 동일하다.As shown in Table 2, the same IC chip as in Example 7 was used except that the distance A from the side edge 2a on one side of the output bump region 4 was 50 μm and a dummy bump region was formed. prepared The dummy bump region is formed between the output bump region 4 and the input bump region 6, and the dummy bumps are arranged in a row in the lengthwise direction of the IC chip. In addition, the dummy bump row is the same as the input bump row 5A.

출력 범프 영역(4)의 폭 방향의 내측과 입력 범프 영역(6)의 폭 방향의 내측 사이의 범프 영역 내측 간 거리(L1)는 935㎛였다. 출력 범프 영역(4)의 폭 방향의 외측과 입력 범프 영역(6)의 폭 방향의 외측 사이의 범프 영역 외측 간 거리(L2)는 1400㎛였다. IC 폭 중점(W/2)으로부터 범프 영역 외측 간 중점(A＋L2/2)까지의 거리(Δ)는 0㎛이고, IC 폭(W)에 대한 비율은 0％였다.The distance L1 between the inside of the output bump region 4 in the width direction and the inside of the input bump region 6 in the width direction was 935 μm. The distance L2 between the outside of the output bump region 4 in the width direction and the outside of the input bump region 6 in the width direction was 1400 µm. The distance (Δ) from the midpoint of the IC width (W/2) to the midpoint between the outer sides of the bump region (A+L2/2) was 0 µm, and the ratio to the IC width (W) was 0%.

비교예 3의 IC칩을 접속한 접속체 샘플에 있어서의 출력 범프열(3A, 3B, 3C), 입력 범프열(5A)의 도통 저항의 측정 결과는, 각각 2.3Ω, 1.2Ω, 0.5Ω, 0.1Ω이고, NG의 평가였다.The measurement results of the conduction resistances of the output bump rows 3A, 3B, and 3C and the input bump rows 5A in the connected body sample to which the IC chips of Comparative Example 3 were connected were 2.3 Ω, 1.2 Ω, 0.5 Ω, It was 0.1Ω and was an evaluation of NG.

[비교예 4] [Comparative Example 4]

표 2에 나타내는 바와 같이, 출력 범프 영역(4)의 일방의 측가장자리(2a)로부터의 거리(A)를 50㎛로 한 것 이외에는, 실시예 7과 동일한 IC칩을 준비했다. 출력 범프 영역(4)의 폭 방향의 내측과 입력 범프 영역(6)의 폭 방향의 내측 사이의 범프 영역 내측 간 거리(L1)는 935㎛였다. 출력 범프 영역(4)의 폭 방향의 외측과 입력 범프 영역(6)의 폭 방향의 외측 사이의 범프 영역 외측 간 거리(L2)는 1400㎛였다. IC 폭 중점(W/2)으로부터 범프 영역 외측 간 중점(A＋L2/2)까지의 거리(Δ)는 0㎛이고, IC 폭(W)에 대한 비율은 0％였다.As shown in Table 2, the same IC chip as in Example 7 was prepared except that the distance A from the side edge 2a on one side of the output bump region 4 was 50 µm. The distance L1 between the inside of the output bump region 4 in the width direction and the inside of the input bump region 6 in the width direction was 935 μm. The distance L2 between the outside of the output bump region 4 in the width direction and the outside of the input bump region 6 in the width direction was 1400 µm. The distance (Δ) from the midpoint of the IC width (W/2) to the midpoint between the outer sides of the bump region (A+L2/2) was 0 µm, and the ratio to the IC width (W) was 0%.

비교예 4의 IC칩을 접속한 접속체 샘플에 있어서의 출력 범프열(3A, 3B, 3C), 입력 범프열(5A)의 도통 저항의 측정 결과는, 각각 3.0Ω, 1.7Ω, 0.4Ω, 0.1Ω이고, NG의 평가였다.The measurement results of the conduction resistances of the output bump rows 3A, 3B, and 3C and the input bump rows 5A in the connected body sample to which the IC chips of Comparative Example 4 were connected were 3.0 Ω, 1.7 Ω, 0.4 Ω, It was 0.1Ω and was an evaluation of NG.

Figure 112022074566657-pat00002
Figure 112022074566657-pat00002

비교예 3과 같이 더미 범프를 형성한 경우, 출력 범프열(3A, 3B)에 있어서의 도통 저항이 높고, 외측의 범프열에 있어서의 도통성을 개선할 정도의 압력 구배를 얻는 것은 곤란했다. 또, 비교예 4와 같이 더미 범프를 형성하지 않은 경우, 출력 범프열(3A, 3B)에 있어서의 도통 저항이 비교예 3보다 높아졌다.When dummy bumps are formed as in Comparative Example 3, the conduction resistance in the output bump rows 3A and 3B is high, and it is difficult to obtain a pressure gradient sufficient to improve conduction in the outer bump rows. Further, when dummy bumps were not formed as in Comparative Example 4, the conduction resistance in the output bump rows 3A and 3B was higher than in Comparative Example 3.

한편, 실시예 7∼11과 같이, IC 폭 중점(W/2)으로부터 범프 영역 외측 간 중점(A＋L2/2)까지의 거리(Δ)를 IC 폭(W)의 0.3％∼3.5％로 한 경우, 출력 범프열(3A, 3B, 3C) 및 입력 범프열(5A) 모두에 있어서 도통 저항이 1.0Ω 이하가 되었다. 이것은, 출력 범프 영역(4)의 폭 방향에 걸친 압력 구배가 평균화되어, 출력 범프열(3A)의 각 출력 범프(3)에 있어서도 충분한 압박력으로 압입할 수 있었기 때문이다. On the other hand, as in Examples 7 to 11, when the distance (Δ) from the midpoint of the IC width (W/2) to the midpoint between the outside of the bump region (A+L2/2) is 0.3% to 3.5% of the IC width (W). , the conduction resistance became 1.0Ω or less in all of the output bump trains 3A, 3B, and 3C and the input bump train 5A. This is because the pressure gradient across the output bump region 4 in the width direction was averaged, and it was possible to press in with a sufficient pressing force also in each output bump 3 of the output bump row 3A.

1 : IC칩
2 : 실장면
2a : 일방의 측가장자리
2b : 타방의 측가장자리
3 : 출력 범프
4 : 출력 범프 영역
5 : 입력 범프
6 : 입력 범프 영역
10 : 이방성 도전 필름
11 : 박리 필름
12 : 도전성 입자
13 : 바인더 수지층
14 : 회로 기판
15 : 전극 단자
17 : 열압착 헤드 1: IC chip
2 : mounting surface
2a: one side edge
2b: side edge of the other side
3: output bump
4: output bump area
5 : input bump
6: input bump area
10: anisotropic conductive film
11: release film
12: conductive particles
13: binder resin layer
14: circuit board
15: electrode terminal
17: thermocompression head

Claims (8)

제 1 측가장자리를 따라 범프열이 형성된 사각형상의 제 1 범프 영역과,
상기 제 1 측가장자리에 대향하는 제 2 측가장자리를 따라 범프열이 형성된 사각형상의 제 2 범프 영역을 구비하고,
상기 제 1 범프 영역의 폭 방향의 거리가, 상기 제 2 범프 영역의 폭 방향의 거리보다 크고,
상기 제 1 범프 영역의 폭 방향의 외측과 상기 제 2 범프 영역의 폭 방향의 외측 사이의 범프 영역 외측 간 중점이, 상기 제 1 측가장자리와 상기 제 2 측가장자리 사이의 측가장자리 간 중점보다, 상기 제 2 측가장자리측에 존재하는 전자 부품. a quadrangular first bump region in which a row of bumps is formed along a first side edge;
a quadrangular second bump region in which a row of bumps is formed along a second side edge opposite to the first side edge;
a distance in the width direction of the first bump region is greater than a distance in the width direction of the second bump region;
The midpoint between the outer sides of the bump area between the outer side in the width direction of the first bump area and the outer side in the width direction of the second bump area is greater than the midpoint between the side edges between the first side edge and the second side edge. An electronic component present on the side of the second side edge. 제 1 항에 있어서,
상기 측가장자리 간 중점으로부터 상기 범프 영역 외측 간 중점까지의 거리가, 상기 제 1 측가장자리와 상기 제 2 측가장자리의 거리의 0.1％∼5.0％인 전자 부품.According to claim 1,
A distance from a midpoint between the side edges to a midpoint between the outer sides of the bump region is 0.1% to 5.0% of a distance between the first side edge and the second side edge. 제 1 항에 있어서,
상기 제 1 측가장자리와 상기 제 2 측가장자리의 거리에 대한 상기 제 1 범프 영역의 폭 방향의 거리와 상기 제 2 범프 영역의 폭 방향의 거리의 범프 영역 폭차의 비율이, 5％∼30％인 전자 부품. According to claim 1,
a ratio of a bump area width difference between a distance in the width direction of the first bump area and a distance in the width direction of the second bump area to the distance between the first side edge and the second side edge is 5% to 30%; Electronic parts. 제 1 항 내지 제 3 항 중 어느 한 항에 있어서,
상기 전자 부품의 실장면에는, 상기 제 1 범프 영역 및 상기 제 2 범프 영역 사이에, 더미 범프가 형성되어 있는 전자 부품.According to any one of claims 1 to 3,
A dummy bump is formed between the first bump region and the second bump region on a mounting surface of the electronic component. 제 1 항 내지 제 3 항 중 어느 한 항에 있어서,
상기 전자 부품은, IC칩인 전자 부품.According to any one of claims 1 to 3,
The electronic component is an IC chip. 제 1 측가장자리를 따라 범프열이 형성된 사각형상의 제 1 범프 영역과, 상기 제 1 측가장자리에 대향하는 제 2 측가장자리를 따라 범프열이 형성된 사각형상의 제 2 범프 영역을 구비하고, 상기 제 1 범프 영역의 폭 방향의 거리가, 상기 제 2 범프 영역의 폭 방향의 거리보다 크고, 상기 제 1 범프 영역의 폭 방향의 외측과 상기 제 2 범프 영역의 폭 방향의 외측 사이의 범프 영역 외측 간 중점이, 상기 제 1 측가장자리와 상기 제 2 측가장자리 사이의 측가장자리 간 중점보다, 상기 제 2 측가장자리측에 존재하는 전자 부품과,
상기 전자 부품이 접착제를 개재하여 접속된 회로 기판
을 구비하는 접속체. a quadrangular first bump area in which rows of bumps are formed along a first side edge; and second bump areas in a quadrangular shape in which rows of bumps are formed along a second side edge opposite to the first side edge, the first bump area comprising: A distance in the width direction of the region is greater than the distance in the width direction of the second bump region, and a midpoint between the outside of the bump region between the outside of the first bump region in the width direction and the outside of the second bump region in the width direction is , an electronic component existing on the side of the second side edge relative to the midpoint between the side edges between the first side edge and the second side edge;
A circuit board to which the electronic components are connected via an adhesive
A connection body having a. 제 1 측가장자리를 따라 범프열이 형성된 사각형상의 제 1 범프 영역과, 상기 제 1 측가장자리에 대향하는 제 2 측가장자리를 따라 범프열이 형성된 사각형상의 제 2 범프 영역을 구비하고, 상기 제 1 범프 영역의 폭 방향의 거리가, 상기 제 2 범프 영역의 폭 방향의 거리보다 크고, 상기 제 1 범프 영역의 폭 방향의 외측과 상기 제 2 범프 영역의 폭 방향의 외측 사이의 범프 영역 외측 간 중점이, 상기 제 1 측가장자리와 상기 제 2 측가장자리 사이의 측가장자리 간 중점보다, 상기 제 2 측가장자리측에 존재하는 전자 부품을, 접착제를 개재하여 회로 기판 상에 배치하고,
가압 툴로 가압함으로써 상기 전자 부품을 상기 회로 기판 상에 접속하는 접속체의 제조 방법. a quadrangular first bump area in which rows of bumps are formed along a first side edge; and second bump areas in a quadrangular shape in which rows of bumps are formed along a second side edge opposite to the first side edge; A distance in the width direction of the region is greater than the distance in the width direction of the second bump region, and a midpoint between the outside of the bump region between the outside of the first bump region in the width direction and the outside of the second bump region in the width direction is , placing an electronic component on the circuit board with an adhesive interposed between the first side edge and the second side edge, the electronic component existing on the side of the second side edge relative to the midpoint between the side edges;
A method of manufacturing a connecting body in which the electronic component is connected on the circuit board by pressing with a pressing tool. 제 1 측가장자리를 따라 범프열이 형성된 사각형상의 제 1 범프 영역과, 상기 제 1 측가장자리에 대향하는 제 2 측가장자리를 따라 범프열이 형성된 사각형상의 제 2 범프 영역을 구비하고, 상기 제 1 범프 영역의 폭 방향의 거리가, 상기 제 2 범프 영역의 폭 방향의 거리보다 크고, 상기 제 1 범프 영역의 폭 방향의 외측과 상기 제 2 범프 영역의 폭 방향의 외측 사이의 범프 영역 외측 간 중점이, 상기 제 1 측가장자리와 상기 제 2 측가장자리 사이의 측가장자리 간 중점보다, 상기 제 2 측가장자리측에 존재하는 전자 부품을, 접착제를 개재하여 회로 기판 상에 배치하고,
가압 툴로 가압함으로써 상기 전자 부품을 상기 회로 기판 상에 접속하는 전자 부품의 접속 방법.a quadrangular first bump area in which rows of bumps are formed along a first side edge; and second bump areas in a quadrangular shape in which rows of bumps are formed along a second side edge opposite to the first side edge; A distance in the width direction of the region is greater than the distance in the width direction of the second bump region, and a midpoint between the outside of the bump region between the outside of the first bump region in the width direction and the outside of the second bump region in the width direction is , placing an electronic component on the circuit board with an adhesive interposed between the first side edge and the second side edge, the electronic component existing on the side of the second side edge relative to the midpoint between the side edges;
A method of connecting electronic components, wherein the electronic components are connected on the circuit board by pressing with a pressing tool.
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